ASIC Design using Organic Transistors

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27 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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i


ASIC Design using Organic Transistors


Submitted in partial fulfillment of the requirements


of the degree of


Doctor of Philosophy


by



Ramesh Raju Navan


(Roll No.

05407009)



S
uperviso
rs:


Prof. V. Ramgopal Rao


Prof.
M. Shojaei Baghini






Department of Electrical Engineering


INDIAN INSTITUTE OF
TECHNOLOGY BOMBAY, M
UMBAI


(2012)




ii


Abstract




This report summarizes
the

fabrication, characterization
,
mobility

enhancement

and
development of a novel
device and
circuit

simulation technique for organic
thin film
transistors (O
TFTs
).
In
this work we have mainly studied
s
olution processed poly (3
-
hexylthiophene) (P3HT)
and vacuum evaporated pentacene

based p
-
type OTFTs
.



T
he
f
i
rst part

of the work is

focused on the
mobility enhancement of OTFTs.

Several
methods of dielectric surface
treatments
were found favorable for organic layer and they were
compared with eac
h other. A novel procedure for o
ctadecyltrichlorosilane

(OTS) deposition
was explored and verified experimentally to give improved mobility

of pentacene OTFTs
.
OTS deposition on silicon dioxide and hafnium oxide w
ere

found to give
better
mobilit
y
compared to other methods tried.

We also demonstrated
mobility e
nhancement of P3HT p
-
type of organic transistors by dispersing
Z
inc
O
xide
(
ZnO
) nanostructures into it.
A
comparative picture is presented between these composite based and pristine P3HT
transistors. Our results indicate
s

more than 60%

mobility enhancement

in the composite
transistors compared to pristine ones.

However, there is still scope for further improvement in
terms of better dispersion of ZnO nanostructures
.


Due to lack of compact models for OTFTs we have used alternate approaches to
perform device and circuit simulations of OTFTs and they are discussed
as
second part of the
work.
One approach of circuit simulation of OTFTs was to extract equivalent
SPICE
(Simulation Program with Integrated Circuit Emphasis)
parameters of OTFTs with the help of
particle swarm optimization (PSO) algorithm. The extracted equivalent SPICE parameters are
used as a device model for SPICE based circuit simulations. Another
approach for OTFT
device simulation was done by use of ISE
-
TCAD (
Integrated Systems Engineering
-

Technology Computer Aided Design
) in it the device parameters for silicon were replaced by
those of organic semiconductor. The results obtained from device si
mulation procedure were
then used to generate the Look
-
up Tables (LUTs) of the organic devices. LUT of the OTFT
can also be directly obtained from the experimental data. LUT generated is used as a model
file in SEQUEL (
Solver for circuit EQuations with Use
r
-
defined ELements)
for simulating
circuits. Simulated results were verified experimentally.




iii


The third

part
deals with the
fabrication and optimization

of gate dielectric
s
.
Here we
have demonstrated organic field effect transistors (OFETs) with photo
-
patte
rnable, solution
processed
,

nanoparticle composite high
-
k gate dielectric layer. The dielectric layer consists of
Barium Titanate (BT) nanoparticles dispersed in SU
-
8, which makes it possible to use
solution
-
processable methods
.

The dielectric constant k o
f the nanoparticle composite films
can be tuned over a wide range by varying the concentration of BT particles, which enables
lower voltage operation possible with these composite gate dielectric films. OFETs with
P3HT as the semiconducting layer have been

demonstrated; it was found that the OFETs with
the nanocomposite dielectric layer show a significant improvement in the drive current yet
retaining the photopatternability, which is an advantage for circuit fabrication. The composite
being a high
-
k enable
s low voltage operation (

4

V) compared to pristine SU
-
8 as a gate
dielectric operating at high voltages (

40

V). Working organic transistors and inverters with a
high
-
k nanocomposite dielectric layer (k

>

13) with considerably lower leakage current have
b
een demonstrated.


In the last part,
a

new compact OTFT
-
based analog to digital converter

(A
DC
)

wa
s
designed and simulated using
LUT

based appro
ach in SEQUEL circuit simulator
.

T
he LUT
data wa
s obtained from f
abricated
P3HT
-
based OTFTs

with
the developed
high
-
k
photopatternable

gate
dielectric layer
.
The LUT simulation approach wa
s validated at the
circuit level using the measurements taken on fabricated OTFT
-
based inverter.
With the
limitation in yield and stability of P3HT
-
based components

c
ircuit
module
s were designed
with fewer transistors
.

Designing a differential architecture
makes it less sensitive to variation
of threshold voltage of input transistors
.
The

proposed

design and circuit

simulation

results
show a great promise for simulation and complex designing approach advantageous for
different
organic
electronic applications.


Keywords

-

o
rganic
s
emiconductors
,

OTFT,
pentacene
, P3HT, HfOx,

SAM, ZnO,
OTFT
circuit simulation,

signal
conditioning,
analog
to
digital
c
onverter
.




iv


Contents



Abstract

i
i


List of Figures

v
i


List of Tables

x
i
i


Abbreviation and
N
omenclature

x
ii
i

1

Introduction

1


1.1 Organic
S
emiconducting
M
aterials

3


1.2 Conduction
M
echanism
s

4


1.3 OTFT Device S
tructure and
Model

5


1.4 Circuit Simulation of OTFTs

8


1.5 Overview of the

Thesis

9




2

Organic Thin Film Transistors

Performance Parameters

12


2
.1 Introduction

12


2
.2 Factors Affecting Mobility

15



2
.2.1 Deposition Process

15



2
.2.2
Temperature

16



2
.2.3 Charge Trappings in Polymer

16



2
.2.4 Influence of Structural Imperfections in Polymer

17



2
.2.5 Surface Modification Technique

-

SAM

18



2
.2.6
Mobility Enhancement of Pentacene OTFT using SAM

23



2
.2.7
Mobility Enhancement of P3HT OTFT using
ZnO Nanostructures

34


2
.3 Controlling Threshold Voltage

45



2
.3.1 Factors affecting Threshold Voltage

46



2
.3.2 Metal
W
ork
F
unction
T
uning

48



2
.3.
3

Double
G
ate
S
tructures

48



2
.3.4 Self Assembled Monolayer

49



2
.3.5 Deliberate
I
nterface
T
rap
C
reation

50



2
.3.6 Threshold
V
oltage
T
uning of
P
entacene OTFTs using SAM

5
0


2
.4
Conclusion

59




3

Fabrication and
Simulation of P3HT and Pentacene OTFT and Circuits

60


3
.1 Introduction

60


3
.2 P3HT OTFT Devices and Inverters

61



3
.2.1 Fabrication and Characterization

61



3
.2.2 OTFT Simulation using SPICE

65



3
.2.3 Results and
Discussions

65


3
.3 Pentacene OTFT Devices and Inverters

66



3
.3.1 Fabrication and Characterization

66




v




3
.3.2 OTFT Simulation using LUT based Approach

70



3
.3.3 Results and Discussions

73


3
.4 Circuit Design Methodology

78



3
.4.1 Circuit Design Problems with OTFT Technology

79



3
.4.2 Bootstrap Inverter

79



3
.4.3 Bootstrapped Circuit Simulation

80



3
.4.4 Bootstrapped Circuit
Fabrication

83


3.5 Conclusion

85




4

Optimization of the Gate Dielectric

8
7


4.1 Introduction

8
7


4.2 Fabrication Procedure

8
7


4.3
Characterization Results

8
8



4.3.1 Silicon Nitride as Gate Dielectric

8
9



4.3.2 Hafnium Oxide as Gate Dielectric

8
9



4.3.3 Stacked Hafnium Oxide/Silicon Dioxideas gate dielectric

90



4.3.4 PMMA as Gate Dielectric

90


4.4
A Novel High
-
k (k > 40) Gate Dielectric

91



4.4.1
Introduction

91



4.4.2 Experiment

91



4.4.3
Results and Discussion

92


4.5 Solution Processed Photopatternable High
-
k Nanocomposite

Gate Dielectric

9
3



4.5.1
Introduction

9
3



4.5.2 Experiment

9
5


4.6 Conclusion

100




5

OTFT Circuit Design
and Simulation for Signal Conditioning Application

101


5.1 Introduction

101


5.2
Signal Conditioning Circuit

102



5.2.1 LUT based Simulation of High
-
k OTFT Device and Inverter Circuit

10
5



5.2.2

Analog to Digital Converter Design

10
7


5.3

Conclusion

1
10




6

Summary and
Future Work

1
11





References

11
5





List of Publications

12
6




vi


List of Figures


1.1

OTFT device configurations: (1) Bottom gate (a) Top
-
contact device (b
)
Bottom
-
contact device (2) Top
-
gate…………………………………….............



6

1.2

Structure of an all polymer transistor where source, drain and gate were printed
by inkjet technique, semiconducting and insulating layers were spin
coated/inkjet printed……………………………………………….....................



6

1.3

General flow showing optimized device fabrication steps and OTFT circuit
simulation approach……………………………………………………………
..



9

1.4

Illustration of the organization of the thesis…………………………….............

1
1

2.1

Typical electrical characteristic of a
p
-
channel OTFT device: (a) Output curve
and (b) transfer curve……………………………………………………………



13

2.2

Relation between grain size and mobility
…….
…………………………………


1
8

2.3

Formation of SAM on SiO
2
…...
………………………………………………...


1
9

2.4

Octadecyltrichlorosilane

structure……………………………………………....

20

2.5

Hexamethyldisilazane structure…………………………………………………

21

2.6

Porphine structure……….………………………………………………………

21


2.7

5
-
(4
-
Hydroxyphenyl)
-
10, 15, 20
-
tri (p
-
tolyl) porphyrin………………………...

22

2.8

Surface characterization based

on contact angle measurements………………...

23

2.9

Formation of hydroxyl phenyl porphyrin SAM on SiO
2
………………………..

26

2.10

AFM surface images of (a)
bare

s
ilicon
d
ioxide
(SiO
2
) surface (b) HMDS
SAM on SiO
2

(c) OTS SAM on SiO
2

(d) Piranha + OTS SAM on SiO
2
……….



27


2.11

Top
-
contact bottom
-
gate OTFT structure……………………………………….


28

2.1
2

Comparison plots with and without SAM………………………………………

2
9

2.1
3

Top
-
contact bottom
-
gate OTFT structure……………………………………….


31

2.1
4

Comparison plots with and without SAM………………………………………


32

2.1
5

Schematic of all
-
p type organic inverter with enhancement mode driver (M1)
and Load (M2) an
d inverter cross
-
sectional view……………………………….


33




vii


2.1
6

Inverter DC characteristics (V
DD

= 4 V) of organic inverter with and without
OTS SAM on sputtered
HfO
x

as gate dielectric and dimensions (W/L)
M1
=
24850 μm/50 μm and (W/L)
M2
= 5050 μm/50 μm, respectively………………...




34

2.17

Vapor
-
Liquid
-
Solid apparatus used for the growth of zinc oxide

nanostructures…………………………………………………………………...



36

2.18

Scanning e
lectron
m
icrographs of the wool
-
like structures grown in the high
temperature zone in a Vapor Liquid
-
Solid (VLS) Process……………………...



36

2.19

Cross
-
sectional view of the P3HT/ZnO

nanocomposite transistor considered in
this work……………………………………………………………………….
..



38

2.20

Comparison of typical (a) output characteristics, gate voltage is different for
each curve, varied from 0

V to
-
40

V in steps of
-
5

V (b) transfer
characteristics, drain Voltage is
-
40

V of transistors based on pristine P3HT
and ZnO/P3HT
composit
e transistors…………………………………………...





38

2.21

(a) SEM and (b) TEM images of ZnO

nanorods grown for 1.5 h by a simple
one
-
step chemical approach. A SAED pattern of ZnO

nanorods is shown as the
insets of the TEM images

..............................................................................




40

2.22

(a) Cross
-
sectional view of the P3HT/ZnO

nanocomposite
based bottom
contact organic fi
e
l
d effect transistor. (b) Transfer (
I
DS
-
V
GS
) characteristics
comparison for d
ifferent concentration of ZnO

nanorods in P3HT/ZnO

nanocomposite where V
GS

is varied from +10 to
-
40 V & V
DS

=
-
40 V (c)
Output (I
DS
-
V
DS
) characteristics of pristine P3HT devices. Similarly (d) to (f)
show the output characteristics for 0.5 mg, 1 mg &

1.5 mg ZnO

nanorods
dispersed in a 1.5 mg of P3HT in chloroform solution where V
DS

is varied
from 0 to
-
40 V & V
GS

varied from 0 to
-
40 V in steps of
-
10 V, respectively
(W/L = 24300

µm

/65

µm
)
……

……………………………………………
...










42

2.23

Statistically
analyzed mobility data of pure and P3HT/ZnO (different ZnO
weight %) nanocomposite. The observed increase in mobility is mainly due to
the reduction of traps in P3HT
……
……………………………………………..




43

2.24

SEM image of ZnO

nanorods

(sample (a), sample (b) and sample (c))………...

44

2.25

XRD patterns of ZnO

nanorods (sample (a), sample (b) and sample (c))………

44

2.26

Transfer (I
DS
-
V
GS
) characteristics comparison for different aspect ratios of ZnO

nanorods in P3HT/ZnO

nanocomposite.
Here, V
GS

is varied from +10 to
-
30 V
& V
DS

=
-
30 V for aspect ratio of 15, 25 & 60 ZnO

nanorods dispersed in a 1.5
mg of P3HT in chloroform solution, respectively (W/L = 24000 µm/50
µm)
………………………………………………………………………............






45


2.27

Threshold
voltage dependence on polymer thickness [
7
1]……………………...


46

2.28

Change in threshold voltage with temperature [
3
0]……………………………..


47

2.29

Drain current vs. gate voltage stress [
3
0]………………………………………..

4
7




viii


2.30

Device geometry of dual gate structure [
7
2]…………………………………….

48

2.
31

Threshold voltage vs.
t
op
-
gate voltage [
7
2]……………………………………

4
8

2.
32

Drain current vs. gate voltage curves with and without OTS treatments [
7
3]…..

49

2.
33

Threshold Voltage vs. exposure time of treatment [
7
5]………………………...

50

2.
34

AFM surface images (a) SiO
2
(b) Porphyrin SAM on SiO
2
[
3
5]………………..

52

2.
35

UV
-
Vis spectrum of porphyrin in toluene and and SAM on SiO
2

[
3
5]…………

53

2.
36

Structure of OFET with SAM layer……………………………………………..

53

2.
37

Log |
I
DS
|
-
V
GS

curve for OFET with W = 4186 μm and L = 100 μm for oxide
thickness of 100 nm …………………………………………………………….



54

2.
38

L
og
|
I
DS
|

vs. V
GS

plot for devices with Al
2
O
3

as dielectric and W

=

2000 µm
and L

=

150 µm………………………………………………………
………….



54

2.
39

AFM images of (a) pentacene on Al
2
O
3

and (b) pentacene on SAM on Al
2
O
3


57

2.4
0

Id
-
Vg characteristics of OFET with and without SAM (copper

porphyrin)
…….

5
8

2
.
4
1

FTIR results of samples before and after plasma exposure……………………..


5
8

3.1

OTFT structure in

Bottom Gate Bottom contact configuration with patterned

gate (Al)
…………………………………………………………………
............



61

3.2

Output (I
DS
-
V
DS
), characteristics

of a typical fabricated OTFT with HfO
x

as
gate dielectric.
……………………………………………………………
……...



62

3.3

I
DS
-
V
GS
(triangles)
and I
DS
1/2
-
V
GS
(solid line)

plots of OTFT with HfO
x

gate
dielectric (W/L

=

15200

µm/20

µm)……………………………………………



6
2

3.4


Schematic of all
-
p type organic inverter with en
hancement mode driver (M1)
and l
oad (M2).
……………………………………………………………
…….



63

3.5

DC transfer characteristics of an organic inverter with (W /L)
M1

= 8400

µm/
100 µm and (W/L)

M2
= 2150

µm/100

µm………………………………
…..



6
4

3.6

Measured transient characteristics of organic inverter. The transient delays are
estimated to be roughly 10
ms…………………………………………………..



64

3.7

Comparison of measured vs. simulated I
DS

− V
DS

c
haracteristics OTFTs ……..
.

6
6

3.
8

Cross
-
section of the
patterned gate
fabricated OTFT
…………………………...

6
7

3.
9

Patterened gate OTFT with sputtered
-
SiO
x

(60nm) as gate dielectric and
patterned pentacene as semiconducting material.

….…………………………...


6
7




ix



3.1
0

Schematic of all
-
p type organic inverter with enhancement mode driver (M1)

and l
oad (M2) and inverter cross
-
sec
tional view
…….
……………………
……


6
8


3.
1
1

The measured DC and transient characteristics of an inverter with (W/L)
M1

=

24850 μm/50 μm and (W/L)
M2

= 3550 μm/50 μm.
……………………
………...



6
8

3.1
2

Output characteristics with

sputtered
-
HfO
x

(45nm) as gate dielectric
………….

6
9

3.
1
3

The measured DC and transient characteristics of an inverter with (W/L)
M1
=
24850 μm/50 μm and (W/L)

M2
= 5050 μm/50 μm
……………………………..



6
9

3.
1
4

Patterened gate OTFT with sputtered HfO
X

(65nm) as gate dielectric and
patterned pentacene

as semiconducting material with (W/L) = 24850 μm/50
μm



70

3.
1
5

The measured DC and transient characteristics of an inverter with (W/L)

M1
=
24850 μm/50 μm and (W/L)

M2
= 5050 μm/50 μm………………………………



70

3.
1
6

Cross
-
section of a bottom contact OTFT device drawn in MDRAW (ISE
-
TCAD tool) (a)
b
efore meshing (b)
a
fter meshing of the device
………………



7
2

3.
1
7

Measured vs.
s
imulated I
D


V
D
characteristics for OTFTs fabricate
d (data
scaled to width W=1μm)
…………………………………………………...
........



7
4

3.
1
8

(a) DC transfer characteristics and (b)
t
ransient response of the simulated all p
-
type enhancement mode organic inverter for V
DD
= 5 V
.
Inset shows the
schematic of Inverter
……
.
……………………………………
………………




7
5

3.
1
9

(a)
Two input NAND gate with only p
-
type transistors gate

(b)
s
imulated
characteristics
……………………………………………………………………



7
6

3.
2
0

(a) Two input NOR gate with only p
-
type transistors gate

(b)
s
imulated
characteristics
……………………………………………………………………



7
6

3.
2
1

Output
characteristics of a 5
-
stage simulated ring oscillator
……………………


7
7

3.
2
2

Measured vs. simulated output characteristics for OTFTs
……………………...

7
7

3.
2
3

(a) P
-
type OTFT
i
nverter and (b) Transient response of the simulated p
-
type
enhancement
-
mode organic
inverter for V
DD

= 4 V
…………………………….



7
8

3.
2
4

Bootstrapped inverter.
…………………………………………………………...

7
9

3.
2
5

Comparison of measured vs. simulated I
DS

− V
DS

c
haracteristics OTFTs (W/L

=

500

μ
m
/150

μ
m
)
…………………………………………………………
...
.....



81

3.
2
6

S
hows the results of
transient simulation of p
-
type based

inverter circuit and p
-
type bootstrapped inverter
………………………………………………………



8
1

3.
2
7

S
hows the p
-
type based dynamic logic circuit

(a)
without and
(b)
with
bootstrap technique
……………………………………………………………...


82




x



3.
2
8

Plots for
p
-
type dynamic logic inverter with and without bootstrapping
……….


82

3.
2
9

(a) The schematic of bootstrap inverter circuit, (b) SEM picture o
f fabricated
bootstrap inverter.
(c) DC transfer characteristics of a fabricated bootstrapped
organic inverter. The

sweep rate of the input for DC characteristics of inverter
is 0.1

V/s. The dashed curve shows the output for a normal inverter with
identical transistors, (d) The transient response of the normal inverter and (e)
The transient response

of the bootstrapped

inverter [
8
2
]
………………………..







85

4.1

Bottom
-
gate top
-
contact OTFT using BDFO as gate dielectric
………………...


9
1

4.
2

Transistor characteristics (a)
d
rain current (I
D
) versus drain
-
source voltage
(V
DS
) (b)
d
rain current (I
D
S
) versus gate voltage (V
GS
) of
the OTFT with BDFO
as the gate dielectric……………………………………………………………..




9
3

4.
3

Effect of BT wt% on the thickness of the spin coated composite film.

(Inset
shows the structure of the MOS capacitor)………………………………
……...



9
6

4.
4

(a) Capacitance verses frequency plots for different concentration of BT
nanoparticles blended into the SU
-
8 dielectric films and
(b)
d
ependence of resistivi
ty and dielectric constant on BT wt%........................




9
6

4.
5

(a) Schematic cross
-
secti
on of bottom contact organic fi
e
l
d effect transistor
with a nanocomposite gate dielectric (b) & (c)
t
ransfer (
I
DS
-
V
GS
)

&
o
utput (I
DS
-
V
DS
) characteristics of
pristine SU
-
8 gate dielectric, and (d) &

(e)
t
ransfer

&

o
utput characteristics of composite SU
-
8 with 0.88 BT wt% gate dielectric

(W/L=24000

µm/50

µm)………………………………
…………
……………..






9
7

4.
6

Shows AFM images of (a) pristine SU
-
8 and (b) 0.88 BT wt% in SU
-
8/BT
nanocomposite…………………………………………………………………..



9
8

4.7

(a) Cross
-
sectional structure of the organic inverter after semiconductor layer
formation (b) Schematic of all p
-
type organic inverter with enhancement mode
driver (M1) and Load (M2), and (c) DC transfer
characteristics of a typical
organic inverter…………………………………………………………
……….





9
9

5.1

Signal conditioning block diagram……………………………………………...

102

5.2

Schematic cross
-
section of a bottom
-
gate
-
bottom contact
p
-
type OFET with
P3HT as its active material [122].
…………........................................................



102

5.3

Response of the OFET with radiation.…………………………………………..

103

5.4

Emulated radiation sensor and its result by simulation
…………………………

103

5.5

Transimpedance

amplifier (TIA) with sensor block and its response…………..

10
4

5.6

(a) Cross
-
section of OTFT device (b)
m
easured vs.
LUT
simulated output
characteristics for OTFTs……………………………………………………….



10
6




xi


5.7

(a) P
-
type OTFT
i
nverter
and (b)
t
ransient response of the
simulated p
-
type
enhancement
-
mode organic inverter for V
DD

= 4 V
…………………………….



10
7

5.8

(a) Differential inverter circuit using four
p
-
type transistors (b) LUT
-
based
simulation results of the switching characteristic of the inverter for higher
values of V
IN
, the output voltage tends to

saturate to

the threshold voltage of
M2
……………………………………………………………………………….





10
8

5.9

Block diagram of the ADC circuit synthesized using the voltage divider and
the differential inverter circuit…………………………………………………..



10
9

5.10

(a) Cascade circuit of a differential and simple inverter for each single bit of
ADC (b)
s
imulation results of the ADC………………………………………...



10
9














xii


List of
Table
s


2.1

Parameter comparison for different conducting polymers
…….......


15

2.2

Contact
a
ngle
v
alues
after different surface treatments

on SiO
2

samples…………………………………………………………….



26

2.3

Roughness measurements after different surface treatments
……...


28

2.4

Mobility and threshold voltage comparison after different surface
treatments
………………………………………………………….



30

2.5

Contact angle values and roughness measurements after different
surface treatments on HfO
x

samples
……………………………….



3
1

2.6

Mobility, threshold voltage and I
on
/I
off

ratio comparison after
surface treatment
…………………………………………………..



3
3

2.7

Summary of comparative study of transistors based on
p
ristine
P3HT and P3HT/ZnO

nanocomposites
……………………………



39

2.8

Roughness measurements after
p
orphyrin
SAM treatment [
3
5]
…..


52

2.9

Various parameters for different
device structures
………………..


56

3
.1

Measured parameters for the fabricated device

with HfO
x

as gate
dielectric
…………………………………………………………...



63

3.2

SPICE parameters extracted

extracted

for P3HT OTFT…………..


66

3.3

Measured parameters forthe

fabricated device with SiO
x

as gate
dielectric
…………………………………………………………...



67

3
.
4

Measured parameters for the fabricated device
…………………....


69

3.5

Material parameters for
p
entacene
semiconductor [
97
]…………...

73


3.6

Defects location and density in
p
entacene
films. All defects are
G
aussian
and acceptor type. Location is w.r.t.
v
alence
band [
97
].
.



73

3.7

Device dimensions and measured parameters of the device
………


74

3.8

Spice para
meters extracted after matching
…………………...
........


74

3.9

Device
related parameters by

experiment
…………………………


80

3.10

SPICE parameters extracted after matching
……………………….

80

4.1

Summary of
d
ielectric
o
ptimization
……………………………...
..

90




xiii


Abbreviations and Nomenclature


ADC

-

Analog to Digital Converter

AFM

-

Atomic Force
Microscopy

Al
2
O
3

-

Aluminum oxide

Al

-

Aluminium

Au

-

Gold

BDFO

-

Bi
0.7
Dy0
.3
FeO
3

BEOL

-

Back End Of Line

B
GBC

-

Bottom Gate Bottom
Contact

BGTC

-

Bottom
-
Gate Top
-
Contact

BT

-

Bar
ium

Titanate

CNT

-

Carbon Nanotubes

Cr

-

Chromium

CuPc

-

C
opper phthalocyanine

CV

-

Capacitance
-
Voltage

FTIR

-

Fourier T
ransform
I
nfrared
S
pectroscopy

HfO
x

-

Hafnium oxide

HMDS

-

Hexamethyldisilazane.

HMTA

-

H
examethylenetetramine

HOMO

-

Highest Occupied Molecular Orbital

ICPCVD

-

Inductively Coupled Plasma Chemical Vapor Deposition

IGFET

-

I
nsulated
G
ate
F
ield
-
E
ffect
T
ransistor

IPA

-

Isopropyl A
lcohol

ITO

-

Indium Tin Oxide

IV

-

Current
-
Voltage

LPCVD

-

Low
-
Pressure
Chemical Vapor Deposition

LUMO

-

Lowest Unoccupied Molecular Orbital

LUT

-

Look
-
up Table

MIS

-

Metal Insulator S
emiconductor

MOS

-

Metal

Oxide Semiconductor




xiv


MOCVD

-

Metal

organic Chemical Vapor Deposition

MTR

-

Multiple Traps and Release

NTCDA

-

1
,4,5,8
-
naphthalene tetracarboxylicdianhydride

NTCDI

-

1,4,5,8
-
naphthalene tetracarboxylicdiimide

OFET

-

Organic
Field Effect

T
ransistors

OLED

-

Organic Light Emitting Diodes

OPVD

-

Organic Photovoltaic Diodes

OTFT

-

Organic Thin Film
T
ransistors

OTS

-

Octadecyltrichlorosilane

P3HT

-

poly (3
-
hexylthiophene)

PEB

-

Post exposure bake

PLD

-

Pulsed Laser Deposition

PMMA

-

Polymethyl Methacrylate

PSO

-

Particle Swarm O
ptimization

PTCDA

-

P
erlenetetracarboxylic

D
ianhydride

PVD

-

Physical Vapor Deposition

RCA

-

Radio Corporation of America

RFID

-

Radio
-
frequency
identification

RT

-

Room temperature

RTA

-

Rapid
T
hermal
A
nnealing

S

-

Subthreshold Swing

SAED

-

S
elected
A
rea
Electron D
i
ffraction

SAM

-

Self
-
Assembled Monolayer


SEM

-

Scanning Electron Micrographs

SiN
x

-

Silicon Nitride

SEQUEL

-

Solver for circuit EQuations with User
-
defined Elements

SiO
2

-

Silicon dioxide

SPICE

-

Simulation Program with Integrated Circuit Emphasis

TCNNQ

-

11,11,12,12
-
tetracyanonaphtho
-
2,6
-
quinodimethane

TDEAH

-

T
etrakis

D
iethylamido

H
afnium

TEM

-

T
ransmission
E
lect
ron M
icroscope

TGBC

-

Top
-
Gate Bottom
-
Contact




xv


Ti

-

Titanium

TIA

-

Transimpedance

A
mplifier

VLS

-

Vapor
-
Liquid
-
Solid

VRH

-

Variable Range Hopping

XRD

-

X
-
R
ay
D
iffraction

VLSI

-

Very Large Scale Integration

UV
-
Vis

-

Ultraviolet
-
V
isible

ZnCl
3

-

Zinc Chloride

ZnO

-

Zinc Oxide

μ

-

Mobility

C
OX

-

Gate Oxide Capacitance

W

-

Channel Width

L

-

Channel Length

I
DS

-

Drain source current

V
GS

-

Gate Source Voltage

V
D
S

-

Drain Source Voltage

V
T

-

Threshold Voltage

V
TO

-

Turn
-
on/onset Voltage

V
IN

-

Input voltage of inverter

V
OUT

-

Output voltage of inverter

V
DD

-

Supply Voltage of inverter