IAR Systems Day - ARM Tech Con 2010

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2 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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IAR Systems
Day
-

ARM
Tech Con 2010


10:30am
-

11:20 am

ARM Microcontroller Debug and Trace Infrastructure

Rob
Cosaro
, NXP and Anders Lundgren, IAR
Systems


11:30am
-

12:20 pm

Taking Trace to the Next Level

Shane Titus, SEGGER and Lotta Frimanson IAR
Systems


2:30pm
-

3:20 pm

Important Technology Factors for Energy
Efficient

Microcontroller Design

Raman Sharma, Energy Micro and Anders Lundgren, IAR
Systems


3:30pm
-

4:20pm

Debugging in the Power Domain

Lotta Frimanson, IAR Systems and Anders Lundgren, IAR
Systems


4:30pm
-

5:20pm

The
Inefficiency
of C++, Fact or Fiction?

Anders
Lundgren, IAR Systems

Who is IAR Systems?


IAR Embedded Workbench


IAR
visualSTATE


IAR J
-
Link & J
-
Trace


IAR
KickStart

kits



World
-
leading provider of software tools for embedded
systems


Founded in 1983 in by computer scientist
Anders
Rundgren


Headquarter in Uppsala, Sweden


Strong
Customer Base with more than 10 000 licenses
with support agreements

Product portfolio

What is up with Trace?

Debug and trace capabilities on NXP's ARM microcontrollers


Outline

Introduction

Debug and trace options on various cores

Implementations on NXP microcontrollers.

Conclusion


4

Debug



Identify and remove errors from (computer hardware or software):


As a Verb:



Real time systems are the worst to debug



As a Noun:



software debugging


Detect and remove concealed microphones from (an area)

Remove insects from (something), especially with a pesticide



5

Terminology



Start stop debug


break points (Hardware/Software)



watch points (Hardware/Software)

Trace


Instruction trace


Records instructions executed


Data trace


Records data movement



6

What is this?

7


8

Emulators did everything

Start
-
stop debugging

Instruction trace

Data trace


Why not use emulators then


Needed separate
bondout

chip


Hard to manage different package
optios


Limit on speed


Expensive tools




9

Process Technology is changing everything

0.35u

0.18u

0.14u

0.09u

LPC1100 Debug



Start stop debug


4 Breakpoints


2
Watchpoints


Can read and write variables on a running core



10

LPC1300 Debug



Start stop debug

(DWT, DAP)


8 breakpoints


6 for instruction


2 for Data


2
Watchpoints

Serial wire trace SWO

(ITM, TPIU)


Pseudo Instruction trace


Data trace on
watchpoints





11

TPIU block diagram





12

LPC1700 Debug



Start stop debug

(DWT, DAP)


8 breakpoints


6 for instruction


2 for Data


2
Watchpoints

Serial wire trace SWO

(ITM, TPIU)


Pseudo Instruction trace


Data trace on
watchpoints

ETM


Full trace


Clock and 4 data pins







13

What is ETB



Embedded trace buffers

On board RAM that Stores trace data

The good


No speed restrictions


No pins required (Except for debug interface)

The bad


Limited trace


Dedicated RAM

LPC3250 has ETB


2k x 24 (6kBytes) dedicated ETB memory


No trace pins








14

LPC1800 Debug



Start stop debug

(DWT, DAP)


8 breakpoints


6 for instruction


2 for Data


2
Watchpoints

Serial wire trace SWO

(ITM, TPIU)


Pseudo Instruction trace


Data trace on
watchpoints

ETM


Full trace


Clock and 4 data pins

ETB


16K of embedded trace buffer


Accessed through debug interface







15

Summary

NXP includes full instruction trace on LPC1800 through the LPC1700

families

Serial wire trace on all M3 devices

Trace helps solve complex debug problems faster

Tools are getting cheaper. Silicon area is not an issue

USE TRACE
to make debugging easier

16

17

Agenda


ETB trace capabilities on ARM9


Demonstration


Trace capabilities on
Cortex
-
M3

ETB


trace buffer on
-
chip

21

ETB Trace functionality in the C
-
SPY debugger


ETB (Embedded Trace Buffer)

o
High speed real
-
time on
-
chip trace buffer

o
Small size buffer


a few Kbytes (6 Kbyte on LPC3250),
still very useful.

o
Visibility of the actual application execution flow in the
IAR C
-
SPY debugger

o
Interfaces with IAR J
-
Link for ARM




ETB trace capabilities on ARM9


Demonstration


Trace capabilities on
Cortex
-
M3

Agenda

Demonstration setup

23

NXP LPC3250


24

Demonstration


ETB trace capabilities on ARM9


Demonstration


Trace capabilities on
Cortex
-
M3

Agenda

ARM core comparison


debugger perspective

N
ot all cores are equal!

ARM7

ARM9

CM0

CM3

CM4

CR4

JTAG

X

X

(X)

X

X

X

SWD

(X)

X

X

SWO

X

X

breakpoints

2

2

≤ 4

6

6

4

watchpoints (DWT)

≤ 2

4

4

8

ITM

X

X

ETM

*

*

*

*

*

ETB

*

*

*

*

*

*) optional

27

Trace capabilities on Cortex
-
M3


ITM (Instrumentation Trace
Macrocell
)

o
Low speed real
-
time trace port

o
Event trace

o
Interfaces with IAR J
-
Link


ETM (Embedded Trace
Macrocell
)

o
High speed real
-
time trace port

o
Visibility of the actual application execution flow in the
IAR C
-
SPY debugger

o
Interfaces with IAR J
-
Trace for Cortex
-
M3



Cortex
-
M3/M4 debug architecture

ETM optional


Data
Watchpoint

and Trace


This unit provides a set of functions that collect
information from the system buses and generates
events to the ITM/ETM units


4
watchpoints

Four independent comparators that can generate
events depending on

o
address match

o
data value


A watch point event can

o
break the core (data breakpoint)

o
trigger an ITM packet (data
watchpoint

log)

o
trigger the ETM


Interrupt trace

o
One ITM packet for each interrupt activity




Instrumentation Trace
Macrocell


Software trace

The ITM implements software triggers to
generate ITM packets by application control

o
32 channels are available

o
each with its own dedicated IO port that can
be written by the application to generate an
ITM packet that can be picked up by the
debugger in
real
-
time




Time stamping

The ITM is also the formatter for events
originating from the DWT. It packetizes the events
and optionally timestamps them

Embedded Trace
Macrocell


Instruction trace

o
Optional unit that may or may not be present
depending on the choice made by the chip
designer

o
Provides high bandwidth instruction trace data
on a dedicated 4
-
bit high speed trace bus

o
Special trace hardware is required to enable a
debugger to receive the ETM trace data, for
example the IAR J
-
Trace for Cortex
-
M probe.

o
Data accesses are not traced.

o
Cycle accuracy is implementation defined. As
of today there seems to be no Cortex
-
M3/M4
with cycle accuracy.


Embedded Trace
Macrocell


Bandwidth is limited

o
4
-
bits at CPUCLK is not sufficient to capture
all executed instructions.

o
Compression is needed.


The compressed trace stream

o
A
-
sync (alignment sync)

o
I
-
sync (instruction sync)

o
Branch address

o
Trigger

o
Exception entry

o
Exception exit

o
P
-
header (conditional instruction)

o
Cycle count


Debug Access Port


SWD/SWO

(Serial Wire Debug / Serial Wire Output)

Required mode to enable the SWO pin and thus
the full power of the DWT and ITM.

SWO is a serial high speed signal that transmits
ITM packets



Trace port

Optional 4
-
bit high speed trace port to output
ETM instruction trace data

Cortex
-
M3/M4 debug architecture

ETM optional


Thank You!