Circuit Level QCA Design

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1 Δεκ 2013 (πριν από 3 χρόνια και 8 μήνες)

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Bayesian Macromodeling for
Circuit Level QCA Design

Saket Srivastava and Sanjukta Bhanja

Department of Electrical Engineering

University of South Florida, Tampa


IEEE
-
Nano2006

Table of Contents


Purpose of this work


Overview of Quantum
-
Dot Cellular Automata


Overview of Bayesian Modeling


Layout Level Bayesian Modeling


Bayesian Macro modeling


Thermal Studies with Macro models


Circuit Level Modeling


Experimental Results


Conclusion

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Purpose of this work


Fast Bayesian Computing Model.


Abstracts the behavior of circuit components in QCA
design using Probabilistic Macromodeling.


Quick Estimation and Comparison of Quantum
Mechanical Quantities in QCA architecture at Layout
level and Circuit level.


Directly models the quantum mechanical steady state
probabilities at a hierarchical level.


Can be used to identify weak spots in the design in
the early design process, at the circuit level itself.

IEEE
-
Nano2006

Prior Work


S. Henderson, E. Johnson, J Janulis, and P. Tougaw,
“incorporating standard cmos design process methodologies into
the QCA logic design process”, IEEE Transactions on
Nanotechnology, vol.3, pp. 2
-
9, March 2004.

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Nano2006

Quick Overview

-

Quantum
-
Dot Cellular Automata


In a QCA cell two electrons occupy diagonally opposite dots in
the cell due to
mutual repulsion

of like charges.




A QCA cell can be in any
one of the two possible states

depending on the polarization of charges in the cell.


P = +1

P =
-

1

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Nano2006

Quick Overview

-

Quantum
-
Dot Cellular Automata


Electrostatic Interaction
between charges in two QCA Cells is
given as:


P = +1

P =
-

1

E
kink
= E
opp. polarization



E
same
polarization


This interaction is determines the
kink energy

between two cells.


Kink energy

is the is the Energy cost of two neighboring cells
having opposite polarization.


P = +1


P = +1

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Quick Overview
-

Bayesian Modeling


Bayesian Network

is a DAG
in which:


Nodes:

Random variables


Links
:

Causal dependencies amongst
random variables.

General representation:

Minimal factored Joint Probability
Distribution function:

Joint Probability Distribution function:

(a) QCA Majority Gate



Each Node has a
Conditional
Probability Table

(CPT) that quantifies
the effect of parents on that node.

(b) Bayesian model

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Nano2006

Quick Overview
-

Bayesian Modeling


The steady state polarization

of a QCA cell is obtained from the
Hamiltonian matrix using Hartree approximation and is given by:

E
k
is the kink energy.

γ

is the tunneling energy.

f
i

is the geometric distance factor.


is the weighted sum of
neighborhood polarizations.

ρ
ss

is the steady state polarization.


P

The probabilities of observing the system in each of the two states
is given as:

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Nano2006

Layout Level Bayesian Model of Cell
Arrangements


We then determine the parent and child nodes of each QCA cell.


Each QCA cell is represented as a random variable (node) taking on two possible
values.


Conditional Probabilities for each cell (node) is then given by:

where:

and

also known as Rabbi frequency.

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Nano2006

Bayesian Macro modeling


A
macromodel

is a functional block containing a small number of cells.



The macromodels of different circuit elements are the conditional probability of
output cells given the values of the input cells.



It can be obtained by marginalizing the joint probability distribution of those cells
over all the remaining cells in a layout.



For example if a macromodel block contains three cells (x
i
,x
j

and x
k
) out of
n
cells in
a layout, then its joint probability is obtained by:

is the joint probability distribution
over all n cells in a layout


where:


To compute the marginal probabilities for each macromodel, we first transform the
DAG into a junction tree of cliques and then the marginal probabilities are calculated
using local message passing between cliques.

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Nano2006

Bayesian Macro modeling

Figure:

Validation of the Bayesian network modeling of
QCA circuits with Hartree
Fock approximation based
coherence vector
based quantum mechanical simulation of
same circuit. Probabilities of correct output are compared
for basic circuit elements.

Symbol

Macromodel

MAJ

Simple Majority

CM

Clocked Majority

INV

Inverter

LINE

Line

IC

Inverter Chain

CO

Corner

ET

Even Tap

OT

Odd Tap

CB

Crossbar

AND

And Gate

OR

Or Gate

Table 1:
Abbreviations for Macromodel
blocks used in the circuit design of Adder
-
1
and Adder
-
2.

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Thermal Studies with Macromodels

Macromodel

QCA Layout

Bayesian Model

Block Diagram

Thermal Behavior

(a) Majority
Gate

1 clock zone

3 inputs

1 output

(a) Clocked
Majority Gate

2 clock zones

3 inputs

1 output

(a) Inverter

1 clock zone

1 input

1 output

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Nano2006

Thermal Studies with Macromodels



As the Temperature increases, the
polarization probability

at
the output node decreases.



Thermal behavior is also
dependent on the input vector set
.



A clocked majority gate consists of two clocking zones as it has
been seen that
circuit reliability increases

when majority gates
are clocked separately from the outputs.


This is done in order to
synchronize the input signals

reaching
the majority gate irrespective of the path length they have
traversed.


Larger number of cells in clocked majority lead to
overall
increased uncertainty

that accounts for a larger drop in
polarization at the output node at higher temperature.

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Nano2006

Thermal Studies with Macromodels

Macromodel

QCA Layout

Bayesian Model

Block Diagram

Thermal Behavior

(a) Majority
Gate

1 clock zone

3 inputs

1 output

(a) Clocked
Majority Gate

2 clock zones

3 inputs

1 output

(a) Inverter

1 clock zone

1 input

1 output

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Circuit Level Modeling



A NAND Gate Example

AND

INV

LINE

A

B

Out

A

B

Out


The QCA layout

of a NAND gate
consists of a Majority gate with one fixed
cell, an Inverter and a Line and in three
clock zones.


The Macromodel circuit

of a NAND
gate is modeled using the macromodel
blocks of an AND gate, an Inverter and a
Line.


A Bayesian network
of the macromodel
circuit is then formed.

A

B

Out


A QCA layout Bayesian model
is also
developed.


The two models

are then studied and a
compared for output node polarization at
different temperatures.

Out

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Nano2006

Circuit Level Modeling


Full Adder
-
2

QCA layout of Adder
-
2

Bayesian network for of Adder
-
2 layout

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Nano2006

Circuit Level Modeling


Full Adder
-
2

Macromodel block design of Adder
-
2

Bayesian model for macromodel circuit design

of Adder
-
2

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Nano2006

Circuit Level Modeling


Full Adder
-
2

Probability of correct output for sum and carry of Adder
2 based on the layout
level

Bayesian net model and the circuit level macromodel, at different temperatures, for
different inputs
(a)

(0,0,0)
(b)

(0,0,1)
(c)

(0,1,0)
(d)

(0,1,1).

(a)

(d)

(c)

(b)

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Circuit Level Modeling


2x2 Multiplier

Macromodel block design of 2x2 Multiplier

QCA layout of 2x2 Multiplier

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Nano2006

Circuit Level Modeling


2x2 Multiplier

Bayesian model for macromodel circuit design of 2x2 Multiplier

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Nano2006

Circuit Level Modeling


2x2 Multiplier

Probability of correct output at the four output nodes of 2x2 Multiplier circuit based on the
layout
-
level Bayesian net model and the circuit level macromodel, at different
temperatures, for different inputs (a)(1,0),(0,1) (b) (1,0),(1,1) (c) (1,1),(0,1) (d) (1,1),(1,1).

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Nano2006

Experimental Results

Table 3:

Comparison between simulation timing of a Full Adder circuits and 2x2
Multiplier circuit in
QCADesigner(QD)

and
Genie Bayesian Network(BN) Tool

for Full Layout and Macromodel Layout.

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Nano2006

Experimental Results


Error Modes


We compute the near
-
ground state configurations that
results in error in the output carry bit
C
out

of a QCA full
using both the layout and circuit level models.



We show the case for input vector set (1,0,0). The other
input vector sets have similar results.



We use red marker to point to the components that are
weak (high error probabilities) in both the layout and circuit
level.



If a node (a macromodel block) in macromodel circuit
layout is highly error prone for a given input set, then some
or all the QCA cells forming that macromodel block are
highly prone to error.



This indicates that weak spot in the design can be
identified early in the design process, at the circuit level
itself.


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Nano2006

Conclusion


We proposed an efficient
Bayesian Network based probabilistic macro modeling

strategy for QCA circuit.



This model can estimate cell polarizations, ground state probability, and lowest
-
energy error state probability, without the need for computationally expensive
quantum
-
mechanical computations.



We showed that the polarization estimates at layout and circuit levels are in good
agreement.



We illustrated a full adder design and a 2
-
bit multiplier design.



We showed that the weak spots at the layout level can be effectively identified at the
circuit level using this model.



One possible future direction of this work involves the extension of the BN model to
handle sequential logic.

IEEE
-
Nano2006

Thank You