Router Design Project
Table of Contents
Introduction and Project Objective
sco Router Hardware Schematic
Hardware Schematic Legend
Hardware Logical Flow
IOS Architectural Representation
IOS Architectural Analysis
Software Component Architecture
Software Architectural Representation
Software Architectural Analysis
Introduction & Project Objective
The Cisco 2500 Series Router are
a series of rack mount access routers typically
used to connect Ethernet networks
. For this project we have been given access to a Cisco
2514 router in class, for which we have been asked to pull apart, research and produce a
design project on, which dep
icts the individual roles of the Hardware, IOS and Software
used in router operation. This document contains the project deliverables which are a
reflection of the research done, along with the information gathered and interpreted from
class lectures. Whil
e all the information in the document may not be exact, the project is
meant to teach through hands on learning and research, how a routers internal
components work closely together to allow it to do its job.
The project will be broken up into three sect
ions which will discuss the three
different areas of the router; the hardware, IOS and Software and will conclude with a
requirements document for the CISCO 2500 Series router.
This model is useful to reference in this project, specifically because it can be broken
down to depict how it relates to the three different areas of this router project. T
different layers correlate to the different components of the routers operability as shown
Data Link Layer
Not part of TCP/IP
But useful for explanation purposes)
I found this TCP/IP Model useful when breaking down the different parts of the
Router and how these pa
rts function with one another. The Model will be referenced
throughout this project.
This Layer depicts the Software
running on the Router which
communicates with lower layers
through ports and sockets.
These layers work in unison
illustrate where the IOS on the router
performs its duties. The Service Access
Point here is Next Protocol Driven.
This layer in conjunction with the
physical hardware, is where hardware
components of the router which will be
discussed come into play. Interrupts are
key as there are no Service Access
Points at this level.
The hardware section of this Project will involve taking apart the Cisco 2514
router issued in class and reverse engineering it. This section wi
ll produce a schematic
drawing with a legend, depicting the different chips found inside of the box after careful
research. When we reference the TCP/IP Model on Page 2, we can see that this section of
the project involves delving into the Physical and Dat
Link layers of the model in terms
of actually physical signals and transmissions across the different components and how a
packet travels through them (Logical Flow).
One of the most important things to note when looking at the hardware
f this router is that it is has a shared memory implementation which can be
seen on the diagram below
This shared memory (aka Packet memory) implementation which was absent in Cisco
predecessors, is a significant upgrade which improves performance by he
lping assure I/O
throughput and is nearer to the interface modules to boost performance by minimizing the
average queuing delay of packets.
Routers use at least two interfaces to
connect to two separate domains or networks.
These different interfaces can be Ethernet, serial, fiber optic or other various types.
2. AUI 1
(Attachment Unit Interface)
3. Serial 0 Port
4. Serial 1 Port
configure and maintain a Cisco Router. A Console port is
similar to a PC’s serial port. A PC or similar device with an Ethernet interface and a
terminal emulation software is required to initially configure the router.
Special purpose port and functions much like a PC’s serial port. Used
to primarily connect a modem so the router can be managed remotely.
7/8. Flash Memory
Provides permanent storage of the IOS, backup configurations and
9. Primary Memory (DRAM)
Divided in Main Processor Memory and Shared I/O Memory
Main Processor Memory is used for Routing tables, running configuration
I/O Memory is used for temporary storage of packets in system buffers
Erasable, programmable, read
only memory used to permanently store the startup
diagnostic code and RxBoot. This memory and software residing inside of it can be
compared to the BIOS of a PC. Contents of ROM remain intact even when rou
is shut off. Boot ROM size is 2MB.
The Configuration File for the Router: “startup
config”, is stored here. This file
remains in this memory even when the router is shut down. This is similar to the
CMOS in a PC which
stores the internal configuration detected by BIOS during the
. Boot ROM Jumper
. ARM Microcontroller
2Mbits of on
chip SRAM and 4Mbits of Flash Memory.
. Analog to Digital Converter
10 bit, multi
Configuration Controller (Programmable Logic Device)
volatile (doesn’t loose data when board is powered down). Upon Power up,
this chip begins reading data from the flash memory.
17. CMOS Local Area Network Controller for Ethernet
Compatible with 802.3, on
board buffer management, network and packet error
reporting. Low power consumption. 48 Pins designed to simplify interfacing
a micro/mini computer to an 802.3 LAN.
18. Serial Communications Adapter
al purpose communications
Converts Parallel data to serial data for communication with other devices. Has 2
full duplex transceivers support synchronous and asynchronous communication.
Provides FIFO transmit and re
ceive buffers with 32 stages each.
19. CMOS Interface Controller 3 Drivers/3 Receivers.
These IC chips can be found in applications such as Modem interfaces, laptop
computers, UART interfaces and voice/data telephone interfaces.
0. Motorola 32 Bit Enhanced Embedded Controller (Processor)
32 Bit Bus, 20MHz Clock, 256 Bytes Data Cache
21. Power Supply
Used to keep the router running at its optimum Operating Environment of around
104 Degrees F While in Op
185 Degrees F Non
Dual asynchronous receiver/transmitter (DUART)
Chip communications device providing two independent full
asynchronous receiver/transmitter channels in a single package. Interfac
directly with microprocessors.
Designed for use in bidirectional synchronous communication between two buses.
25. V.35 Interface Receiver/Transmitter
This chip set consists of two chips, one performing a recei
ve function, and the other
performing a transmit function. Used in applications such as Modem Emulators,
High speed data transmission systems and matrix switches.
26. High Performance General Array Logic
27. High Performance EEPROM based, P
rogrammable Logic Device
This section of the project will involve looking at the ‘middle’ part of the TCP/IP
Model on page two, which involves the Internet and Transport layers
where the IOS
operates. The IOS consists of a few different parts which we will examine in this section
and the IOS Architectural drawing is based on notes taken in class which illustrate these
different components of the IOS.
The Cisco IOS design is bas
ed on the same principles used in the architecture of
any general operating system. The main task of the OS is to control the hardware
resources and provide a logical separation between hardware and software operational
functionality. The Cisco IOS however
, is designed specifically for efficient and fast
packet processing and forwarding.
The router IOS is process oriented. It is a multi
task cooperative operating system
and each process is responsible for giving the back the CPU to the next process. These
processes have 6 different states in their life
cycle which is shown in the diagram on the
S’ are much simpler and easier to understand than an OS on a PC. For
one, Routers do not create new data, they simply move it from one place to another
(through the processes generated)
and if they can’t figure out what to do with it, they
give it to the
The key to IOS design in a router is that if you know how much data is coming in,
and in turn, you know how much data needs to go back out, then what you need to take
into account in the design specification, is to do as much as possible to
not slow this
transitional process down.
IOS Architecture Analysis
The main function of the Cisco IOS is Interprocess Communication. The IOS is
responsible for sharing, coordinating and controlling communication betw
hardware and the router software. To do all of this, the IOS uses things such as tables,
maps and memory shares. The different components of the IOS as shown on the IOS
Architectural representation consist of these tables, maps and memory shares an
d they all
work in unison to make sure the router operates as it is programmed to.
The IOS Sits on top of the hardware. It interprets hardware signaling so as to
perform actions such as activate appropriate software and devices and captures, in a
e way in our network environment.
The IOS communicates with the hardware via interrupts. The IOS remains
inactive, until ‘woken up’ by an interrupt from the hardware to notify the IOS that there
is something in the buffer waiting to be processe
d. The processor then begins a process to
start doing the lookup in the routing and forwarding table. This lookup produces which
output interface the router needs to send out the packet, along with layer 2 information
needed to be written to the packet bef
ore it’s sent. The processor then will do the layer 2
rewrite, and move the packet to be sent out of the verified network media.
Communication between the IOS and upper level software in this entire process is
done through ports and sockets as op
posed to interrupts and is explained in the next
section of this project.
The IOS is, as said earlier, a Multi
tasking operating system. This particular Cisco
router’s IOS has a monolithic structure which means that it performs several different
parallel. However, one of the major points of the IOS’ operation which needs to
be pointed out is that because of this monolithic structure, the IOS lacks protection
mechanisms (such as the protection of separate processes’ memory) which means that
ough every process does have a separate memory block allocated for it, nothing
can stop a process from intruding into a memory block of another process,
the information which is kept inside these running processes called “context”. We
this context by
a stack frame
pushing all the variables to a single place
in memory so when you return to the process you pick up where you left off
IOS Component Functions
As shown in the IOS Architectural representation diagram, there ar
e a few
different components which make up the IOS. These components functions are explained
Shared piece of memory two processes can both see. This is a
mechanism which allows for
one software module to talk with another one, or fo
software module to talk to the buffer.
(E.g. 802.3 communicating with IP). This control
block can be seen as a memory map, and there is one single control block for every
running process not just one centralized unit. The control block makes sure mem
not erased (keeps ‘context’ in place).
Locks / Semaphores
Prevents the occurrence that two processes will converge on the
same spot in memory at the exact same time. These locks and semaphores make sure that
we do not write over the memory that
we want to preserve. This component puts
s them until a certain time (distinguished by timer)
being processed. These locks / semaphores can be seen as a locking protocol which uses
basic wait and signal techniques to s
olve important process synchronization problems.
Allows for one process to send a message directly to another. A
given process will call the function
to send a message to another process. The other
process will call the
function to wait for a message to arrive. This correlation of
functions is similar to locks and semaphores in that you cannot send two consecutive
messages, but rather you must wait for one message to be picked up first.
of the IOS holds important information in the form of
data structures such as the ARP cache, routing tables (1 per protocol which is configured
on the router) and configuration tables per port. These data structures can be arranged in
the form of arrays, l
inked lists, or the more complex adjacency matrices.
A specialized type of clock utilized by the IOS to control the sequence of the
processes running. These timers tell the IOS when to stop waiting so that it isn’t sitting
and using resources end
In between each of these components, there exists Glueware, which is a set of
routines that allow these components to interface with one another. More specifically,
Glueware is defined as
a type of software that can be used to "glue" or integ
software components and databases together, to form a seamless integrated system.
Internetworking with TCP/IP Volume II, Douglas Comer
Software Component Architecture
This final part of the project takes a look at the remaining layer on the TCP/IP
Model from page 2 (the Application layer)
as it relates to the final component of this
project. There are various different software implementations which can be configured to
run on the router, examples of which will be given later on.
It is important to realize at this point, that the project
was broken up into three
different sections, representing the three different parts of the router internals and how
each of them work together, to allow the router to perform its job. The software
applications running on the router were not something we w
ent in depth on in class,
however this diagram below from the text book
shows in good detail the three separate
sections and how they are interconnected:
Internetworking with TCP/IP Volume II, Douglas Comer
on top of the IOS, which is
responsible for handling the
Internet layer and Transport
in this example we
see that IP was used along
with TCP and an example of
UDP is also shown. The
hardware sits below the IOS
as discussed previously.
can see from this diagram that
after the more complex
operations the IOS performs,
the packet travels up into a
designated application to be
Software Component Architectural Analysis
As you can see from
the architectural representation on the previous page, there
are various software applications which can be configured to run on the Cisco router and
those listed in the diagram were just some examples including routing protocols and other
layer 3 applica
tions such as DNS, Email, etc.
One of the major points to take from the architecture of application software
running on the router, is how it communicates with the IOS which sits directly below
these running applications. Unlike the relationship between
the physical hardware and the
data link layer (which uses interrupts for process initialization), or the relationship
between the data link layer and Internet Protocol designation (which uses the control
block operating in the Service Access Point), the c
ommunication between the Transport
layer protocols such as TCP or UDP and the application software is done using the
system of Ports and Sockets.
Ports and Sockets are different because
they are a generic (no single vendor)
implementation of interproces
s communication that allows for two things:
vendor specific implementation i.e. D
ell and Unix can
The ports are represented not in
stem but across the system i.e If I specify that I
m using port 80, I
to have port 80 available.
The communication between the software applications and the IOS below it
which is using ports and sockets in the SAP between the two layers, is vendor
independent and the port addressing scheme used is used throughout th
e internet, driven
by a specified port number.
Overall description of the router and general thoughts on the routers design,
requirements it was trying to satisfy, target market and
performance limitations. This
requirements document serves as the last portion of the project, and was compiled after
all research and analysis was done. It serves as a reference point for general router
overview information on hardware and specifications
as well as thoughts by the author on
what was discovered after project completion.
Professor Calabrese, Network Engineering Students, Cisco,
Picture of the Router front view:
Picture of the Router Re
Summary of Router Interfaces
Primary memory (DRAM SIMMs)
1 MB (expandable to 4, 8, or 16 MB)
Shared (packet) memory
1 MB (
DRAM on the board)
code memory (Flash or PROMs)
4 MB (expandable)
Boot ROM memory
2 MB (expandable)
Nonvolatile RAM (NVRAM) memory
Dimensions (H x W x D)
1.75 x 17.5 x 10.56
one rack unit
10 lb. (4.5 kg)
Input voltage, AC power
100 to 240 VAC
1.2 to 0.6A
Input voltage, DC power
W, 40 to 72 VDC
1.5 to 1.0A
MHz Motorola 68EC030
32 to 104
F (0 to 40
40 to 185
40 to 85
The router which was used as the basis for this project;
the Cisco 2514, is a Cisco
2500 series router design and launched in 1993. These routers including the 2514, were a
series of 19” rack access routers used to connect Ethernet or token ring networks (the 2514
did not support token ring), via serial connecti
ons. The router was discontinued in 2001 and
replaced by Cisco's then newer series; the 2600. When the unit was first launched, software
running on them was proprietary to Cisco, however over time; uClinix (a Linux based
software) was introduced as a freew
are compatible with the box.
After researching this product, it became apparent that the target market for the router
was for use in home offices, or small to medium sized networks.
To start, this router featured the Motor
ola 68EC030 CISC processor which at the
time, according to research, was one of the best performing processors on the market. The
processor was a 232
bit, 0MHz model which was considered at the time to be powerful and
research showed that the same processo
r was used in various other technologies worth
mentioning such as Apple's Macintosh II, Sun Microsystems 3/80 Desktop workstation,
UNIX workstations and some laser printers.
The memory in this router was also ideal for its time period. The total memory on
board was 1MB of DRAM, which was able to be upgraded significantly if chosen. This
router comes out of the box with 1MB and as is, would probably best suit a home office;
however with upgrades of up to 16MB, it is clear this router could be capable of han
larger medium sized network.
The connections on this router include 2 Ethernet based AUI ports, 2 Serial ports, an
auxiliary and a console port. This router lacks a dedicated Token Ring Port which can be
found on other 2500 series routers however
the fact that a network management tool has been
incorporated on the box through the Aux and Console ports is worth noting. Older routers
lacked this feature which enabled quick configuration and troubleshooting if needed.
Other features that should be m
entioned include the routers aesthetic design which for
its time, again, was targeted towards a rack mounting system. It weighs heavily and has older
components which shouldn’t be moved around or shaken too much. The LED's positioned on
the back of the box
also stand out. This is a nice feature to have on any box so that users can
see if the port is up or down. The routers operating and non
operating temperatures can be
seen as irrelevant in terms of comparison to today's designs because of the simple fact
temperatures don’t change enough over such a short period of time.
Constraints / Design Flaws:
After the research was completed at the end of this project, it was easy to point
out some constraints or design limitations imposed by this router. While
research, it was common that other router models came up in search results, particularly
Cisco models on the vendor’s site. Taking note of some of these various other models,
particularly the newer ones, allowed for comparison in features and sp
Firstly, starting with the physical hardware, it should be noted that the box itself is
big and bulky and in turn, the board and its components are spread out over a rather large
surface area. This design results in slower tra
nsmission speeds than a router speed with
chips and busses that sit closer and more compact with one another. The Ethernet ports
are based over serial connections which is something you would not typically see in
today’s newer models and if this router was
to be tried today, it would be difficult to
implement. The single RJ
45 port was for configuration purposes and this would need to
be changed to comply with today’s standards.
On a security note, it can be seen when taking the router apart that the box h
large power supply accompanied by a single fan. Typically, technology improves over
time and I would be concerned with how sufficient this design would be in keeping the
box cool. Possibly adding another fan or incorporating better ventilation on th
would be an improvement.
Lastly, in terms of memory capacity, the out of the box standard should be enough
for home office or small network use however it should most certainly be upgraded if this
router were to be used over a larger, medium sized
After spending the greater part of the last few weeks researching this project,
many things were learned about the 2514 router and router internals as a whole. The three
different parts to this project proved challenging and frequen
tly, certain aspects were
unable to produce solid factual research. Most of the information in this project was
obtained from class notes and individual research however some aspects relied solely on
educated guesses. The box itself was an older model but
proved to do the job in getting to
become familiar with router internals and components. Obviously there are many things
that have changed in the time this router was manufactured however the same basic
concept of routing has remained the same. If there wa
s any aspect of this project I would
change it would be the amount of time and detail spent in class going over exactly what
was expected and resources to look for the information. Also, if there was any way of
obtaining a newer box to work on, this may al
so have proved beneficial because it would
allow for work to be done on more technologically advanced boxes which would be seen
in today’s work place. In Conclusion, I feel this project served its intended purpose and
helped establish a foundation for rout
er internal operations.