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CHAPTER 13
Heat Transfer in Electronic Equipment
AVRAMBARCOHEN
Department of Mechanical Engineering
University of Minnesota
Minneapolis,Minnesota
ABHAY A.WATWE and RAVI S.PRASHER
Intel Corporation
Chandler,Arizona
13.1 Introduction
13.1.1 Cooling requirements
History
Present and future
13.1.2 Thermal packaging goals
Preventing catastrophic failure
Achieving reliable operations
Lifecycle costs
13.1.3 Packaging levels
13.2 Thermal resistances
13.2.1 Introduction
13.2.2 Basic heat transfer modes
Conduction
Convection
Radiation
13.2.3 Chip package resistance
Internal resistance
External resistance
Flow resistance
Total resistance:singlechip packages
13.3 Lengthscale effects on thermophysical properties
13.3.1 Spreading resistance
13.3.2 Heat ﬂow across solid interfaces
Thermal contact resistance
Thermal boundary resistance
Interstitial materials
Thermal conductivity of particleladen systems
Effect of ﬁller concentration on mechanical strength
13.3.3 Firstorder transient effects
Lumped heat capacity
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Thermal wave propagation
Chip package transients
13.3.4 Heat ﬂow in printed circuit boards
Anisotropic conductivity
Thermal vias
Effect of trace layers
13.4 Convective phenomena in packaging
13.4.1 Printed circuit boards in natural convection
13.4.2 Optimumspacing
13.4.3 Printed circuit boards in forced convection
13.5 Jet impingement cooling
13.5.1 Introduction
13.5.2 Correlation
13.5.3 Firstorder trends
13.5.4 Figures of merit
13.5.5 General considerations for thermal–ﬂuid design
13.5.6 Impingement on heat sinks
13.6 Natural convection heat sinks
13.6.1 Empirical results
13.7 Phasechange phenomena
13.7.1 Heat pipes and vapor chambers
Alternative designs
13.7.2 Immersion cooling
13.8 Thermoelectric coolers
13.9 Chip temperature measurement
13.10 Summary
Nomenclature
References
13.1 INTRODUCTION
13.1.1 Cooling Requirements
History Despite the precipitous drop in transistor switching energy that has charac
terized the solidstate semiconductor revolution,the cooling requirements of micro
electronic components have not diminished.As the twentyﬁrst century begins,high
performance chip power dissipation exceeds 100 W,some three ordersofmagnitude
above the SSI (smallscale integration) chips of the early 1960s,and informed opin
ion suggests that a 150W chip will become reality within the ﬁrst decade of the
twentyﬁrst century.Thermal management is thus one of the key challenges in ad
vanced electronic packaging,and considerable improvement in thermal packaging
will be needed to exploit successfully the Moore’s lawacceleration in semiconductor
technology.
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In the early 1960s chip heat removal requirements for the 2 to 3mmSSI silicon
semiconductor devices were typically in the range 0.1 to 0.3 W.By the mid1980s,
increased chip transistor counts and functional densities pushed LSI (largescale
integration) ECL (emittercoupled logic) power dissipation to 5 Wfor 5mm chips
(BarCohen,1987).
Although historical reliability data for silicon bipolar chips,based largely on
military electronic sytems,had established a “traditional” upper limit of 110 to 125°C
on the junction temperature,in the 1980s reliability and performance considerations
led to a lower standard,65 to 85°C,in commercial applications,thus halving the
allowable temperature rise of the chip above the ambient 45°C.The resulting LSI chip
heat ﬂuxes,approaching 25 ×10
4
W/m
2
(25 W/cm
2
),combined with the lowered chip
temperatures,necessitated the development of highperformance cooling systems and
posed a formidable challenge to the electronic packaging community.
Mainframe computers of this era based on highspeed bipolar chips were charac
terized by watercooled multichip modules,with an effective thermal resistance of
1 to 2 K/W · cm
2
(BarCohen,1987).However,although slower,the lowerpower
CMOS (complementary metal oxide on silicon) VLSI (very large scale integration)
chips,with power dissipation often less than 1 Wacross a 10mmchip,were becom
ing the technology of choice for workstations and desktop computers.These chips,re
quiring effective thermal resistances some 25 times lower than the mainframe bipolar
chips,could often be cooled passively (conduction spreading and air natural convec
tion) and rarely required more than modest forcedconvection and simple aircooled
extended surface heat sinks.
In the mid1990s,the thirst of the marketplace for greater integratedcircuit speed
and functionality,along with growing onchip heating which accompanied lower
operating voltages and higher currents,pushed CMOS microprocessor chip power
dissipation to the range 15 to 30 Wand forced the use of ever more aggressive air
cooling technology.As the end of the decade approached,chips in highperformance
workstations were routinely dissipating in excess of 75 W,with heat ﬂuxes that were
once again approaching 25 ×10
4
W/m
2
.To facilitate continued air cooling of these
higherpower chips and in recognition of the vast reliability improvements in silicon
devices,the allowable junction temperatures in the ﬁnal years of the 1990s rose to
values close to 100°C in desktop computers and workstations.
Present and Future To understand the future trends in the cooling requirements
for microelectronic components,it is helpful to examine the consensus emerging
from industrywide “roadmapping” efforts,including the Semiconductor Industry
Association’s (SIA’s) National Technology Roadmap for Semiconductors:Technol
ogy Needs (1997) and National Electronics Manufacturing Institute’s (NEMI’s) Tech
nology Roadmap (1996).These trends are summarized in Table 13.1,where the
salient thermal and related parameters,starting with the 1999 state of the art and ex
tending to 2012,are classiﬁed by application categories.In the lowcost or commod
ity product category,including disk drives,displays,microcontrollers,boomboxes,
and video cassette recorders,power dissipation is very modest,and only incidental
cooling expenditures can be tolerated.In this category,today and for the foreseeable
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future,thermal management rarely involves more than reliance on buoyancyinduced
natural circulation of air,augmented perhaps by passive heat spreading.Operation
at an elevated chip temperature of typically 125°C in an anticipated internal ambi
ent temperature of 55°C,resulting in a driving force of 70°C,provides some com
pensation for the relatively high chiptoair thermal resistance associated with this
approach.
Similar constraints severely limit the options for today’s batteryoperated hand
held products,including PDAs (personal digital assistants) and cellular phones,where
clever use of heat spreaders generally makes it possible to maintain the 1 to 2 Winte
grated circuits (ICs) at temperatures at or below115°C.Signiﬁcantly,in this category,
thermal management capability is today in rough equilibriumwith the battery power
available for extended operation,but an anticipated doubling of the available battery
power by the late years of the current decade may well necessitate more aggressive
approaches.
Natural convection cooling is also generally the rule for memory devices.But
when many such DRAMs and/or SRAMs,each typically dissipating 1 W,are stacked
together or densely packed on a printed circuit board,forced convection is used to
keep these devices from exceeding their allowable temperature of approximately
100°C.Such techniques can be expected to be more broadly applied for thermal
management of future memory devices,dissipating,perhaps,so much as 2.5 W,by
the end of the decade.
During the 1990s,the automotive category claimed the “harsh environment” man
tle previously worn by “milspec” components.The elevated ambient temperatures
under the hood and elsewhere in a vehicle,reaching as high as 165°C,make it neces
sary for automotive ICs,dissipating 10 to 15 W,to operate reliably at temperatures as
high as 175°C.This category also includes equipment used in mining and resource ex
ploration and in the upper spectrumof military applications.The relatively small chip
size of 53 mm
2
in 1999,projected to growto just 77 mm
2
by 2012,and an anticipated
constant power dissipation of 14 W,result in chip heat ﬂuxes that are comparable to
those encountered in the most demanding,highperformance category.
However,due to the small allowable temperature difference for these components,
the automotive category poses the most demanding of electronic cooling require
ments.While a wide variety of heatspreading and aircooling strategies,for elevated
chip temperature operation,have been implemented successfully in this product cat
egory,development efforts are also addressing conventional temperature operation
based on the use of refrigerated cold plates.Throughout the 1990s,heatsinkassisted
air cooling was the primary thermal packaging approach for the cost/performance cat
egory,which included both desktop and notebook computers.Thermal management
of the microprocessors used in desktop computers often relied on clipattached or
adhesively bonded extruded aluminum heat sinks,cooled by remotely located fans.
But as the chip power reached 50 Wby the end of the decade,thermal packaging for
this product category required progressively more reﬁned designs as well as lower
thermalresistance interface materials.Returning to Table 13.1,it may be seen that
cost/performance chip heat ﬂuxes are forecasted to peak by 2006,at approximately
40%higher values than in 1999.
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Table 13.1 Thermal Characteristics of Current and Future Semiconductor Packages
Year of Commercialization
1999 2001 2003 2006 2012
Commodity
Power dissipation (W) n/a n/a n/a n/a n/a
Chip size (mm
2
) 53 56 59 65 77
Onchip frequency (MHz) 300 415 530 633 1044
Junction temperature (°C) 125 125 125 125 125
Ambient temperature 55 55 55 55 55
Pin count 40–236 40–277 40–325 40–413 40–666
Handheld
Power dissipation (W) 1.4 1.7 2 2.4 3.2
Chip size (mm
2
) 53 56 59 65 77
Heat ﬂux (W/cm
2
) 2.6 3.0 3.4 3.7 4.2
Onchip frequency (MHz) 300 415 530 633 1044
Junction temperature (°C) 115 115 115 115 115
Ambient temperature (°C) 55 55 55 55 55
Pin count 117–400 137–469 161–413 205–524 330–846
Memory (DRAM)
Power dissipation (W) 0.8 1.1 1.5 2 3
Chip size (mm
2
) 400 445 560 790 1580
Heat ﬂux (W/cm
2
) 0.20 0.25 0.27 0.25 0.19
Onchip frequency (MHz) 100 100 125 125 150
Bits/chip (mega) 1,000 4,000 16,000 256,000
Junction temperature (°C) 100 100 100 100 100
Ambient temperature 45 45 45 45 45
Pin count 30–82 34–96 36–113 40–143 48–231
Cost performance
Power dissipation (W) 48 61 75 96 109
Chip size (mm
2
) 340 285 430 520 750
Heat ﬂux (W/cm
2
) 13.5 15.8 17.4 18.5 14.5
Onchip frequency (MHz) 526 727 928 1108 1827
Junction temperature (°C) 100 100 100 100 100
Ambient temperature 45 45 45 45 45
Pin count 300–976 352–895 413–1093 524–1476 846–2690
High performance
Power dissipation (W) 88 108 129 160 174
Chip size (mm
2
) 340 385 430 520 750
Heat ﬂux (W/cm
2
) 25.9 28.1 30.0 30.7 23.2
Onchip frequency (MHz) 958 1570 1768 2075 3081
Transistor (MHz/cm
2
) 6 10 18 39 180
Junction temperature (°C) 100 100 100 100 100
Ambient temperature 45 45 45 45 45
Pin count 1991 1824 2228 3008 5480
Automotive
Power dissipation (W) 14 14 14 14 14
Chip size (mm
2
) 53 56 59 65 77
Heat ﬂux (W/cm
2
) 26.4 25.0 23.7 21.5 18.2
Onchip frequency (MHz) 150 150 200 200 250
Junction temperature (°C) 175 175 180 180 180
Ambient temperature 165 165 170 170 170
Pin Count 40–236 40–277 40–325 40–413 40–666
Source:Data fromNEMI (1996) and SIA (1997).
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In an attempt to minimize the performance gap between notebook and desktop
computers,fancooled heat sinks did begin to appear in notebook computers toward
the end of the 1990s.However,throughout much of this decade,battery power limi
tations made it necessary to harness naturally convecting air,circulating past lowﬁn
heat sinks and heat pipes,as well as metal cases heated by spreading,to provide the
requisite cooling for the 3 to 5W chips.In the coming years,advanced notebook
computers using modiﬁed cost/performance chips will pose extreme challenges to
the thermal management community.
In the late 1990s,under the inﬂuence of market forces,thermal management of
nearly all the products in the highperformance category devolved to the aggressive
use of air cooling,exploiting technology that was a natural outgrowth of the air
cooled multichip modules of the 1980s.By the end of the decade,a renaissance in
thermal packaging produced heat sinks for highend commercial workstations and
servers that were routinely dissipating 60 to 70 Wwith chip heat ﬂuxes of some 26
W/cm
2
.As may be seen in Table 13.1,the packaging community consensus suggests
that early in the second decade of the twentyﬁrst century,power dissipation will rise
to 175 Wfor chips operating at some 3 GHz.However,it is anticipated that chip area,
growing from 3.8 cm
2
to some 7.5 cm
2
,will keep pace with chip power dissipation
in the coming years,yielding chip heat ﬂuxes that increase only marginally above the
present values to approximately 30 W/cm
2
by 2006,before beginning a slowdecline
in later years.
13.1.2 Thermal Packaging Goals
PreventingCatastrophic Failure In today’s highperformance microelectronic
systems,catastrophic failure may be associated with an immediate and total loss
of electronic function and package integrity,or drastic,though reversible,deterio
ration in performance.The prevention of permanent as well as intermittent catas
trophic failure is the primary and foremost goal of electronics thermal management
and often requires the elimination of large temperature excursions.Excessive tem
peratures,inducing large thermomechanical stresses,may lead to excessive strain
and/or stress levels in the silicon,delamination of the die attach and heat sink or
spreader bond layer,as well as broken wire,solder,or gold bonds.Furthermore,ele
vated temperatures,which exceed the design speciﬁcation of the package,may result
in melting,vaporization,or even combustion of lowtemperature packaging mate
rials.Alternatively,unanticipated chip and package temperature variations beyond
the speciﬁed tolerance may lead to shifts in semiconductor behavior (e.g.,CMOS
switching frequency) or that of adjacent photonic (e.g.,emitted wavelength,conver
sion efﬁciency) or microwave components (e.g.,phase shift),as well as to structural
misalignment and signal delays that undermine the ability of the package to deliver
the requisite performance.Adetailed understanding of the catastrophic vulnerability
of the speciﬁed component(s) provides the basis for establishing the thermal manage
ment strategy for a particular package or product,including selection of the appropri
ate ﬂuid,heat transfer mode,and inlet coolant temperature required to meet design
speciﬁcations.
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Achieving Reliable Operations Following selection of the thermal packaging
strategy,attention can be turned to meeting the desired level of reliability and the
associated target failure rates of each component and subassembly.Individual solid
state electronic devices are inherently reliable.However,because a single microelec
tronic chip may include as many as 15 million transistors and 600 leads,and because
many tens of such components may be used in a single system,achieving failurefree
operation over the useful life of a product is a formidable challenge.The suppression
of thermally induced failures often requires adherence to strict limits on the temper
ature rise or fall relative to the ambient temperature and the minimization of spatial
and temporal temperature variations in a package.
The reliability of a systemis the probability that the systemwill meet the required
speciﬁcations for a given period of time.As an individual electronic component
contains no moving parts,it can often perform reliably for many years,especially
when operating at or near room temperature.In practice,integrated circuits operate
at temperatures substantially above ambient,and unfortunately,most electronic com
ponents are prone to failure fromprolonged exposure to these elevated temperatures.
This accelerated failure rate results from the interplay of numerous factors,includ
ing the consequences of thermal strain and stress in the bonding and encapsulation
materials,parasitic chemical reactions,dopant diffusion,and dielectric breakdown
(Pecht et al.,1992).Although accurate failure rate predictions defy simple correla
tions,under some conditions a modest 10 to 20°C increase in chip temperature can
double the component failure rate.Consequently,for many package categories,tem
perature is the strongest contributor to the loss of reliability.In such systems,thermal
management is critical to success of the electronic system.
LifeCycle Costs In the ﬁnal stages of thermal design of an electronic system,the
reliability,availability,and maintainability of the proposed thermal control alterna
tives must be evaluated and used to guide the ﬁnal technology and equipment choice.
It is the role of the packaging engineer to assure that the enhanced reliability of the
components,resulting fromlower operating temperature as well as the minimization
of spatial and temporal temperature variations,is sufﬁcient to compensate for the ad
ditional lifecycle cost and inherent failure rate of fans,pumps,heat pipes,interface
materials,and other elements of the cooling system.Successful thermal packaging
requires a judicious and insightful combination of materials and heat transfer mech
anisms to stabilize the component temperatures at an acceptable level.
13.1.3 Packaging Levels
To initiate the development of a thermal design for a speciﬁed electronic product,it is
ﬁrst necessary to deﬁne the relevant packaging level (see Fig.13.1).The commonly
accepted categorization places the chip package,which houses and protects the chip,
at the bottom of the packaging hierarchy (level 1).The printed circuit board (PCB),
which provides the means for chiptochip communication,constitutes level 2,while
the backplane or motherboard,which interconnects the printed circuit boards,is
termed level 3 packaging.The box,rack,or cabinet,that houses the entire system
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Figure 13.1 Electronic packaging levels.
is generally referred to as level 4.The primary thermal transport mechanisms and
commonly used heat removal techniques vary substantially fromone packaging level
to the next as the scale of the thermal transport phenomena shifts fromthe microscale
(or even nanoscale in future years) at level 1,to the mesoscale at level 2,and on to
the macroscale in packaging levels 3 and 4.
Level 1 thermal packaging is concerned primarily with conducting heat from the
chip to the package surface and then into the printed circuit board.At this pack
aging level,reduction in thermal resistance between the silicon die and the outer
surface of the package is the most effective way to lower the chip temperature.As
shown in Table 13.2,a variety of passive cooling techniques are available to reduce
the thermal resistance.For example,improved thermal performance can be obtained
by using dieattach adhesives,with diamond,silver,or other highconductivity ﬁller
material,thermal greases,and phasechange materials,which soften at the operat
ing temperature to conformbetter to the surface of the chip.Alternatively,attaching
metalplate heat spreaders to the chip,and using thermally enhanced molding com
pounds and embedded heat slugs [for plastic ball grid array (PBGA) and lead frame
packages],can also lead to beneﬁcial results.It is also quite common to attach heat
sinks to the surface of a package to create additional surface area for heat removal by
natural and/or forced convection.In very high power applications,it may be neces
sary to cool the chip directly by attachment to a heat pipe,by direct attachment of a
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TABLE 13.2 Thermal Management Techniques for Distinct Packaging Levels
Packaging Level Passive Cooling Techniques Active Cooling Techniques
Level 1:chip package Highconductivity adhesive Fans
Greases Air jet impingement
Phasechange materials Dielectric liquid
Highconductivity molding
compound
Thermoelectric cooler
Heat spreader
Heat slug
Heat sinks
Dielectric liquid immersion
Heat pipes
Level 2:PCB Thick power and ground
planes
Fans
Ducted air
Insulated metal substrates Dielectric liquids
Heat pipes Cold plates
Natural convection
Levels 3 + 4:module
and rack
Natural convection Ducted air
Heat pipes Airhandling system
Cold plates
Refrigeration systems
heat sink,by impingement of highvelocity air jets,or by immersion in a dielectric
liquid.
Heat removal at level 2 typically occurs both by conduction in the printed circuit
board and by convection to the ambient air.Use of printed circuit boards with thick,
highconductivity power and ground planes and/or embedded heat pipes provides
improved thermal spreading at this level of packaging.Use of electrically insulated
metal substrates can also be considered.Often,heat sinks are attached to the back
surface of the printed circuit board.In many airborne systems or in systems designed
for very harsh environments,convective cooling of the component is not possible;
instead,heat must be conducted to the edge of the printed circuit board.Attachment
of a heat sink or a heat exchanger at this edge then serves to remove the heat dissipated
by the components populating the printed circuit board or substrate.
As might be surmised from the frequent use of the term computer on a chip
or computer in a package,many of today’s electronic systems can be packaged
adequately at level 1 or 2.Heat sinks or ﬁnned surfaces protruding into the airstream
are often used at levels 1 and 2 to aid in the transfer of heat to the ambient air.
When levels 3 and 4 are present,thermal packaging generally invoves the use of
active thermal control measures such as airhandling systems,refrigeration systems,
or water pipes,heat exchangers,and pumps.Often,however,it is possible to cool the
module and/or rack by relying on natural circulation of the heated air.
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13.2 THERMAL RESISTANCES
13.2.1 Introduction
To determine the component temperatures and temperature gradients encountered in
the ﬂow of heat within electronic systems,it is necessary to deﬁne the relevant heat
transfer mechanisms and establish their governing relations.In a typical system,heat
removal from active regions of the microcircuit(s) or chip(s) may require the use
of several mechanisms,some operating in series and others in parallel,to transport
to the coolant or ultimate heat sink the heat generated.Practitioners of the thermal
arts and sciences generally deal with four basic thermal transport modes:conduction,
including contact resistance;convection;phase change;and radiation.
The expression of the governing heat transfer relations in the form of thermal re
sistances (Kraus,1958) greatly simpliﬁes the ﬁrstorder thermal analysis of electronic
systems.Recognizing that heat ﬂow q is analogous to electrical current and that the
temperature drop ∆T is analogous to a voltage drop,it is possible to deﬁne a general
thermal resistance R as
R =
∆T
q
(13.1)
Although,strictly speaking,this analogy applies only to conduction heat transfer,it
is possible to generalize this deﬁnition to all the modes of thermal transport.Thus,
following the established rules for resistance networks,thermal resistances that occur
sequentially can be summed to yield the overall thermal resistance along that heat
ﬂow path.Conversely,the reciprocal of the overall thermal resistance of several
parallel heat transfer paths or mechanisms can be found by summing the reciprocals
of the individual resistances.
In reﬁning the thermal design of an electronic system,primary attention should
be devoted to reducing the largest thermal resistances along a speciﬁed thermal path
and/or providing parallel paths for heat removal from a critical area or component.
While thermal resistances associated with various paths and thermal transport mech
anisms constitute the building blocks for the development of a thermal packaging
solution,they have also found widespread application as ﬁgures of merit in evaluating
and comparing the thermal efﬁcacy of various packaging techniques and strategies.
13.2.2 Basic Heat Transfer Modes
Conduction Based on Fourier’s equation for onedimensional thermal diffusion
(Incropera and DeWitt,1996),the thermal resistance for conduction heat transfer is
given by
R =
L
kA
(13.2)
where Lis the length of the heat ﬂowpath,k the thermal conductivity of the medium,
and Athe crosssectional area for heat ﬂow.Table 13.3 lists the values of the thermal
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Table 13.3 RoomTemperature Thermal Properties of Commonly Used Electronic
Packaging Materials
Density Speciﬁc Heat Thermal Conductivity
Material (kg/m
3
) (J/kg · K) (W/m· K)
Air 1.16 1,005 0.024
Epoxy (dielectric) 1,500 1,000 0.23
Epoxy (conductive) 10,500 1,195 0.35
Polyimide 1,413 1,100 0.33
FR4 1,500 1,000 0.30
Water 1,000 4,200 0.59
Thermal grease — — 1.10
Alumina 3,864 834 22.0
Aluminum 2,700 900 150
Silicon 2,330 770 120
Copper 8,800 380 390
Gold 19,300 129 300
Diamond 3,500 51 2,000
Source:Incropera and DeWitt (1996).
conductivity,density,and speciﬁc heat of some of the commonly used electronic
packaging materials.Conduction resistance values for typical packaging materials
are displayed in Fig.13.2 as a function of the thermal conductivity and the ratio of
thickness to crosssectional area of a single layer.This ﬁgure reveals the conduction
resistance to range from2 K/Wfor a 1mmthick 1000mm
2
layer of a typical epoxy
encapsulant to 6 × 10
−4
W/K for a 25µmthick layer of copper 100 mm
2
in area.
Similarly,typical soft bonding materials are found to pose resistances of 0.1 K/Wfor
solders and 1 to 3 K/Wfor epoxies and thermal greases for typical L/Aratios ranging
from0.25 to 1.0 m
−1
.
Equation (13.2) is strictly valid only for onedimensional heat conduction.How
ever,for geometrically complex electronic packages,in which heat ﬂow is two or
threedimensional,the shape factor approach can be used to deﬁne the internal resis
tance of the package via
R =
L
kA
=
1
k(A/L)
=
1
kS
(13.3)
The shape factor S in eq.(13.3) is solely geometry dependent and can be found
tabulated in many of the popular heat transfer textbooks (McAdams,1954;Incropera
and DeWitt,1996;Swartz and Pohl,1989).
Convection Following the formof the conventional relations for convective heat
transfer,often referred to as Newton’s law of cooling (Incropera and DeWitt,1996),
the thermal resistance in convective thermal transport can be written in the form of
eq.(13.3):
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10
2
10
1
1 10 10
2
10
3
10
1
1
10
2
10
Thermal Conductivity (W/m
.
K)
R
cond
(K/W)
R X kA
cond
=/
Copper
Silicon
Alumina
Epoxy
Figure 13.2 Conduction thermal resistances for packaging materials.
R =
1
hA
(13.4)
where h is the coefﬁcient of heat transfer.The heat transfer coefﬁcients for typical
ﬂuids and speciﬁed domains relevant to electronic packaging vary by nearly three
orders of magnitude,from approximately 5 W/m
2
· K for air in natural convection
and 25 W/m
2
· Kfor air in forced convection,to some 150 W/m
2
· Kfor highvelocity
air jets,perhaps 1000 W/m
2
· K for forced convection of water in cold plates,and
values approaching 5,000 W/m
2
· K for the pool boiling of ﬂuorocarbon liquids.
The heat transfer literature contains many theoretical equations and empirical
correlations that can be used to determine the heat transfer coefﬁcient for speciﬁed
ﬂuids ﬂowing within channels or along surfaces of various geometries.Many of these
relations are expressed in nondimensional formas
Nu = C · Re
n
· Pr
m
(13.5)
where Nu is the Nusselt number,C a geometric constant,Re the Reynolds number,
and Pr the Prandtl number.Many of the commonly used empirical correlations for
convective heat transfer in geometries encountered in electronic packaging conﬁgura
tions are summarized in Table 13.4.Alternatively,simpliﬁed heat transfer coefﬁcient
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TABLE 13.4 Correlation for Convective Heat Transfer Coefﬁcients
Mode of Convection Correlation
Natural convection froman
isothermal vertical surface
h = C(Ra)
n
= C
k
f
L
ρ
2
f
βgC
p
∆T L
3
µ
f
k
f
n
C = 0.59,n =
1
4
for 1 < Ra < 10
9
C = 0.10,n =
1
3
for 10
9
< Ra < 10
14
Natural convection froma
vertical isoﬂux surface
h = 0.631
k
f
L
C
p
ρ
2
f
gβq
H
5
µ
f
k
2
f
L
1/5
Natural convection on an
isothermal horizontal surface
h = C(Ra)
n
= C
k
f
L
ρ
2
f
βgC
p
∆T L
3
µ
f
k
f
n
C = 0.54,n =
1
4
for 10 ≤ Ra ≤ 10
7
C = 0.15,n =
1
3
for 10
7
≤ Ra ≤ 10
11
Forced convection on an
isothermal ﬂat plate
h = C(Re)
n
(Pr)
1/3
= C
k
f
L
ρ
f
VL
µ
f
n
µ
f
C
p
k
f
1/3
Laminar:C = 0.664,n =
1
2
Turbulent:C = 0.0296,n =
4
5
Forced convection on an isoﬂux
ﬂat plate
h = C(Re)
n
(Pr)
1/3
= C
k
f
L
ρ
f
VL
µ
f
n
µ
f
C
p
k
f
1/3
Laminar:C = 0.453,n =
1
2
Turbulent:C = 0.0308,n =
4
5
Laminar forced convection in a
circular tube
h =
k
f
D
3.66 +
0.0668(D/L) · Re · Pr
1 +0.04
[
(D/L) · Re · Pr
]
2/3
Re =
ρ
f
VD
µ
f
,Pr =
µ
f
C
p
k
f
for Re < 2000
Turbulent forced convection in a
circular tube
h =
k
f
D
(0.023Re
0.8
· Pr
n
)(Re > 2000)
n = 0.4 for heating,n = 0.3 for cooling
Source:Incropera and DeWitt (1996).
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TABLE 13.5 Simpliﬁed Equations for Convective Heat Transfer Coefﬁcients for Air
at 50°C
Mode of Convection Correlation
Natural convection froman
isothermal vertical surface
h =
1.51
L
(∆T L
3
)
1/4
Natural convection froma vertical
isoﬂux surface
h =
1.338
L
q
H
5
L
1/5
Natural convection on an isothermal
horizontal surface
h =
1.381
L
(∆T L
3
)
1/4
Forced convection on an isothermal
ﬂat plate
h =
3.886
V
L
0.5
for laminar ﬂow
0.099
V
4
L
0.2
for turbulent ﬂow
Forced convection on an isoﬂux ﬂat
plate
h =
2.651
V
L
0.5
for laminar ﬂow
0.103
V
4
L
0.2
for turbulent ﬂow
Laminar forced convection in a
circular tube
h =
1
D
0.131 +
1563(VD
2
/L)
1 +32.50(VD
2
/L)
2/3
Turbulent forced convection in a
circular tube
h =
0.00071
V
4
D
0.2
for heating
0.000736
V
4
D
0.2
for cooling
equations and/or tabulated values for speciﬁc ﬂuids and geometries of interest can
be used to streamline the determination of this most important parameter.Table 13.5
lists such simpliﬁed equations for calculation of heat transfer coefﬁcients for air at
an average temperature of 50°C.
Values of convection resistance for a variety of coolants and heat transfer mech
anisms are shown in Fig.13.3 for a typical heat source area of 10 cm
2
and the ve
locity range 2 to 8 m/s.These resistances are seen to vary from100 K/Wfor natural
convection in air,to 33 K/Wfor forced convection in air,to 0.5 K/Wfor boiling in
ﬂuorocarbon liquids.
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Figure 13.3 Convective thermal resistances for typical coolants.
Radiation Thermal radiation is governed by the difference between the source and
sink temperatures,each raised to the fourth power:
q = εσAF
12
T
4
1
−T
4
2
(13.6)
where ε is the emissivity;σ the Stefan–Boltzmann constant,equal to 5.67 × 10
−8
W/m
2
· K
4
;and F
12
the radiation view factor between surfaces 1 and 2.For highly
absorbing and emitting surfaces placed in close proximity to each other,F
12
is close
to unity.The value of F
12
also approaches unity when determining the ﬂowof radiant
heat froma small,highly emitting surface to a large,highly absorbing surface which
surrounds it on all sides.Relations for estimating the view factor for simple geome
tries and a variety of surface conditions can be found in textbooks by Incropera and
DeWitt (1996) and Swartz and Pohl (1989).View factors for a variety of complex
geometries have also been tabulated by Howell (1982).
For modest temperature differences,eq.(13.6) can be linearized to the form
q = h
r
A(T
1
−T
2
) (13.7)
where h
r
is the effective radiation heat transfer coefﬁcient and is approximately
equal to
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h
r
= 4εσF
12
T
1
T
2
3/2
(13.8)
Noting the form of eq.(13.7),the radiation thermal resistance—analogous to the
convective resistance—is seen to be expressible as
R =
1
h
r
A
(13.9)
13.2.3 Chip Package Resistance
The thermal performance of alternative chip and packaging is commonly compared
on the basis of the overall (junctiontocoolant) thermal resistance R
T
.This packaging
ﬁgure of merit is generally deﬁned in a purely empirical fashion:
R
T
=
T
j
−T
f
q
(13.10)
where T
j
and T
f
are the junction and coolant (ﬂuid) temperatures,respectively,and
q is the chip heat dissipation.To lower chip temperatures at a speciﬁed power,it
is clearly necessary to select and/or design a chip package with the lowest thermal
resistance.Examination of various packaging techniques reveals that the junction
tocoolant thermal resistance is,in fact,composed of an internal,largely conductive
resistance and an external,primarily convective resistance.As shown in Fig.13.4,the
internal resistance R
j
is encountered in the ﬂowof dissipated heat fromthe active chip
Figure 13.4 Primary thermal resistances in a singlechip package.
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surface through the materials used to support and bond the chip and on to the case
of the integratedcircuit package.The ﬂow of the heat from the case directly to the
coolant,or indirectly through a ﬁn structure and then to the coolant,must overcome
the external resistance R
ex
.
Internal Resistance In ﬂowing fromthe chip to the package surface or case,the
heat encounters a series of resistances associated with individual material layers such
as silicon,copper,alumina,and epoxy,as well as the contact resistances that occur
at the interfaces between layers of materials.Although the actual heat ﬂow paths
within the chip package are rather complex and may shift to accommodate varying
external cooling situations,it is possible to obtain a ﬁrstorder estimate of the internal
resistance by assuming that power is dissipated uniformly across the chip surface and
that the heat ﬂow is largely onedimensional.
Equation (13.11) can be used to determine the internal chip module resistance,
where the summed terms represent the conduction thermal resistances posed by the
individual layers,each with thickness ∆x.
R
T
≡
T
j
−T
c
q
=
∆x
kA
(13.11)
External Resistance To determine the resistance to thermal transport from the
surface of a component to a ﬂuid in motion (i.e.,the convective resistance),it is
necessary to quantify the heat transfer coefﬁcient h.The heat transfer coefﬁcient
can be calculated by using the various correlations listed in Tables 13.4 and 13.5
for both natural and forced convection.The external resistance R
ex
for convective
cooling can be expressed as shown in eq.(13.4).When a heat sink or compact heat
exchanger is attached to the package,the external resistance accounting for the bond
layer conduction and the total resistance of the heat sink R
sk
can be expressed as
R
ex
=
T
c
−T
f
q
=
∆x
kA
+R
sk
(13.12)
where
R
sk
=
1
nhA
ﬁn
η
+
1
h
b
A
b
−1
(13.13)
is the parallel combination of the resistance R
ﬁn
of the n ﬁns:
R
ﬁn
=
1
nhA
ﬁn
η
(13.14)
where η is the ﬁn efﬁciency,and the exposed or base surface resistance R
b
not
occupied by the ﬁns,
R
b
=
1
h
b
A
b
(13.15)
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Here the base surface area (A
b
= A
T
− nA
f
),and the heat transfer coefﬁcient h
b
are used because the heat transfer coefﬁcient that is applied to the base surfaces
is not necessarily equal to that on the ﬁns.In an optimally designed ﬁn structure,
the ﬁn efﬁciency η can be expected to fall in the range 0.5 to 0.7 (Kraus and Bar
Cohen,1983).
FlowResistance The transfer of heat to a ﬂowing gas or liquid that is not under
going phase change results in an increase in the coolant temperature from the inlet
temperature T
in
to an outlet temperature T
out
,which results in a ﬂow resistance R
fl
given by (Kraus and BarCohen,1983)
R
fl
=
Q
q
1
2 ˙m
(13.16)
where Qis the heat absorbed by the ﬂuid fromall the components in its ﬂowpath,q
the heat dissipation of a single component,and ˙mthe mass ﬂow rate.
Total Resistance:SingleChip Packages The overall singlechip package
resistance relating the chip temperature to the inlet temperature of the coolant can
be found by summing the internal,external,ﬂow resistance,and various spreading
resistances to yield
R
T
= R
jc
+R
sp
+R
ex
+R
fl
(13.17)
where R
sp
is the spreading resistance arising from the threedimensional nature of
heat ﬂowin the heat spreader and heat sink base.R
sp
is discussed in greater detail in
Section 13.3.1.
13.3 LENGTHSCALE EFFECTS ONTHERMOPHYSICAL
PROPERTIES
Thermal analysis and control of electronic equipment occurs across the wide range
of length scales encountered in packaged microelectronic components:from the
nanoscale features characteristic of advanced semiconductor devices,to the micro
scale functional cells on the silicon,to the mesoscale dimensions of individual chips
and the macroscale of packages and printed circuit boards.In the preceding discus
sion,it was assumed that thermophysical properties are independent of the size of
the specimen or the length scale involved in a particular thermal transport process.
However,extensive research on heat transport in miniaturized systems,such as occurs
in microelectronic devices,and thermal processes occurring at a very fast rate,such
as encountered in pulsed laser heating,has shown that at very small length scales,
thermophysical properties such as the thermal conductivity and the speciﬁc heat can
deviate signiﬁcantly fromthe commonly accepted macroscale values.
Two distinct length scales govern the diffusion of heat through solids:the mean
free path of electrons or phonons,and the characteristic wavelength of the energy
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carrier.Variations in the mean free path produce the classical size effect on the
thermal conductivity of any material (Tien and Chen,1994).The quantumsize effect,
reﬂecting the impact of the characteristic wavelength of the energy carrier (Tien and
Chen,1994),has been shown to affect both the thermal transport properties and the
thermodynamic properties.
The Asheghi et al.(1996) results for the effect of ﬁlm thickness on the thermal
conductivity of silicon at various temperatures are shown in Fig.13.5.This ﬁgure
reveals that thermal conductivity is more sensitive to ﬁlm thickness at cryogenic
temperatures,at which the mean free path of the energy carriers grows to become
comparable to the size of the specimen.In this domain,thermal transport is limited
by boundary scattering of phonons or electrons.Majumdar (1993) has derived an
expression for calculation of the effective thermal conductivity of thin,dielectric ﬁlms
where phonons are the dominant thermal carriers:
k
ﬁlm
k
bulk
=
1
1 +
4
3
(l/δ)
(13.18)
where l is the mean free path and δ is the thickness of the ﬁlm.Equation (13.18) is
valid only at temperatures below the Debye temperature.
Prasher and Phelan (1998) calculated the size effect on the bulk phonon heat ca
pacity of thin ﬁlms and various other microstructures showing that if the characteristic
length of the microstructure approaches the dominant phonon wavelength,the spe
ciﬁc heat per unit volume becomes dependent on the dimension of the thin ﬁlms.They
Figure 13.5 Thinﬁlmthermal conductivity of silicon.(FromTien and Chen,1994.)
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suggested that when the grouping,NT/φ,where N is the number of atomic layers in
the thin ﬁlm,T the temperature,and φ the Debye temperature,is less than unity,the
heat capacity can be expected to display sensitivity to the characteristic dimension.
Their results show that such size effects on the thermodynamic properties are more
important at cryogenic temperatures.
13.3.1 Spreading Resistance
In chip packages that provide for lateral spreading of the heat generated in the chip,
the increasing crosssectional area for heat ﬂow in the “layers” adjacent to the chip
reduces the heat ﬂux in successive layers and hence the internal thermal resistance.
Unfortunately,however,there is an additional resistance associated with this lateral
ﬂow of heat,which must be taken into account in determination of the overall chip
package temperature difference.The temperature difference across each layer of such
a structure can be expressed as
∆T = qR
T
(13.19)
where
R
T
= R
1D
+R
sp
(13.20)
or
R
T
=
∆x
kA
+R
sp
(13.21)
For the circular and square geometries common in microelectronic applications,
Negus et al.(1989) provide an engineering approximation for the spreading resistance
R
sp
of a small heat source on a thick substrate or heat spreader,insulated on the sides
and held at a ﬁxed temperature along the base as
R
sp
=
(0.475 −0.626 +0.13ζ)
3
k
√
a
(13.22)
where ζ is the square root of the heat source area divided by the substrate area,k the
thermal conductivity of the substrate,and a the area of the heat source.
The spreading resistance R
sp
from eq.(13.22) can now be added to the one
dimensional conduction resistance to yield the overall thermal resistance of that layer.
It is to be noted that the use of eq.(13.22) requires that the substrate be three to ﬁve
times thicker than the square root of the heat source area.Consequently,for relatively
thin layers on thicker substrates,such as thin lead frames or heat spreaders interposed
between the chip and the substrate,eq.(13.22) cannot be expected to provide an
acceptable prediction of R
sp
.Instead,use can be made of the numerical results plotted
in Fig.13.6 to obtain the appropriate value of the spreading resistance.
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Figure 13.6 Spreading resistance on thin layers.
Kennedy (1959) analyzed heat spreading froma circular uniformheat ﬂux source
to a cylindrical substrate with isothermal temperature boundaries at the edges,the
bottom,or both,and presented the results in graphic form.Spreading resistance
charts prepared originally by Kennedy (1959) were reproduced by Sergent and Krum
(1994).Although the boundary conditions and geometry assumed by Kennedy (1959)
do not match the mixed boundary conditions and rectangular shapes found in most
electronic packages,the spreading resistance results can be used with acceptable
accuracy in many design situations (Simons et al.,1997).Using the spreading re
sistance factor H from the appropriate Kennedy graph,the spreading resistance is
calculated using
R
sp
=
H
kπ
√
a
(13.23)
where k is the thermal conductivity and a is the heat source area (Figs.13.7 to 13.9).
Song et al.(1994) developed an analytical model to estimate the constriction–
spreading thermal resistance R
sp
froma circular or rectangular heat source to a sim
ilarly shaped convectively cooled substrate.Lee et al.(1995) extended the solutions
provided by Song et al.(1994) to present closedformexpressions for dimensionless
constriction–spreading thermal resistance based on average and maximum tempera
ture rise through the substrate.Their set of equations is
R
sp,avg
=
0.5(1 −ζ)
3/2
φ
c
k
√
A
source
(13.24)
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R
sp,max
=
1/
√
π
(1 −ζ)
3/2
φ
c
k
√
A
source
(13.25)
φ
c
=
tanhλ
c
τ +(λ
c
· Bi)
1 +(λ
c
· Bi) tanhλ
c
τ
(13.26)
λ
c
= π+
1
e
√
π
(13.27)
τ =
δ
b
(13.28)
Bi =
hr
k
(13.29)
Figure 13.7 Spreading resistance factor H
1
for surface z = w at zero temperature.(From
Simons et al.,1997.)
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0.01 0.1 1.0
0.01
0.1
1.0
10
a b/
SpreadingResistanceFactorH
1
w
b
a
z
T = 0
0.01
0.015
0.02
0.025
0.03
0.04
0.05
0.06
0.08
0.10
0.15
0.20
0.25
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.50
2.00
2.50
3.00
4.00
5.00
6.00
7.00
8.00
9.00
10.00
w b/
r
Figure 13.8 Spreading resistance factor H
2
for surface z = w at zero temperature.(From
Simons et al.,1997.)
In eqs.(13.24)–(13.29),R
sp,ave
is the constriction resistance based on the average
source temperature,R
sp,max
the constriction resistance based on the maximumsource
temperature,δ the ﬁn thickness,r the outer radius of the substrate,h the convective
heat transfer coefﬁcient,and k the thermal conductivity.The authors claim the ex
pressions to be accurate to within 10% for a range of source and substrate shapes
and for source and substrate rectangularity aspect ratios less than 2.5.Use of the
convective boundary condition on the substrate base makes these relations especially
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Figure 13.9 Spreading resistance factor H
3
for surface z = w at zero temperature.(From
Simons et al.,1997.)
well suited to the analytical determination of the spreading resistance of a chipto
heat sink assembly as well as a chip encapsulated in a convectively cooled plastic
package.
13.3.2 Heat Flow across Solid Interfaces
Heat transfer across an interface formed by the joining of two solids is accompanied
by a temperature difference caused by imperfect contact between the two solids.
Even when perfect adhesion is achieved between the solids,the transfer of heat is
impeded by the acoustic mismatch in the properties of the phonons on either side of
the interface.Traditionally,the thermal resistance arising due to imperfect contact
has been called the thermal contact resistance.The resistance due to the mismatch
in the acoustic properties is usually termed the thermal boundary resistance.The
thermal contact resistance is a macroscopic phenomenon,whereas thermal boundary
resistance is a microscopic phenomenon.
Thermal Contact Resistance When two surfaces are joined,as shown in Fig.
13.10,asperities on each of the surfaces limit the actual contact between the two
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Figure 13.10 Contact and heat ﬂow at a solid–solid interface.
solids to a very small fraction,perhaps just 1 to 2% for lightly loaded interfaces,of
the apparent area.As a consequence,the ﬂowof heat across such an interface involves
solidtosolid conduction in the area of actual contact,A
co
,and conduction through
the ﬂuid occupying the noncontact area,A
nc
,of the interface.At elevated tempera
tures or in vacuum,radiation heat transfer across the open spaces may also play an
important role.The pressure imposed across the interface,along with microhardness
of the softer surface and the surface roughness characteristics of both solids,deter
mine the interfacial gap δ and the contact area A
co
.Assuming plastic deformation of
the asperities and a Gaussian distribution of the asperities over the apparent area,for
the contact resistance R
co
,Cooper et al.(1969) proposed
R
co
=
1.45
k
s
(P/H)
0.985
σ

tan θ
−1
(13.30)
where k
s
is the harmonic mean thermal conductivity,deﬁned as k
s
= 2k
1
k
2
/(k
1
+k
2
);
P the apparent contact pressure;H the hardness of the softer material;and σ the root
meansquare (rms) roughness,given by
σ
1
=
σ
2
1
+σ
2
2
(13.31)
where σ
1
and σ
2
are the roughness of surface 1 and 2,respectively.The term 
tan θ
in eq.(13.30) is the average asperity angle:

tan θ
2
=  tan θ
1

2
+ tan θ
2

2
(13.32)
This relation neglects the heat transfer contribution of any trapped ﬂuid in the inter
facial gap.
In the pursuit of a more rigorous determination of the contact resistance,Yovano
vich and Antonetti (1988) found it possible to predict the areaweighted interfacial
gap,Y,in the form
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Y = 1.185σ
−ln
3.132P
H
0.547
(13.33)
where σ is the effective rms as given by eq.(13.31),P the contact pressure (Pa),and
H the surface microhardness (Pa) of the softer material,to a depth of the order of
the penetration of the harder material.Using Y as the characteristic gap dimension
and incorporating the solid–solid and ﬂuid gap parallel heat ﬂow paths,Yovanovich
(1990) derived for the total interfacial thermal resistance,
R
co
=
1.25k
s

tan θ
σ
P
H
0.95
+
k
g
Y
−1
(13.34)
where k
g
is the interstitial ﬂuid thermal conductivity.In the absence of detailed
information,σ/
tan θ can be expected to range from5 to 9 µmfor relatively smooth
surfaces.
Thermal Boundary Resistance When dealing with heat removal from a chip
and thermal transport in various packaging structures at roomtemperature and above,
the thermal boundary resistance R
b
is generally negligible compared to the contact re
sistance.However,at the transistor level,where interfaces—often formed by epitaxial
thin ﬁlmdeposition,through atomistic processes such as physical vapor deposition—
may be nearly perfect,the thermal boundary resistance should be included.Two
theoretical models are widely used to predict the thermal boundary resistance R
b
:
the acoustic mismatch model (AMM) and the diffuse mismatch model (DMM).The
former is based on the specular reﬂection of sound waves at the interface and the latter
is based on the diffuse scattering of phonons at the interface.Swartz and Pohl (1989)
provide a comprehensive discussion of both AMMand DMMmodels for the thermal
boundary resistance and have shown that the microscopic thermal boundary resis
tance resulting from the mismatch in the acoustic properties in the lowtemperature
limit can be obtained by the following DMMequation:
R
b
=
π
2
30
k
4
b
¯
h
3
jj
c
−2
1,jj
×
j
c
−2
2,jj
jj
c
−2
1,jj
+
jj
c
−2
2,jj
T
−3
(13.35)
where k
b
is the Boltzmann constant,
¯
h the Planck constant divided by 2π,c the speed
of sound,jj the mode of sound (jj = 1 for the longitudinal mode,and jj = 2 for the
transverse mode),and the subscripts 1 and 2 refer to the two solids in contact.Note
that this relation is strictly valid only at very low temperatures.Similar equations
to estimate R
b
using DMM at high temperatures or AMM can be obtained from
Swartz and Pohl (1989).Although AMM and DMM are based on very different
physical arguments,they appear to yield identical results for most material pairs
(Swartz and Pohl,1989).Both these models are very good in predicting R
b
at very
low temperatures but fail miserably at high temperatures for various reasons,such
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as increased scattering of phonons and deviation from the Debye density of states
(Swartz and Pohl,1989).
Interstitial Materials In describing heat ﬂow across an interface,eq.(13.34)
assumed the existence of a ﬂuid gap,which provides a parallel heat ﬂow path to
that of the solid–solid contact.Because the noncontact area may occupy in excess
of 90%of the projected area,heat ﬂow through the interstitial spaces can be of great
importance.Consequently,the use of highthermalconductivity interstitial materials,
such as soft metallic foils and ﬁber disks,conductive epoxies,thermal greases,and
polymeric phasechange materials,can substantially reduce the contact resistance.
The enhanced thermal capability of many of highperformance epoxies,thermal
greases,and phasechange materials commonly in use in the electronic industry is
achieved through the use of large concentrations of thermally conductive particles.
Successful design and development of thermal packaging strategies thus requires the
determination of the effective thermal conductivity of such particleladen interstitial
materials and their effect on the overall interfacial thermal resistance.
Comprehensive reviews of the general role of interstitial materials in controlling
contact resistance have been published by several authors,including Sauer (1992).
When interstitial materials are used for control of the contact resistance,it is desirable
to have some means of comparing their effectiveness.Fletcher (1972) proposed two
parameters for this purpose.The ﬁrst of these parameters is simply the ratio of the
logarithms of the conductances,which is the inverse of the contact resistance,with
and without the ﬁller:
χ =
ln κ
cm
ln κ
bj
(13.36)
in which κ is the contact conductance,and cmand bj refer to control material and bare
junctions respectively.The second parameter takes the thickness of the ﬁller material
into account and is deﬁned as
η =
(κδ
ﬁller
)
cm
(κδ
gap
)
bj
(13.37)
in which δ is the equivalent thickness.
The performance of an interstitial interface material as decided by the parameter
deﬁned by Fletcher (1972),in eqs.(13.36) and (13.37) includes the bulk as well as the
contact resistance contribution.It is for this reason that in certain cases the thermal
resistance of these thermal interface materials is higher than that for a bare metallic
contact because the bulk resistance is the dominant factor in the thermal resistance
(Madhusudan,1995).To make a clear comparison of only the contact resistance
arising from the interface of the substrate and various thermal interface materials,
it is important to measure it exclusively.Separation of the contact resistance and
bulk resistance will also help researchers to model the contact resistance and the bulk
resistance separately.
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Equations (13.36) and (13.37) by Fletcher (1972),showthat the thermal resistance
of any interface material depends on both the bond line thickness and thermal con
ductivity of the material.As a consequence,for materials with relatively low bulk
conductivity,the resistance of the added interstitial layer may dominate the thermal
behavior of the interface and may result in an overall interfacial thermal resistance that
is higher than that of the bare solid–solid contact (Madhusudan,1995).Thus,both the
conductivity and the achievable thickness of the interstitial layer must be considered
in the selection of an interfacial material.Indeed,while the popular phasechange
materials have a lower bulk thermal conductivity (at a typical value of 0.7 W/m· K)
than that of the siliconebased greases (with a typical value of 3.1 W/m · K),due to
thinner phasechange interstitial layers,the thermal resistance of these two categories
of interface materials is comparable.
To aid in understanding the thermal behavior of such interface materials,it is useful
to separate the contribution of the bulk conductivity from the interfacial resistance,
which occurs where the interstitial material contacts one of the mating solids.Fol
lowing Prasher (2001),who studied the contact resistance of phasechange materials
(PCMs) and siliconebased thermal greases,the thermal resistance associated with
the addition of an interfacial material,R
TIM
can be expressed as
R
TIM
= R
bulk
+R
co
1
+R
co
2
(13.38)
where R
bulk
is the bulk resistance of the thermal interface material,and R
co
the contact
resistance with the substrate,and subscripts 1 and 2 refer to substrates 1 and 2.Prasher
(2001) rewrote eq.(13.38) as
R
TIM
=
δ
κ
TIM
+
σ
1
2κ
TIM
A
nom
A
real
+
σ
2
2k
TIM
A
nom
A
real
(13.39)
where R
TIM
is the total thermal resistance of the thermal interface material,δ the
bondline thickness,κ
TIM
the thermal conductivity of the interface material,σ
1
and
σ
2
the roughness of surfaces 1 and 2,respectively,A
nom
the nominal area,and A
real
the real area of contact of the interface material with the two surfaces.Equation
(13.39) assumes that the thermal conductivity of the substrate is much higher than
that of the thermal interface material.The ﬁrst term on the righthand side of eq.
(13.39) is the bulk resistance,and other terms are the contact resistances.Figure 13.11
shows the temperature variation at the interface between two solids in the presence of
a thermal interface material associated with eq.(13.39).Unlike the situation with the
more conventional interface materials,the actual contact area between a polymeric
material and a solid is determined by capillary forces rather than surface hardness,
and an alternative approach is required to determine A
real
in eq.(13.39).Modeling
each of the relevant surfaces as a series of notches,and including the effects of surface
roughness,the slope of the asperities,the contact angle of the polymer with each the
substrates,the surface energy of the polymer,and the externally applied pressure,a
surface chemistry model was found to match very well with the experimental data
for PCM and greases at low pressures (Prasher,2001),as shown in Fig.13.12 for
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Figure 13.11 Temperature drops across an interface.
PCM.Unfortunately,it has not yet been found possible to determine the contact area
with a closedformexpression.It is also to be noted that eq.(13.39) underpredicts the
interface thermal resistance data at high pressures.
Thermal Conductivity of ParticleLaden Systems Equation (13.39) shows
that the bulk and contact resistance of the thermal interface material are dependent
on the thermal conductivity of the interface material.The thermal conductivity of
a particleladen polymer increases nonlinearly with increasing volume fraction of
the conducting particle,as suggested in Fig.13.13.One of the most commonly
used models for predicting the thermal conductivity of a particleladen,twophase
system is the Lewis and Nielsen (1970) model.This model calculates the thermal
conductivity of twophase systemusing
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Figure 13.12 Surface chemistry model of contact resistance.
k = k
m
1 +SBϕ
1 −Bψϕ
(13.40)
where k
m
is the thermal conductivity of the continuous phase or base polymer,ϕ the
particle volume fraction,and S a shape parameter that increases with aspect ratio.
Table 13.6 provides the value of A for dispersed polymers.The constant B in eq.
(13.40) can be estimated using the expression
B =
k
p
/k
m
−1
k
p
/k
m
+S
(13.41)
where k
p
is the thermal conductivity of the ﬁller and
TABLE 13.6 Values of A for Several Dispersed Types
Aspect Ratio of
Dispersed Phase
(Length/Diameter) A
Spheres 1 1.5
Randomly oriented rods 2 1.58
4 2.08
6 2.8
10 4.93
15 8.38
Source:Cross (1996).
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ψ = 1 +
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2
m
φ (13.42)
where ϕ
m
is the maximumpacking fraction.Table 13.7 lists values of ϕ
m
for spheres
and rods in different packing conﬁgurations.
Another commonly used model for predicting thermal conductivity of twophase
systems is effective medium transport (EMT),discussed by Devpura et al.(2000).
Both the EMT and Lewis–Nielsen models were developed for moderate ﬁller density
(up to around 40% by volume) and often fail to predict the thermal conductivity at
higher percentages of the ﬁller.The Nielsen model becomes unstable above a 40%
volume fraction,as shown by Devpura et al.(2000),whereas the EMT model under
predicts the thermal conductivity above 40%.
Devpura et al.(2000) have proposed a new model,based on the formation of a
percolation network of the ﬁller,for calculating the thermal conductivity of high
volumefraction particleladen systems.The change in the conductivity of the matrix
from its value at the percolation threshold (percentage of ﬁller particles at which
percolation starts) is given by
∆k =
k
f
(p −p
c
)
0.95±0.5
(13.43)
where p
c
is the volume fraction at the percolation threshold and p is the volume
fraction.The thermal conductivities calculated using the percolation,EMT,and
LewisNielsen models are shown in Fig.13.13,where the percolation model appears
to provide a useful upper bound on the thermal conductivity.Unfortunately,how
ever,the threshold value p
c
needed in eq.(13.43) can only be determined from a
full numerical simulation.Devpura et al.(2000) have provided an algorithm for the
percolation modeling of particleladen systems.
The effective thermal conductivity of a particleladen polymeric system is also
dependent on the interfacial resistance between the particle and the matrix.Devpura
TABLE 13.7 MaximumPacking Fraction φ
m
Shape of Particles Type of Packing φ
m
Spheres Facecentered cubic 0.7405
Hexagonal close 0.7405
Bodycentered cubic 0.6
Simple cubic 0.524
Randomclose 0.637
Randomloose 0.601
Rods or ﬁbers Uniaxial hexagonal close 0.907
Uniaxial simple cubic 0.785
Uniaxial random 0.82
Threedimensional random 0.52
Source:Cross (1996).
BOOKCOMP,Inc.—John Wiley &Sons/Page 978/2nd Proofs/Heat Transfer Handbook/Bejan
978
HEAT TRANSFER IN ELECTRONIC EQUIPMENT
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Conductivity(W/m
.
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Percentage filler (Al O )
2 3
Percolation model
Experimental data
EMT (Maxwell
Eucken equation)
Nielsen Model
Figure 13.13 Comparing the percolation model with experimental data and other existing
models for a bimodal distribution of Al
2
O
3
ﬁller (65 µm:9µm = 4:1) in polyethylene
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