High Performance Embedded Microcontroller - Cortus

pleasanthopebrothersΗλεκτρονική - Συσκευές

2 Νοε 2013 (πριν από 3 χρόνια και 10 μήνες)

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Features
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High Throughput RISC Core
Optional Memory Management
Optional Memory Protection Unit
Integer Divider
Dual & Multi-Core Capable
The APS5 has been designed to ensure high throughput,
and high clock frequencies, most instructions (including
loads and stores) execute in a single cycle due to the 5-7
pipeline with out-of-order completion.
The simple, vectored, interrupt structure ensures low
latency, real time, response to external events with a
minimum of overhead. Up to 251 external user interrupts
are supported.
A coherent data cache is available, supporting multi-core
architectures.
Instruction Cache
Optional Data Cache
5-7 Stage Pipeline
Integer Multiply
CoreMark 1.0 : 1.931468 / GCC4.5.3 20120201 (Cortus Eval) -mmul -flto
-O3 -funroll-all-loops -finline-limit=500-IC:/cortus-ide/toolchain/aps3/include -DPERFORMANCE_RUN=1
advanced processing solutions
APS5
www.cortus.com
High Performance Embedded Microcontroller
The APS5 from Cortus is a high
per f or mance, ex t endi bl e 32
microcontroller core suitable for
creating complex embedded systems
with caches, co-processors and
multiple cores.
Designed for advanced control and
communication applications, it is well
suited to complex sensors, home
automation, military and aerospace.
As a member of the Cortus APS family of
processors the APS5 shares the key
architectural features of the other processors,
with a common toolchain and IDE, bus interface
and peripheral set.
The ASP5 is fully upwards compatible with the
other APS processors. Its instruction set
includes all APS3 instructions plus additional
ones to enhance computation performance and
further improve code density. The modern RISC
architecture and careful design ensures that the APS5 can
achieve a high maximum clock frequency, F. The APS5
max
has a high performance integer multiplier and divider.
The APS5 has a modern RISC architecture, with a 5-7
stage pipeline and out-of-order completion. Co-processor
operations can use the main register set and there are no
penalties over native instructions.
Performance
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Implementation Results
CoreMark 1:1·93
DMIPS 2·29 DMIPS/MHz
At least 400MHz in 90nm
2
0·041 mm
2
0·150 mm
65nm (TSMC)
130nm (UMC)
23·77 µW/MHz
2·55 µW/MHz
Area
F
max
Power
512 MHz
277 MHz
2
0·089 mm
16·83 µW/MHz
434 MHz
90nm (UMC)
low power
R0 = 0
RTT
CPU Core
UART
Interrupt
Controller
ALU
Multiply
Timer
GPIO
RAM
Watchdog
X-Bar
Flash
Divide
Status
R15
On-Chip
Debug
Co
Processor
optional
D-Cache
optional
DMA
I-Cache
www.cortus.com/aps5.html
sales@cortus.com +44 1264 369483
Ecosystem
The APS5 benefits from the shared ecosystem
surrounding the APS family. It has a complete software
development environment including toolchain for C and
C++, a complete adapted IDE based on one of the most
widely used IDEs - Eclipse. Debugging is fully supported
with an integrated instruction set simulator, the Cortus on-
chip-debuging hardware and an Ethernet connected
JTAG interface - the EtherTag. Ports of various RTOSs are
available such as FreeRTOS, Micrium µC/OS, µCLinux…
Going Further
If the computation performance or throughput of the APS5
is stretched by your application there are a number of
possible solutions.
Simple dual core systems, as shown above, can achieve a
CoreMark figure of 3·51 CoreMarks/MHz. This can be
further increased using multi-core architectures, with a
coherent data cache.
Equally it is easy to realise heterogeneous multi-
processor systems, for example pairing an APS5 for time
critical data processing with an APS3 to handle I/O and a
Bluetooth network stack.
Your application could have algorithms that can be helped
by implementing them partially or totally in hardware. The
APS5 features an easy to use, high performance, co-
processor interface. Co-processor instructions suffer no
penalty over native instructions and can fully exploit the
internal registers, out of order completion and pipeline.
Use one of Cortus’ co-processors, or develop your own
and accelerate your application.
Applications
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The APS5 is suited to a wide variety of applications, such
as:
Embedded Control
Encryption and Decryption
Wireless and Wired Communication
Advanced Sensing
Home Automation
Dual and Multi-core Systems
D-Cache
R0 = 0
RTT
CPU Core
ALU
Multiply
Divide
Status
R15
R0 = 0
RTT
CPU Core
ALU
Multiply
Divide
Status
R15
X-Bar
Co
Processor
optional
Co
Processor
optional
X-Bar
optional
I-Cache
I-Cache
Data
Memory
Program
Memory
On-Chip
Debug
&
DMA
Peripherals
Peripherals
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The APS5 shares the low latency, high speed APS bus
architecture with other members of the processor family.
Cortus offers a wide choice of peripherals developed
specifically for the APS family ranging from UARTs,
Counters/Timers to Ethernet MACs and USB2.0 blocks all
supplied with examples and driver code. Also available
are bridges to and from AHB-Lite™.
Counter
Timer with Capture and PWM
UART
GPIOSPII2CWatchdog
USB 2.0 Device & OTG
Ethernet 10/100 MAC
AHB-Lite™ Bridge, master and slave
A wide range of peripherals are available including: