Multi-Project Wafer (MPW) for Prototyping on DALSA Semiconductor ...

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Multi-Project Wafer (MPW) for Prototyping on
DALSA Semiconductor High Voltage CMOS/DMOS
Technologies with MEMS Post-Processing option
    
DES-0041.05


Issued Date: February 7th, 2008




DALSA Semiconductor
18, Boul. de l’Aéroport, J2L 1S7
Bromont, Québec, Canada
Tél : (450) 534-2321
Fax: (450) 534-2168
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 2 of 16
Copyright ©2008 DALSA Semiconductor inc.

This document will be revised and reissued as necessary. DALSA Semiconductor Inc. reserves the right to
make changes herein at any time without notice. DALSA Semiconductor Inc. does not assume any
responsibility or liability arising out of the application or use of any information contained herein. It’s
expressly agreed that DALSA Semiconductor Inc. shall in no event be liable for indirect, incidental or
consequential damages of any nature whatsoever.
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 3 of 16

Table of Contents

CHAPTER 1
WELCOME TO DALSA SEMICONDUCTOR’S MPW SERVICE...........................4
1.1 SCOPE.............................................................................................................................................4
1.2 WHAT’S THE IDEA OF MPW?............................................................................................................4
1.3 TECHNOLOGIES AND DESIGN KITS....................................................................................................5
CHAPTER 2
ACCESS TO MPW SERVICE........................................................................................6
CHAPTER 3
MPW PRODUCT FLOW................................................................................................7
CHAPTER 4
DALSA SEMICONDUCTOR TECHNOLOGIES........................................................8
4.1 CMOS/DMOS TECHNOLOGIES DESCRIPTION...................................................................................8
4.2 MEMS POST-PROCESSING DESCRIPTION..........................................................................................8
4.3 CHARACTERISTICS............................................................................................................................9
4.4 PROPAGATION DELAY.....................................................................................................................10
4.5 CMOS/DMOS TARGETED APPLICATIONS........................................................................................10
4.6 TECHNOLOGY CONSTRAINTS APPLICABLE TO MPW DESIGNS..........................................................11
4.7 DALSA SEMICONDUCTOR 0.8µM DESIGN KIT’S CONTENT...............................................................12
CHAPTER 5
DIE SIZE.........................................................................................................................13
5.1 SIZE DEFINITION.............................................................................................................................13
CHAPTER 6
PRICING.........................................................................................................................14
6.1 CHIP PRICING................................................................................................................................14
6.1.1 Area calculation...................................................................................................................14
6.1.2 Price per mm
2
.......................................................................................................................14
CHAPTER 7
DELIVERABLES...........................................................................................................15
7.1 SCHEDULE.....................................................................................................................................15
7.2 QUANTITIES...................................................................................................................................15
7.3 PACKAGING...................................................................................................................................16


Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 4 of 16

CHAPTER 1
Welcome to DALSA
Semiconductor’s MPW
Service


1.1 Scope
The Multi-Project Wafer User Guide is the document to be read by
everyone who plans to manufacture prototypes of their design in DALSA
Semiconductor technologies.
This User Guide provides you with all the information you need to
fabricate your design using the MPW DALSA Semiconductor strategy.

1.2 What’s the idea of MPW?

DALSA Semiconductor Multi-Project Wafer (MPW) program is
designed to help small, innovative organizations to design and prototype
chips (in small quantities) at a lower cost. By gathering different designs
on the same wafer, the production costs are shared between MPW users
This service is open to commercial companies and academic institutions
such as universities. It offers DALSA Semiconductor advanced
technologies through CMC Microsystems (http://www.cmc.ca)

N.B.:Commercial companies can also access directly DALSA Semiconductor
services.
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 5 of 16

1.3 Technologies and Design Kits

The technologies available under MPW at DALSA Semiconductor are:
CMOS/DMOS Technologies

C08G – 0.8µm 5V/HV CMOS/DMOS process with Design Kit
DK08G
C08E – 0.8µm 5V/20V CMOS process with Design Kit DK08E
C08C – 0.8µm 5V CMOS process with Design Kit DK08C
For more detail refer to chapter 4.



MEMS Post-Processing

C08G+ – MEMS Post-processing on 0.8µm 5V/HV CMOS/DMOS
products with Design Kit MK08I
C08E+ – MEMS Post-processing on 0.8µm 5V/20V CMOS products
with Design Kit MK08I


Used with permission of University of Waterloo
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 6 of 16


CHAPTER 2
Access to MPW Service


MPW users need to follow these steps carefully to have access to
DALSA Semiconductor MPW runs.
Step 1. Enter into a customer agreement with CMC.
Step 2. Sign a Non Disclosure Agreement with DALSA
Semiconductor through CMC (
fab@cmc.ca
)
Step 3. Obtain the design kits for the selected technology or
technologies through CMC. Design kit installation
instructions are provided by CMC.
Step 4. Book space on a target run brokered by CMC
Step 5. Submit DRC clean designs in GDSII to CMC or obtain
waiver (which will be marked with drcignore layer in DB )
on intentional DRC violations> This must be done prior to
run deadline. Please be sure that you comply to the
technology constraints enumerated in section 4.6.
How to contact CMC:
MPW users may send email to
fab@cmc.ca
or telephone at 613-530-
4666 for inquiry or assistance regarding any of the above steps.
Users can find CMC’s fabrication schedule at
www.cmc.ca/about/fab_schedule.html



Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 7 of 16

CHAPTER 3
MPW Product Flow

MPW user designs will go through the following steps after submission
to CMC:
Step 6. CMC checks design database for data integrity and design
manufacturability.
Step 7. CMC transfers required basic technical information
(process flavor, post-processing and die size) to DALSA
Semiconductor 1 week before the run deadline.
Step 8. CMC transfers database, all required technical information
(layers used …) and PO to DALSA Semiconductor.
Step 9. DALSA Semiconductor performs final check, perform the
Mask Data Preparation and sign-off for fabrication.
Step 10. DALSA Semiconductor manufactures prototypes and return
them to CMC
Step 11. CMC returns the prototypes to MPW users
Please refer to Chapter 4 for technology constraints applicable to MPW
designs.

Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 8 of 16

CHAPTER 4
DALSA Semiconductor
Technologies


4.1 CMOS/DMOS Technologies description

MPW projects are supported with access to 3 DALSA Semiconductor
0.8µm technologies and 3 design kits. They are described here:
DK08G Foundry Design Kit is based on DALSA Semiconductor 0.8µm
5V/HV CMOS/DMOS process (C08G). It supports standard CMOS
devices in addition to high voltage devices that can sustain 20V to 300V
typical operating voltages.
DK08E Foundry Design Kit is based on DALSA Semiconductor 0.8µm
5V/20V process (C08E). It supports standard CMOS devices in addition
to scalable high voltage devices limited to 20V typical operating voltage.
DK08C Foundry Design Kit is based on DALSA Semiconductor 0.8µm
5V CMOS process (C08C). It supports standard 3 –5V CMOS.
All manufacturing, design information and IP portfolio specifications
related to a specific technology are included inside the specific design kit.
All 3 design kits are based on Cadence and Synopsys EDA tools.

4.2 MEMS Post-Processing description

DALSA Semiconductor’s MEMS post-process for CMOS/DMOS wafer
from DALSA Semiconductor’s production line is a structural release
process using one mask and a two steps cavity etch:
• 1st stage is an anisotropic etch. Structural materials are metals.
Nitride and oxides are sacrificial. That stage cuts the shapes of
the metal patterns down to the substrate bulk ;
• 2nd stage is an isotropic etch. Structural materials are nitride,
oxides and metals. Silicon is sacrificial. That stage is designed
to etch the silicium bellow the metal patterns.
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 9 of 16
4.3 Characteristics

The next table summarizes some features of the three CMOS/DMOS
technologies.
Design Kit
DK08G
DK08E
DK08C
Process name C08G C08E C08C
Substrate type P
-
/P
+
EPI P
-
/P
+
EPI N
-
Bulk
Transistor type

MOS N/P LV
DMOS 20-
300V
EDPMOS
MOS N/P LV
MOS N/P S ext.
MOS N/P D ext.
MOS N/P LV
Plates 24 21 16
Wells 3 3 1
Conductor
layers
Poly1,Poly2,
metal1, metal2
and metal3
Poly1,Poly2,
metal1, metal2 and
metal3
Poly1,Poly2,
metal1, metal2
and metal3
Gate oxide
thickness
170A/325A 170A/500A 170 A
Threshold
voltage
0.65V/-0.65V
1.2V/-0.8V
0.65V/-0.65V
0.9V/0.9V
-1V/-1V
0.65V/-0.65V
Supply voltage
range
2.7V to 300V 2.7V to 22V 2.7V to 5.5V
Polysilicon
resistor
37 to 5K per
square
37 to 10K per
square
37 to 10K per
square
Capacitor
(poly1-poly2)
1.35 fF/µm
2
0.80 fF/µm
2
1.05 fF/µm
2

Capacitor V
(poly1-poly2)
5V 20V 5V
Bipolar NPN Isolated (17V) Isolated (17V) --
Bipolar PNP Isolated(23V)
140V
Isolated (23V) --
Please consult the User Guide of the appropriate design kit for details.
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 10 of 16

4.4 Propagation Delay

Since each technology is related to a Design Kit, the table below shows
the some characteristics for every DK: the technology, the propagation
delay of 2 standard cells and the circuit density.

Parameter
DK08G
DK08E
DK08C
Process code related C08G C08E C08C
Inverter 0.69ns 0.69ns 0.69ns
2-input NAND 0.85ns 0.85ns 0.85ns
Density of gate per mm
2
2.8K 2.8K 2.8K
N.B.: Propagation delay in nanoseconds at fan-out 2 of same cell type.

4.5 CMOS/DMOS targeted applications


DK08G
DK08E
DK08C
Medium signal
processing for
mixed signal
Medium signal
processing for
mixed signal
Medium signal
processing for
mixed signal
MEMS/microfl
uidics/photonic
s control

MEMS control
HVIC Audio
Smart Power
Integrated
Circuit


Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 11 of 16

4.6 Technology Constraints Applicable to MPW Designs

Please read this section carefully.
• C08C and C08G circuits are processed on the same substrate at
once.
• No starting material other than the P
-
/P
+
EPI is supported. That
means only p-well is supported for C08C IC layout.
• Dies designed with the DK08C will see processing steps for the
C08G. Evaluation of the effect is as follow:
o The capacitance will be the one from C08G
o The resistivity of the poly high-res will be the one of
C08G.

• Dies designed with the DK08C, DK08E or DK08G will also see
processing steps for nbase or poly high-res if any one design on
the run uses nbase and/or poly high-res.
• Only 3-metal processes (not 2-metal processes) are supported.
That means pads must be on metal3.
• The Data Base submitted must not contain scribe line.
• Use Metal 3 pads.
• Any identification must be done on Metal 1 layer for your
protection.
• Dalsa is free to feel the area surrounding the design with any
pattern for ease of manufacturing.

Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 12 of 16

4.7 DALSA Semiconductor 0.8µm Design Kit’s content

Each design kit has its own specific features related to front-end
schematic capture, back-end layout verifications, simulation models, IP
cells, etc. Please consult the User Guide of the appropriate design kit for
details.


Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 13 of 16

CHAPTER 5
Die Size


5.1 Size definition

A few terms must be defined which are specific to MPW projects:
Die size
This is the area occupied by the GSDII database received from
the customer
Diced die size
This is the size of the die that the customer will receive. This size
will be determined during the Mask Data Preparation. It will include the
size of the design database plus additional space and a triple Metal scribe
line required for Mask Data Preparation. This size will be communicated
by DALSA Semiconductor prior wafer fabrication.
Maximum possible diced die size
This is the size of the larger die that a run can accommodate. It is 22mm
x by 20.7mm or 14.7mm x 23.4mm for a rectangular die.
Note: The diced die will be larger than required and it’s a limitation
only for MPW project. If it’s a concern for you, please contact CMC
(
fab@cmc.ca
).

Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 14 of 16

CHAPTER 6
Pricing


6.1 Chip Pricing

6.1.1 Area calculation
For pricing purpose the area used for calculation is based on the die size
definition of the previous section.

6.1.2 Price per mm
2

Pricing is divided in 3 categories:
-
Fixed price for die smaller than 6 mm
2
-
Price is proportional to die size for die between 6 and 36 mm
2.
- Reduced rate for large die


Contact CMC or DALSA Semiconductor for current price list.

Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 15 of 16

CHAPTER 7
Deliverables


7.1 Schedule


Cycle time from the submission of the data base to CMC to the time the
prototypes in loose dies format are delivered to MPW users are:

Process
Voltage
Cycle time
(Weeks)
C08G 5V/HV 16
C08E
5V/20V
19
C08C 5V 16
MEMS P.P. N/A + 2
These cycle times are for references only.
Please consult the CMC site for runs schedule at
http://www.cmc.ca/about/fab_schedule.html .
Packaging, if required, is handled separately and requires additional cycle
time.

7.2 Quantities

Thirty (30) untested dice will be delivered in tray pack.
Additional dice could be available at extra charges. Customers can make
arrangement with CMC prior to design submission for additional dice.
Special discount may be applied on additional order base on the product
mix of the MPW run and the quantities required.
Copyright 2008, DALSA Semiconductor Inc. All right reserved. DES-0041.05 Page 16 of 16

7.3 Packaging

Packaging is not included and must be arranged separately if required.
Contact CMC or DALSA Semiconductor for more information.