Vertical ZnO Nanowire Field Effect Transistor

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2 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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Vertical ZnO
Nanowire
F
ield Effect Transistor


Abstract



In order to fully utilize the scaling advantage of
quasi
-
one
-
dimensional nanostructures
,
v
ertically
grown ZnO nanowires
have been successfully

fabricated
using
DC and pulse
d

electrodeposition method
s

in a

highly ordered
anodic aluminum
template.
An evaporated layer of
titanium

on one side of the template serves as the working electro
de in a standard three
electro
chemical

cell.
It is found that pulsed electrodeposition grows Zn nanowires with
a
much
h
igher filling factor and uniformity.
The
ZnO
nanowires
we
re

formed by thermal
ly

oxid
izing
the
Zn nanowires
.

XRD spectra of increasing oxidation time show t
hat the as grown Zn was
gradual
ly
converted to ZnO.
The
electrical transport
propert
y

of
individual
n
anowires
was

characterized
with
an
atomic force microscope

using conductive probes
.
Vertically aligned field effect
transistors
will be

constructed, which
will
serve as the building blocks for
nanoscale

memory and

logic
devices.

Introduction


The fabricati
on and characterization of various types of nanowires have been given
consider
able interest in recent years.
In particular, methods of fabrication such that subsequent
characterizations are easily repeatable

and consistent are desirable.
This is largely du
e to the
unique hurdles one must clear when dealing wi
th phenomena on the nanoscale.
These difficulties
have materialized two distinct methodologies for synthesizing nanoscale devices

bottom up and
top down approaches.


In this project, a highly ordered po
rous alumina template was utilized to grow ZnO
nanowires from the bottom of the
pores up via electrodeposition.

The hexagonally repeatable
pattern of the template ideally overcomes the problem of locating and characterizing a single
nanowire on a consisten
t bas
is.
Previous methods of single nanowire characterization have
involved processes that are not ideally suited for actual device fabrication due to their low yields.


The future of being able to grow ZnO nanowires in a vertically aligned substrate appea
rs
b
right.
Small scale transistors can be made from two wires se
parated by a layer of alumina.
The
layout of the device is such that simple logic gates and memory elements could be created on one
chip with a characteristic length that is competitive with t
oday’s transistor size.


This report focuses on the device fabrication itself and provides preliminary data on the
as
-
grown wires.

Experimental


To fabricate the alumina template with the desired pore diameter and interpore distance, a
two
-
step anodization

process was e
mployed.
First, 99.99% pure, .25mm thick aluminum was
mec
hanically polished on one side.

A mixture of HClO
4

and ethanol was then used to electrically
finish the polishing at 5V for 3 minutes.


The first anodization was carried out at 60V in a

solution of rigorously stirred
.1 M oxalic
acid for one hour. This approximately yields a

20 micron thick alumina layer, which is
subsequently removed by immersing the chip into a mixture of 1.8 wt% chromic acid and 5 wt%
phosphoric acid for two hours.
Th
e second anodization is performed under the same parameters,
except 30 minutes is used instead of one hour to a
chieve a 10 micron thickness. T
o ensure all of
the pores

are open throughout their entirety, the chip is briefly immers
ed into 5 wt% phosphoric
a
cid.
This process yields an average pore diameter of 80
-
100 nm and an interpore disatance of

140
-
150 nm
.


The side that was polished is then coated with roughly 70nm of titanium and then ano
ther
100nm of gold after that.
This provides the device with a wor
king electrode that will be used in
the electrodeposition.


The chip is then bonded to a glass slide for stability u
sing a high temperature epoxy.
The top
layer of alumina and the bulk aluminum are removed by placing the device into saturated mercuric
chlo
ride, which se
lectively etches the aluminum.
The top of the remaining alumina layer is
typically covered by a barrier layer which is removed using a

Gatan Duomill

ion mill
ing machine
.


Our initial efforts using Pulsed Electrodeposition (PED) were a pulse w
ith a current density
of 70ma/cm
2

for 10ms, with a rest period of

10 seconds.
The voltage was carried out relative to a
standard calomel reference electrode with a carbon counter electrode in a three e
lectrode
electrochemical cell.
As was mentioned above,
the titanium evaporated on the one side of the
alumina layer served as the working electrode.


Preliminary thermal oxidization at
BLANK

was carried out for
two hours

and XRD
measurements were made during this process to track the removal of Zn and subseque
nt formation
of ZnO.


A Digital Instruments MultiMode

AFM was used to characterize the electrical transport
properties of the purely Zn wires and will be used in the near future to measure those same
properties of ZnO.

Results and Discussion


Once the devi
ce fabrication process parameters were well developed and understood, the
emphasis fell
on the electrodeposition step.
Achieving uniform and complete growth throughout a
majority of the p
ores remains the primary issue.

Originally, a DC method of supplying
c
urrent to
the system was used.
This gave varying results, none of which we
re desirable.
Either only a few
pores would actually nucleate and grow a wire, resulting in large crystals on top of the alumina
template, or the growth in the pores was irregular a
nd did not fill them with uniform diameters.


In order for there to be any growth, much less uniform growth, there must be enough Zn
2+

ions at the nucleation site to form Zn
0
.
In addition, there has to be an appropriate amount of
current supplying electro
n
s to drive the same reaction.
The problem with DC electrodeposition is
that it is constantly supplying the electrons needed, so Zn
2+

will form Zn
0

almost anywhere it can.
This yields two
results, as mentioned earlier.
One, only 1% of the potential nucleat
ion sites (i.e.
the bot
tom of a pore) actually grows.
Because of a random distribution of diffusion times for any
given number of electrolyte ions, some pores have an abundant amount of Zn
2+

ions throughout
their entire length. Once a pore is preferred und
er DC conditions, it continues to be the main site
of growth. Even if ample time is allotted for the electrolyte to initially diffuse to all the pores,
growth within a single pore seems uneven.


The motivation behind using PED as an alternate filling metho
d mostly involves the

diffusion
of the electrolyte.
PED allows for diffusion time not only in the beginning of the electrodeposition,
which increases the filling factor, but also throughout its duration, which improves the
quality of
individual filling.
Pr
eliminary attempts at utilizing these features have increased pore filling factor

from approximately 1% to 75%.
In addition, the pores are individually filled evenly, as is shown
in

Figure 1b
.


Fig.1
: A. DC electrodeposition; B. PED. Notice the filling

factor has significantly increased.


Initial XRD data suggests that thermally oxidizing the as
-
grown Zn wires in air effectively
converts them to ZnO. This is seen in Figure 2, where the two dominant peaks of Zn diminish with
oxidization time. It is yet t
o be seen exactly how long the full transition will take, however.

A

B


Fig.2
: A. No annealing time; B. After 2 hours of annealing.


Figure 3
shows an IV curve t
aken from a single Zn nanowire.

The nonlinear nature of the
curve is
due to the fact that the nanowires are actually depressed beneath the surface of the

surrounding alumina template.
To an AFM probe, this essentially translates into six peaks around
the depressed wire, d
ue to its hexagonal structure.
This prevents the cond
ucting probe from
making good contact with the wire; hence, a resistance associated with thi
s gap is seen on the IV
curve.
Also,
the nonlinear shape of the curve is indicative of a Schottky junction, meaning that the
A

B

top couple

nanometers of the wire have
converted to ZnO
.

Future electrical transport
measurements will be taken once Zn has been sufficiently converted to ZnO.



Fig.3
:
I
-
V

Curve shows the Shottky contact between the probe and the nanowire.

Conclusion


Zn nanowires we
re fabricated in a vertically aligned hexagonally ordered alumina template
via PED. The wires exhibited Schottky electrical transport behavior when measure with AFM
techniques. Preliminary oxidization efforts showed the diminishing of Zn in the device and
it is
expected that ZnO will form with more annealing time. Small scale transistors will be fabricated
using the wires as the basic template.

Acknowledgements


I would like to acknowledge Jia Lu and her research group (Joseph Fan, Dawei Wang, Marco
Huang,
and CJ Chien) who all contributed a great deal toward this project. Also,
acknowledgements go out to Said Shokair and the IM
-
SURE program for making available this
opportunity, and the National Science Foundation for their funding and support.

References

1.

Y. Li, G.S. Cheng, and L.D. Zhang
, J. Mater. Res., Vol. 15, No. 11, (2000).

2.

K. Nielsch, F. Müller, A.
-
P. Li, U. Gösele
, Adv. Mater. 2000, 12, No. 8.