UNIT I : MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES 9

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DOC/LP/01/28.02.02


UNIT I
:
MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES


9



Depletion region of a PN junction


large signal behavior of bipolar transistors
-

small signal

model of bipolar transistor
-

large sig
nal behavior of MOSFET
-

small signal model of the

MOS
t
ransistors
-

short channel effects in MOS transistors


weak inversion in MOS

transistors
-

substrate
current flow in MOS transistor.

Objective:




To
S
tudy
and Understand
the large signal and small signal

models of active devices
.











LESSON PLAN

LP


AP9221

LP Rev. No: 0
0

Date:
04/02/2013

Page 01 of 06

Sub Code & Name:
AP9221
-

Analysis and
D
esign of
A
nalog

I
ntegrated
C
ircuits



Unit : I Branch :
M.E Applied Electronics


Semester: I
I

Session
No.

Topics to be covered

Time

Ref

Teaching
Method



1

Introduction
-
A
nalog i
ntegrated Circuits,
PN
J
unction diode

50m

1,
3

BB

2

Depletion region of a PN junction

50m

1,
3

BB

3

Large signal behavior of bipolar tran
sistors

10
0m

1,
3

BB

5

S
mall signal model of bipolar transistor


50m

1,
3

BB

6

Large signal behavior of MOSFET

50m

1,3

BB

7

S
mall signal model of the MOS transistors


50m

1,3

BB

8

S
hort channel effects in MOS transistors

50m

1,3

BB

9

W
eak inversion in M
OS

t
ransistors
-

S
ubstrate
current flow in MOS transistor.


50m

1
,3

BB

10

Problems

50m

1,3

BB

DOC/LP/01/28.02.02


UNIT II


CIRCUIT CONFIGURATION FOR LINEAR

IC



9



Current sources, Analysis of difference amplifiers with active load using BJT and FET,supply and
temperature independent biasing techniques, voltage references. Output stages:Emitter follower, source
follower and Push pull output stages.

Objectives:

T
o study
about t
he working principle of difference amplifier.


Session
No.

Topics to be covered

Time

Ref

Teaching
Method

11

Current sources

50m

1

BB

12

Analysis of difference amplifiers with active load using
BJT

50m

1

BB

13

Analysis of difference amplif
iers with active load using
FET

50m

1

BB

14

Supply and temperature independent biasing
techniques

10
0m

1

BB

16

Voltage references


100
m

1

BB

18

Output stages: Emitter follower, source follower Push
pull output stages.


50m

1

BB

19

Output stages: Push p
ull output stages.


50m

1

BB

20

Problems

50m

1

BB
















LESSON PLAN


LP


AP9221

LP Rev. No: 00

Date:
04/02/2013

Page 02 of 06

Sub Code & Name:
AP9221
-

Analysis and
Design of Analog

Integrated Circuits



Unit : II

Branch :

M.E Applied Electronics



Semester: I
I


DOC/LP/01/28.02.02


UNIT III OPERATIONAL AMPLIFIERS

9




An
alysis of operational amplifiers circuit, slew rate model and high frequency analysis,

Frequency response of integrated circuits: Single stage and multistage amplifiers,Operational
amplifier


noise.


Objective
:
To Understand the characteristics of Operat
ional amplifier


Session
No.

Topics to be covered

Time

Ref

Teaching
Method

21

Analysis of operational amplifiers circuit, slew rate
model


100
m

1,

BB

23

H
igh frequency analysis


10
0m

1

BB

25

Frequency response of integrated circuits: Single stage

ampli
fiers


50m

1

BB

26

Frequency response of integrated circuits: multistage
stage amplifiers


10
0
m

1

BB

28

Operational amplifier noise


5
0
m

1

BB

29

Problems

50
m

1

BB
















LESSON PLAN


LP


AP9221

LP Rev. No: 00

Date:
04/02/2013

Page 0
3

of 06

Sub Code & Name:
AP9221
-

Analysis and Design of Analog

Integ
rated Circuits



Unit : III

Branch :

M.E Applied Electronics



Semester: I
I


DOC/LP/01/28.02.02


UNIT IV



ANALOG MULTIPLIER AND PLL

9


Analysis of four quadrant and variable trans conductance multiplier, voltage controlled

oscillator, closed loop analysis of PLL, Monolithic PLL design in integr
ated


circuits:

Sources

of noise
-

Noise models of Integrated
-
circuit Components


Circuit Noise Calculations

Equivalent Input Noise Generators


Noise Bandwidth


Noise Figure and Noise


Temperature.

Objective:




To
study about the working of analog multi
plier

and PLL.



To understand the noise models of IC
.


Session
No.

Topics to be covered

Time

Ref

Teaching
Method

30

Analysis of four quadrant and variable trans
c
onductance multiplier


50m

1,

BB

31

Voltage controlled oscillator


50m

1

BB

32

Closed loo
p analysis of PLL


50m

1

BB

33

Monolithic PLL design in integrated circuits


50
m

1

BB

34

Sources of noise


50
m

1
,5

BB

35

Noise models of Integrated
-
circuit Components


50
m

1

BB

36

Noise models of Integrated
-
circuit Components


50
m

1

BB

37

Circuit No
ise Calculations, Equivalent Input Noise
Generators

50
m

1

BB

38

Noise Bandwidth
, Noise Figure and Noise

Temperature.


50
m

1

BB

39

Problems

50
m

1

BB





LESSON PLAN


LP


AP9
221

LP Rev. No: 00

Date:
04/02/2013

Page 04

of 06

Sub Code & Name:
AP9221
-

Analysis and Design of Analog

Integrated Circuits



Unit : I
V

Branch :

M.E Applied Electronics



Semester: I
I











DOC/LP/01/28.02.02


UNIT V

ANALOG DESIGN WITH MOS TECHNOLOGY

9


MOS Current Mirrors


Simple, Cascode, Wilson and Wi
dlar current source


CMOS Class

AB output stages


Two stage MOS Operational Amplifiers, with Cascode, MOS Telescopic
-

Cascode Operational Amplifier


MOS Folded Cascode and MOS Active Cascode

Operational Amplifiers

Objective:



To
study about the

current
sources and MOS operational amplifiers
.


Session
No.

Topics to be covered

Time

Ref

Teaching
Method

40

MOS Current Mirrors


Simple, Cascode

100m

1,
5

BB

42

Wilson and Widlar current source

50m

1

BB

43

CMOS Class AB output stages


Two stage MOS
Operatio
nal Amplifiers with Cascode


10
0m

1

BB

45

MOS Telescopic
-

Cascode Operational Amplifier


50m

1

BB

46

MOS Folded Cascode Operational Amplifiers

50m

1

BB

47

MOS Active Cascode Operational Amplifiers


50m

1

BB

48

Problems

50m

1

BB


















LESSON PLAN


LP


AP9221

LP Rev. No: 00

Date:
04/02/2013

Page 0
5

of 06

Sub Code & Name:
AP9221
-

Analysis and Design of Analog

Integrated Circuits



Unit : V

Branch :

M.E Applied Electronics



Semester: I
I



D
OC/LP
/01/28.02.02


Course Delivery Plan:






REFERENCES:

1. Gray, Meyer, Lewis, Hurst, “Analysis and design of Analog IC’s”, Fourth Edition, Willey

International, 2002.

2. Behzad Razavi, “Principles of data conversion system design”, S
.Chand and company

ltd, 2000

3. Nandita Dasgupata, Amitava Dasgupta,”Semiconductor Devices, Modelling and

Technology”, Prentice
Hall of India pvt. ltd, 2004.

4. Grebene, Bipolar and MOS Analog Integrated circuit design”, John Wiley &

sons,Inc.,2003.

5. Phi
llip E.Allen Douglas R. Holberg, “CMOS Analog Circuit Design”, Second Edition
-

Oxford University Press
-
2003
.



LESSON PLAN


LP


AP9221

LP Rev. No: 00

Date:
04/02/2013

Page 0
6

of 06

Sub Code & Name:
AP9221
-

Analysis and Design of Analog

Integrated Circuits



Branch :
M.E Applied Electronics






Semester: I
I


Week

1

2

3

4

5

6

7

8

9

10

11

12

13

I II

I II

I II

I II

I II

I II

I II

I II

I II

I II

I II

I II


I

-


UNIT


1


1

1

1

1

2

2

2

2

2

3

3

3

3

3

4


4


4

4

4


4


5

5

5

5

5

T
EST

-

T1

T2

T3

T4

T5


T6

T7

T8

T9

C
A
T

I

T10

T11

C

A

T

II


Prepared

by

Approved by

Signature




Name

M.Anushya


Dr.S.Ganesh Vaidyanathan


Designation

Asst.Prof

HOD, Department of ECE

Date

04
/
02
/201
3

04/02/2013

Note
:
T1,…
, T1
1
: Weekly
Test;

CAT: Continuous Assessment Test