Project TE 316, Existing Example No. C 7 Level/Categories CL: 1a, 1b, 3b AL: 1a, 1b, 3b

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Project

TE
316
, Existing Example No.
C 7



Level/Categories



CL: 1a, 1b, 3b

AL: 1a, 1b, 3b





Documents (Classification is Based on [Document Number, e.g., US 3 958 369A])




DE 22 01

824 A1

FR 2

088

338 A5

GB 1

284

257 A



Short Version of the Disclosur
e


A monolithic semiconductor circuit comprises a lateral PNP transistor and an inversely
operated vertical NPN transistor. The lateral transistor is formed by a pair of mutually spaced
P
-
type regions diffused in an N
-
type semiconductor body. The collector

region has diffused
therein a region of N
-
type and constituting the collector of the vertical transistor. The
semiconductor body constitutes the base region of the lateral transistor and the emitter region
of the vertical transistor.



Representative Prio
r Art
(only for Category 3)


With regard to bipolar circuits in monolithic technology, an improvement over provid
ing

separate isolation pockets for each circuit
element

consists in grouping several circuit
components in one isolation pocket. Semiconductor
zones connected to the same potential are
preferably jointly integrated. It is also known for NPN and PNP transistors to be jointly
integrated in a four
-
layer structure. In a known circuit of this kind the NPN transistor
integrated jointly with the PNP tra
nsistor acts as
anti
-
saturation
. T
hese known circuits cannot
be realized without area
-
consuming isolation diffusion, nor do they lead to a simplification of
or savings in the process steps employed
.



Invention Information


Grouping several circuit compone
nts in the same isolation pocket is known in the prior art
(see above)
.
The addition to the prior art is to group a lateral PNP transistor and vertical NPN
transistor in the same group.
The addition to the prior art
provides
a simpler production
process, e
liminating isolation diffusion, and a higher packing density.



In the description a number of logic combinations/circuits realized using the combination of
lateral and vertical transistors. The applicant does not claim novelty of the
logic
combinations/ci
rcuits, but states that “It is known for logic combinations to be realised merely
with the aid of NOR circuits.” (page 2, lines 47 and 48).


In summary, the following piece of Invention Information is identified:


I1:
a monolithic
semiconductor
integrated
circuit utilizing a combination of lateral and
inversely operated
vertical bipolar transistors



Additional Information

(only for Category 3)


The information about realizing different
logic combinations/circuits

serves as illustrating
different applicatio
ns of the invention and should, for search reasons, be classified as
Additional Information:


A1: the application of I
1 when realizing different logic circuits



Identification of Potential Subclasses


By using a term search

in the IPC Catchword Index
the
potentially appropriate IPC places for
invention information and addit
ional information
are identified.

Obvious alternatives like
“semiconductor device” and “logic circuit” have been used in the queries.




Subject Matter

Tool

Query

IPC Places

I1

Cat chwor
d Index

SEMICONDUCTOR devices

H01L

A2

Catchword Index

Electric LOGIC circuits

H03K 19/00



Analysis and Selection of Classification Symbols


Core Level


I1


The title of H01L is
“Semiconductor devices;...”
. This clearly provides for the invention
.


The t
itle of main group H01L 27/00 is
“Devices consisting of a plurality of semiconductor or
other solid
-
state components formed in or on a common substrate”

and H01L 27/02
“including semiconductor components specially adapted for rectifying, oscillating, ampli
fying
or switching and having at least one potential
-
jump barrier or surface barrier; including
integrated passive circuit elements with at least one potential
-
jump barrier or surface barrier”
is the only relevant one
-
dot subgroup. The invention concerns m
onolithic circuits on a
semiconductor substrate and, thus, H01L 27/04 “the substrate being a semiconductor body”

is
the appropriate two
-
dot subgroup. Three
-
dot subgroups H01L 27/06 and H01L 27/10 under
H01L 27/04 cover “including a plurality of individual
components in a non
-
repetitive
configuration” and “including a plurality of individual components in a repetitive
configuration”
, respectively
. According to note (2), by “component” is meant an electric
circuit element, which is one of a plurality of eleme
nts formed in or on a common substrate.
The invention concerns integrated circuits and said three
-
dot groups are not appropriate places
for classification.
The three
-
dot subgroup H01L 27/08 “including only semiconductor of a
single kind” and its four
-
dot s
ubgroup H01L 27/082 “including bipolar components only”,
however, provides for the invention and said four
-
dot subgroup would the correct place for
classifying I1.


Classifying in main group H01L 29/00 “
Semiconductor devices specially adapted for
rectifyin
g, amplifying, oscillating or switching and having at least one potential
-
jump barrier
or surface barrier; Capacitors or resistors with at least one potential
-
jump barrier or surface
barrier, e.g. PN
-
junction depletion layer or carrier concentration layer;

Details of
semiconductor bodies or of electrodes thereof
” could be considered. However, sa
i
d main
group refers to main group H01L 27/00 when the invention concerns “
devices consisting of a
plurality of solid state components formed in or on a common subst
rate
”, which I1 does. Main
group H01L 29/00
may
, thus, be discarded.


A1


The title of
subclass
H03K is
“Pulse technique”
, which has to be understood in the context
of the title of class H03, which is
"Basic electronic

circuitry
"
.

Note (1) of H03K states t
hat
the subclass covers logic circuits. This clearly covers I1.


Main group H03K 19/00 covers
“Logic circuits,…”,
and one
-
dot subgroup H03K 19/02
covers “using specified components”. The title of two
-
dot subgroup H03K 19/08 is “using
semiconductor devices”

and that of three
-
dot subgroup H03K 19/082 is “using bipolar
transistors”. Three
-
dot subgroup H03K 19/082 is, thus, clearly the correct place for
classifying A1.


Advanced Level


I1


The title of H01L is
“Semiconductor devices;...”
. This clearly provides
for the invention.


The title of main group H01L 27/00 is
“Devices consisting of a plurality of semiconductor or
other solid
-
state components formed in or on a common substrate”

and H01L 27/02
“including semiconductor components specially adapted for recti
fying, oscillating, amplifying
or switching and having at least one potential
-
jump barrier or surface barrier; including
integrated passive circuit elements with at least one potential
-
jump barrier or surface barrier”
is the only relevant one
-
dot subgroup.

The invention concerns monolithic circuits on a
semiconductor substrate and, thus, H01L 27/04 “the substrate being a semiconductor body” is
the appropriate two
-
dot subgroup. Three
-
dot subgroups H01L 27/06 and H01L 27/10 under
H01L 27/04 cover “including a

plurality of individual components in a non
-
repetitive
configuration” and “including a plurality of individual components in a repetitive
configuration”, respectively. According to note (2), by “component” is meant an electric
circuit element, which is on
e of a plurality of elements formed in or on a common substrate.
The invention concerns integrated circuits and said three
-
dot groups are not appropriate places
for classification. The three
-
dot subgroup H01L 27/08 “including only semiconductor of a
single

kind” and its four
-
dot subgroup H01L 27/082 “including bipolar components only”,
however, provides for the invention and said four
-
dot subgroup would the correct place for
classifying I1.


Classifying in main group H01L 29/00 “
Semiconductor devices specia
lly adapted for
rectifying, amplifying, oscillating or switching and having at least one potential
-
jump barrier
or surface barrier; Capacitors or resistors with at least one potential
-
jump barrier or surface
barrier, e.g. PN
-
junction depletion layer or car
rier concentration layer; Details of
semiconductor bodies or of electrodes thereof
” could be considered. However, said main
group refers to main group H01L 27/00 when the invention concerns “
devices consisting of a
plurality of solid state components forme
d in or on a common substrate
”, which I1 does. Main
group H01L 29/00 may, thus, be discarded.


A1


The title of subclass H03K is
“Pulse technique”
, which has to be understood in the context
of the title of class H03, which is
"Basic electronic

circuitry
"
.

Note (1) of H03K states that
the subclass covers logic circuits. This clearly covers I1.


Main group H03K 19/00 covers
“Logic circuits,…”,
and one
-
dot subgroup H03K 19/02
covers “using specified components”. The title of two
-
dot subgroup H03K 19/08 is “usi
ng
semiconductor devices” and that of three
-
dot subgroup H03K 19/082 is “using bipolar
transistors” and said three
-
dot subgroup clearly covers A1. Of the four
-
dot subgroups under
H03K 19/082 H03K 19/091 covering “Integrated injection logic or merged transi
stor logic”
could be relevant. Integrated Injection Logic
comprises

a PNP lateral transistor and an
inverted
vertical NPN transistor and merged transistor logic may comprise lateral and vertical
bipolar transistors. Therefore, H03K 19/091 covers A1 and sai
d four
-
dot subgroup is the
correct place for classification.




Subject
Matter

Analysis of Subclass
Selection

Subclass

Analysis of Group Selection

IPC CL

IPC (2006)

IPC AL

I1

Not e in H01L

H01L

Common rule

H01L 27/082

H01L 27/082

A1

Note in H03K

H03K

Comm
on rule

H03K 19/082

H03K 9/091



Complete Classification


The complete core and advanced level classification for this document based on the above
analysis is as follows:


Core Level


Int. Cl. (2006)

H01L 27/082

H03K 19/082


Advanced Level


H01L 27/082

(2
006.01)

H03K 19/091

(2006.01)