EE114: Project Report

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1





EE
114
: Project Report







Group Members:

Luke
Ekkizogloy
, ID: 05516859, SCPD,
lukee@stanford.edu


Hesam Fathi Moghadam, ID: 05494955, SCPD,
hfathimo@stanford.edu




















Date Due:
November 21
, 2008


2

Table of Contents


1

DESIGN OUTLINE

................................
................................
................................
................................
................................
...........

3

2

SCHEMATIC
................................
................................
................................
................................
................................
.......................

5

3

CALCULATIONS OF DESI
GN PARAMETERS

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................................
................................
....................

6

3.1

P
ARAMETER
R
ANGE
D
ETERMINATION

................................
................................
................................
................................
..........

8

4

RESULTS
................................
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................................
................................
................................
..............................

9

4.1

S
IMULATED
B
ODE
P
LOT

................................
................................
................................
................................
................................
..

9

4.2

T
RANSIENT
S
IMULATION
P
LOT
................................
................................
................................
................................
.....................

10

5

CONCLUSIONS

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...............
11

6

APPENDIX

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.........................
12

6.1

S
PICE
N
ETLIST
................................
................................
................................
................................
................................
.................

12

6.2

S
PICE
.OP

O
UTPUT

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................................
................................
................................
................................
.........

13




3

1

Design Outline


The EE114 project

objective

was to
port a given

o
perational trans
resistance a
mplifier

(
schematic shown
in section two
) to the 1µm technology
. This involved

choosing the size of the

transistors

and resistors

to
achieve a set of specifications. This particular problem called for

maximizing the bandwidth of the

circuit while maintaining a power and gain target. Our initial approach to solving this problem was to
reach a closed form approximation for the

gain,

power

consumption,

and
bandwidth
.

To do this we first
identified all the
amplifier

stages, namely a common gate input,
cascode
differential pair middle stage
and a common drain output stage. Next the biasing structures were identified


the common drain gets
bi
ased by a ‘magic battery’ (or diode connected NMOS transistors), the
cascode
differential pair
input
gets biased by a resistor divider network
, the common gate stage of the cascode differential pair gets
biased by two series transistors (the bottom one in
triode region)

and the final common drain stage gets
biased by a resistor divider network.


After understanding the given circuit architecture, the next step was formulating the equations for gain,
power consumption and bandwidth. These equations and the a
ssociated assumptions to make the design
complexity manageable are discussed in section three of this report.


Having all the required equations on paper, we chose Maple as our calculation and optimization tool
.
A

set of ‘knobs
,


namely input transistor wi
dth of each of the three stages, current through each of the three
stages and the voltage gain of the cascode differential pair were chosen and
Maple
was used to optimize
the bandwidth while meeting the gain and power constraint.
We chose to manipulate the

currents in each
of the stages of our amplifier as well as the gain of the differential pair while holding constant the total
power consumption of the amplifier as well as the total transresistance gain.
Using Maple, we generated
multiple tradeoff curves
(
shown in section 3
) and got a good understanding of what transistor sizes,
currents and overdrive voltages are feasible.
With this we were able to find an operating point which
allowed us to implement a basic netlist in
H
SPICE

using ideal current and volt
age sources.
It should be
noted that the mentioned knobs were chosen because they can be directly incorporated into the netlist
with little effort.


The next step was replacing all the ideal sources with transistors. One of the assumptions we used in our
M
aple calculations was the
voltage
bias points of the 2
nd

and 3
rd

amplifier stages that is setup by the
resistor divider network.
T
he transistors acting as current and voltage sources were sized based on
required
current and bias conditions required to meet

the assumed voltage bias points of the 2
nd

and 3
rd

stage (
more detail in section 3
). Following the replacement of all the ideal sources, the gain and power
consumption of the amplifier were retrieved and compared to the targets and calculations


they wer
e
similar.


Given that the disregarded parasitic capacitances of the current and voltage sources were now known, a
MATLAB script was generated that incorporated these values

along with more exact equations that
incorporated body effect
. A constrained non
-
linear optimization problem was formulated

in the script to
maximize the bandwidth while meeting the gain and power constraints. The optimizer was semi
-
successful as will be described in the comments and conclusions section, so sweeps of transistor sizes,
overdrive voltages and resistor values were done to find the true optimal solution based on the equations
in the script.



4

Finally, after incorporating all the MATLAB script results into the circuit, further optimization of
bandwidth was done by using intu
ition and doing some simple sensitivity analysis as will be described
in
section 3
.









5

2

Schematic


<
Please see next page.
>


6

3

Calculations of Design Parameters


Initial calculation
s were performed in Maple and

equation
s

were
created to estimate the bandw
id
th given
our gain and power consumption constraints
. We took the liberty of making a number of gross
approximations to simplify the equation and solution space. Since we did not know the sizes of the
current mirror transistors and we only needed sizes so

that we can start implementing a simplified circuit
in SPICE, we completely ignored the capacitances from all the current mirror transistors. Additionally
we lumped together the differential pair transistors M2 and associated cascoded transistors M2C as a

single transistor. This can be done since the capacitance at the node between them is relatively small and
the impedance is
also relatively small
. We then used the Miller Theorem to move the gate to drain
capacitance to the gate input. We also used the Mi
ller Theorem to simplify the gate to drain capacitance
at M3 as well. This leaves four nodes to analyze.


We approximate all capacitances as fractions of
Cgs
.



Node 1 is the input between M1 and MBN1. We ignore MBN1 completely and simplify.




Node
2 is the input to M2a. We ignore MBP1 and add the Miller capacitance of
.




Node 3 is the input to M3a. We ignore MBP2a and add the Miller capacitance of
.




Node 4 is the output node of the amplifier. We ignore MBN3a and add the Miller capacit
ance of

.
This negative capacitance essentially cancels out the C
sbM3
capacitance. This approximation is valid since the load capacitor dominates.




We then write equation for the gain of our amplifier. This is one of our constraints.



7

Additionally w
e define the small signal gain of the differential pair in our amplifier and use that as an
additional design parameter. This helps simplify the equations and removes the resistors from the
bandwidth equation simplifying it further.



We then manipulate t
he equations to remove the dependence on the resistors and write Maple functions
to evaluate our time constants in terms of gm, C
gs
, and gain of our differential pair.






For an additional constraint, we can write the power consumption of our amplifi
er in terms of the
currents through our transistors.


If we minimize currents through the bias networks to save power we simplify to:



In order to constrain our power consumption, we write I
M2a

in terms of I
M1

and I
M3a
. We then only adjust
I
M1

and I
M3a

and I
M2a

will be calculated so that our power specification is never violated. By substituting
expressions for
g
m

and
C
gs

we can define bandwidth entirely with the widths of the three main
transistors, the currents through two of them and the gain of our
differential pair.





The design parameters we chose to manipulate are the widths of the transistors, the currents through the
transistors and the gain of the differential pair in the design. We formulated a function that calculates
bandwidth given th
ose parameters. We then ran Maple’s non
-
linear optimization tool on this function to
attempt to find a good starting point.




This starting point indicates a bandwidth of 45 MHz with parameters of W
M1
=20u, W
M2
=5u,
W
M3
=52.7u,
av

= 3.55, I
M1
=444uA and I
M3
=350uA. Once an initial point is found, we can then graph the
bandwidth as a function of two variables at a time. This graphical analysis allows us to reduce the

8

solution space for all the variables. Additionally it gives us intuition about the sensitivity

of our circuit to
any of these parameters.


<Insert Bandwidth Graphics or reference to >


3.1

Parameter Range Determination


Using the graphs generated from Maple we extracted a rough solution space for all our variables.
Table
1

i
ndicates the low and high end of our solution space as well as the actual value used in the final design
of our circuit. Please note that even though the solution space was calculated using gross
approximations, the optimized and simulated values used in o
ur circuit lie within our solution space.

The
analysis performed to reach the used values in this table is

detailed in SECTION XXXX



Table
1
:
Summary of parameter ranges


Parameter

Low

High

Value
Used

Description

W
M1

16u

46u

35u

W
idth of transistor M1

W
M2

5u

12u

11u

Width of transistors M2a and M2b

W
M3

45u

98u

50u

Width of transistors M3a and M3b

av

3.5

8

??

Gain of the differential pair stage

I
M1

275u

550u

298u

Current flowing through M1

I
M3

240u

420u

357u

Current flowing thr
ough M3a


9

4

Results

4.1

Simulated Bode Plot




Figure
1
.
Simulated Bode Plot of A(jω), Magnitude and Phase



ANOTATE HANDCALCULATED VALUES ON THE SAME PLOT










10

4.2

Transient Simulation Plot




Figure
2
.
Trans
ient Simulation Plot of V
op
, V
om
, V
od

(Input Amplitude/Frequency = 20µA/1MHz)


ANNOTATE EXPECTED QUIESCENT POINTS AND PEAK VOLTAGES USING HORIZONTAL
MARKER LINES.




11

5

Conclusions


In conclusion ….










12

6

Appendix

6.1

Spice Netlist


<Insert Spice Netlist>







13

6.2

Spice .OP Output



<Insert Spice OP Output>