Chapter 3 CMOS Processing Technology (III)

parkagendaΗλεκτρονική - Συσκευές

2 Νοε 2013 (πριν από 3 χρόνια και 7 μήνες)

53 εμφανίσεις

Chapter 3

CMOS Processing Technology (III)



Making a wafer base


(a)




Use seed crystal of Si


Czochralski method of crystal growth


(b)




Slice into wafers


(c)




Wafer and chips


(d)




Wafer sites (die, test)










Process steps

(A) Change su
rface material

(B) Add material

(C) Remove material


(A)

Change surface material



Ion implantation
: impurities are implemented into surface of the
wafer






Brutally forced atoms into the silicon crystal will
damage

the
crystal lattice



To repair the crys
tal lattice, the wafer is
annealed

(heating it)



Second effect of heating:
Diffusion
!




(B) Adding a layer



Epitaxial deposition
: growing a new layer of Sillicon while
maintaining the lattice structure

--
approach:
C
hemical
V
apor
D
eposition (CVD)




Ar
range for highly reactive gases to pump in.



Mixture of gases reacts with each other.



Reacted gases travel through the tube until they encounter wafer



Silicon of the mixture condenses on the surface, giving a nice
epitaxial layer


(
C
) Adding a layer


--

Patterning silicon dioxide through
Optical Lithography

(
transfer

a
pattern to a layer on a chip is called Lithography)




In each process, certain areas are
defined

on chip by appropriate
masks
.



The integrated circuit may be viewed as a set of patter
ned layer
of
:

(a) Doped silicon

(b) Polysilicon

(c) Metal (Al, Cu)

(d) Insulating SiO
2






Use of E
-
beam


For accurate generation of high
-
density patterns required in
sub
-
micron devices,
electron beam (E
-
beam) lithography

is used
instead of optical litho
graphy.



In the following, the main processing steps involved in the
fabrication of an n
-
channel MOS transistor on a p
-
type substrate
will be examined.



Fabrication of the nMOS Transistor


The process starts with the oxidation of the silicon substrate (
Fig.
2.4(a)), in which a relatively thick silicon dioxide layer, also called
field oxide, is
created on the surface (Fig. 2.4(b)). Then, the field
oide is selectively etched to expose the silicon surface on which the
MOS transistor will be created (Fig. 2.
4(c)). Following this step, the
surface is covered with a thin, high
-
quality oxide layer, which will
eventually form the gate oxide of the MOS transistor (Fig. 2.4(d)).










Grow Field
Oxide

Etch

Field
Oxide

Grow Thin

Oxide

On top of the thin oxide layer, a layer of polysilicon (polycrystalline
s
ilicon) is deposited (Fig. 2.4(e)). Polysilicon is used both as gate
electrode material for MOS transistors and also as an interconnect
medium in silicon integrated
circuits
. Undoped polysillicon has
relatively high resistivity. The resistivity of polysili
con can be
reduced, however, by doping it with impurity atoms.


After deposition, the polysilicon layer is patterned and etched to
form the interconnects and the MOS transistor gates (Fig. 2.4(f)).
The thin gate oxide not covered by polysilicon is also etc
hed away,
which exposes the bare silicon surface on which the source and
drain junctions are to be formed (Fig. 2.4(g)).




The entire silicon surface is then doped with a high concentration of
impurities, either through diffusion or ion implantation
(in this case
with donor atoms to produce n
-
type doping). Figure 2.4(h) show
that the doping penetrates the exposed areas on the silicon surface,
Deposit
Poly

Undoped



Pattern
Poly



Etch thinox
not covered
by poly



ultimately crating two n
-
type regions (source and drain junctions) in
the p
-
type substrate. The impurity dopin
g also penetrates the
polysilicon on the surface,
reducing

its resistivity. Note that the
polysilicon gate, which is patterned before doping, actually defines
the precise location of the channel region and, hence, the location
of the source and the drain r
egions. Since this procedure allows
very precise positioning of the two regions relative to the gate, it is
also called the
self
-
aligned process
.




Once the source and drain regions are completed, the entire
surface is again covered with an insulating
layer of silicon dioxide
(Fig. 2.4(i)). The insulating oxide layer is then patterned in order to
provide contact windows for the drain and source junctions (Fig.
2.4(j)). The surfaces is covered with evaporated aluminum which
will form the interconnects (F
ig. 2.4(k)). Finally, the metal layer is
Self
-
aligned
process



Doped



patterned and etched, completing the interconnection of the MOS
transistors on the surface (Fig. 2.4(l)). Usually, a second (and third)
layer of metallic interconnect can also be added on top of this
structure by cr
eating another insulating oxide layer, cutting contact
(via) holes, depositing, and patterning the metal.







Device Isolation Techniques


The MOS transistors that comprise an integrated circuit must be
electrically isolated from each other during fab
rication. Isolation is
required to prevent unwanted conduction paths between the
devices, to avoid creation of inversion layer outside the channel
regions of transistors, and to reduce leakage currents. To achieve a
sufficient level of electrical isolation

between neighboring
transistors on a chip surface, the devices are typically created in
dedicated regions called,
active areas
, where each active area is
surrounded by a relatively thick oxide barrier called the
field oxide
.


On possible technique to crea
te isolated active areas on silicon
surface is first to grow a thick field oxide over the entire surface of
the chip, and then to selectively etch the oxide in certain regions, to
Metal layer
patterned &
etched



define the active areas. This fabrication technique, called etched
field
-
oxi
de isolation, is already illustrated in Fig. 2.4(b) and Fig.
2.4(c).



Local Oxidation of Silicon (LOCOS):

Selective grow
Field Oxide

on certain region.













Channel
-
Stop
Implant



Grow Field
Oxide



Etch Nitride &
Pad Oxide





Fabrication of the CMOS Transistor


The
simplified

process sequence for the fabricati
on of CMOS
integrated circuits on a p
-
type silicon substrate is shown in Fig. 2.1.
The process starts with the creation of the n
-
well regions for pMOS
transistors, by impurity implantation into the substrate. Then, a thick
oxide is grown in the regions sur
rounding the nMOS and pMOS
active regions. The thin gate oxide is subsequently grown on the
surface through thermal oxidation. These steps are followed by the
creation of n+ and p+ regions (source, drain, and channel
-
stop
implants) and by final metallizati
on (creation of metal
interconnects).







The process of creating an n
-
well inverter (or in general, any n
-
well
CMOS circuits) can divided into three stages. In the first stage,
n
-
well are formed and active regions are defined for the transistors.
The
transistors are created in the second stage. In the third stage,
the metal interconnections are formed.