Mixed-Signal ASIC Design for

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Slide
1

of 34

ESA AMICSA 2006



Mixed
-
Signal ASIC Design for
Space Communications

Presented by Dr. Rajan Bedi


Slide
2

of 34

ESA AMICSA 2006



Mixed
-
Signal ASIC Design for Space
Communications

UK EXPORT CONTROL SYSTEM EQUIPMENT & COMPONENTS RATING:
3A001a1a, 3A001a2, 3A001a5a1, 3A001a5a2, 3A001a5a3, 3A001a5a4,
3A001a5b, 3A101a, 3C001a, 3C001b, 4A002b2, 4A002b1 & 5E001c1.



UK EXPORT CONTROL TECHNOLOGY RATING: 3E001, 4E001 5E001b1 &
5E001c2e.



Rated By : Rajan Bedi with reference to UK Export Control Lists (version
INTR_A12. DOC 13 August 2003) which contains the following caveat:
“The control texts reproduced in this guide are for information purposes
only and have no force in law. Please note that where legal advice is
required, exporters should make their own arrangements”.



Export licence : Not required for EU countries. Community General Export

authorisation EU001 is valid for export to : Australia, Canada, Japan,

New Zealand, Norway, Switzerland & USA.



Slide
3

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ESA AMICSA 2006



Presentation Overview


Introduction & Motivation



Research into mobile payload ADCs



Research into broadband payload ADCs



Research into space
-
grade DACs



Mixed
-
Signal Processing



Conclusion

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4

of 34

ESA AMICSA 2006



Introduction


Increasing amounts of analog
ue

circuitry and digital logic

are

now being
integrated

on die and flown.



The availability of
:


Low
-
power, high
-
performing BiCMOS technologies
, f
T

(peak
cut
-
off frequency) ~ 300 GHz!


The inherent total
-
dose tolerance of the SiGe HBT
.


The addition of a SOI layer to SiGe BiCMOS.


The ability to individually size of NPNs and PNPs with trench
isolation.


I
ntegrated EDA tools and common design & verification flows.



All of these offer the potential to advance mixed
-
signal
microelectronics

for space applications.


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5

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ESA AMICSA 2006



Motivation


The benefits of integrating analog
ue

circuitry with digital
logic include:



Higher performance


Lower power consumption


Less mass


Reduced costs


Improved reliability


Greater levels of reusability


Enhanced system testing and quality



All of these
benefits
contribute to the spirit of “Faster,
Better, Cheaper”!


Slide
6

of 34

ESA AMICSA 2006



Motivation



Telecommunication satellites with on
-
board digital
processors require ADCs at the receiver to digitize
the IF/baseband carrier information.



Future mobile missions will be required to digitize
information bandwidths around 50 MHz


this will
necessitate baseband sampling at a rate greater
than 100 MSPS.




Future broadband missions will be required to
digitize information bandwidths around 500 MHz


this will necessitate baseband sampling at a rate
greater than 1 GSPS.





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7

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ESA AMICSA 2006



Motivation


This performance will only be delivered by advances in
mixed
-
signal processing.



Experience has shown that accessing the latest deep sub
-
micron technologies is difficult due to the low volumes
required by space companies.



When the major semiconductor vendors are willing to
develop hardware, the NRE costs are exorbitant.



Moreover, the suitability of the fabrication technology for
space flight first needs to be assessed, with vendors often
adopting a low
-
risk approach to radiation testing and
qualification.



As a satellite manufacturer, how do we support the
development of future digital payloads for our customers?


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8

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ESA AMICSA 2006



Motivation


This

variation

in

the

range

of

sampling

frequencies

greatly

impacts

the

micro
-
architecture,

the

circuit

design,

the

resolution

and

power

consumption

of

mixed
-
signal

converters

that

can

be

considered

for

use

on

satellite

payloads
.



This

range

of

payload

types,

limited

power

budget,

restricted

fabrication

options

and

operation

in

a

harsh

environment
,

all

combine

to

make

ADC/DAC

design

for

space

communications

extremely

challenging
.




This

objective

of

this

presentation

is

to

share

with

vendors

current

research

on

low
-
power,

high
-
performance,

space
-
grade

converters

for

use

with

future

mobile

and

broadband

payloads
.





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9

of 34

ESA AMICSA 2006



ADC Design


The

design

of

low
-
power

ADCs

capable

of

sampling

around

150

MSPS

differs

from

those

required

to

sample

above

1

GSPS
.




The

development

of

an

ADC

involves

a

number

of

trade
-
offs,

e
.
g
.

as

the

required

sampling

frequency

or

dynamic

range

increase,

so

does

the

complexity,

size,

weight,

cost

and

power

dissipation

of

device
s
.




As

a

general

rule,

effective

resolution

decreases

by

one

bit

for

every

doubling

of

the

sampling

frequency
.


Slide
10

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ESA AMICSA 2006



Low
-
Power Narrowband ADC




For low
-
power ADCs, a sampling frequency of
150 MSPS is achieved by implementing micro
-
architectures that combine elements of the
successive approximation and flash techniques
with pipeline
-
type signal processing.






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11

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ESA AMICSA 2006




Pipelined ADC Micro
-
Architecture


First stage of the pipeline performs a coarse quantisation on
the input while subsequent stages are concurrently
processing previously acquired input samples.



STAGE 0


STAGE 1


STAGE N
-
1


STAGE N


LATCH




LATCH




LATCH







+

+

+

+

+

+


ANALOGUE PIPELINE


DIGITAL PIPELINE

INPUT

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12

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ESA AMICSA 2006



Pipelined ADC Micro
-
Architecture

Each stage comprises a S&H, low
-
resolution
ADC and DAC and a subtractor.

--

DAC

ADC


SAMPLE & HOLD



A

+

VIN

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13

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ESA AMICSA 2006



Pipelined ADC Micro
-
Architecture


High
-
throughput, concurrent design.



For

pipelined

ADCs,

power

dissipation

can

be

minimised

through

the

appropriate

choice

of

per
-
stage

resolution

and

selection

of

suitable

op
-
amp

architectures
.



Thermal

noise,

comparator

offsets,

sample
-
and
-
hold

offsets,

gain

errors

and

non
-
uniform

levels

within

the

interstage

DACs

all

affect

the

performance

of

pipelined

ADCs
.




Simulations

and

circuit

design

are

continuing

that

investigate

trade
-
offs

between

thermal

noise,

speed,

linearity

and

power

dissipation
.







Slide
14

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ESA AMICSA 2006



Pipelined ADC Micro
-
Architecture


For low power operation, CMOS converters are
preferred as
digital
consumption scales with
sampling frequency.



Bi
polar

converters developed to operate at a
particular frequency but used at lower rate, will
incur a fixed penalty and dissipate the same power
as clocking at the higher frequency due to
constant current structures.



Slide
15

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ESA AMICSA 2006



Pipelined ADC Micro
-
Architecture


The digital capability of CMOS easily allows the
inclusion of error correction, calibration and other
computational features to improve overall
converter performance and accuracy.



Fabrication using deep submicron CMOS results
in higher performance due to reductions in
parasitics.



However, concomitant with the migration to
smaller feature sizes, lower supply voltages make
it more difficult to maintain input SNR



Continual
technology scaling impacts ADCs!

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16

of 34

ESA AMICSA 2006



Low Power Broadband ADC




For low
-
power
broadband
ADCs, sampling
frequencies above 1 GSPS are achieved by
implementing interleaving micro
-
architectures or
variations of Flash techniques:




Folded Flash


Folded & Interpolative Flash


Pipelined, Folded & Interpolative Flash



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ESA AMICSA 2006



Folded Flash ADC





INPUT

COARSE

ADC


FOLDING

CIRCUIT

FINE

ADC


DIGITAL ADDER &

CORRECTION CIRCUIT

DIGITAL OUTPUT WORD

Folding is a technique that reduces hardware while maintaining
the one
-
step nature of a full Flash ADC.

An analogue pre
-
processing circuit generates a residue which
is digitised to obtain the LSBs.

The MSBs are resolved using a coarse ADC that operates in
parallel with the folding circuit.

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ESA AMICSA 2006



Folded Interpolative Flash ADC



Interpolation reduces the number of comparator
preamplifiers at the input of a Flash converter.



Interpolation substantially reduces the input
capacitance, power dissipation and area of flash
converters, while preserving the one
-
step nature of
a Flash architecture.



Simulations

show

that

offset,

gain

and

timing

mismatches

result

in

SNR

degradation

at

high

input

frequencies
.




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19

of 34

ESA AMICSA 2006



DAC Design


We have started investigating current
-
steering
DAC micro
-
architectures with the goal of achieving
low power with high speed and low distortion.



Traditionally current
-
steering DACs were
fabricated using bipolar technology, however, the
ability to generate matched CMOS current mirrors
will result in lower power consumption.



A segmented architecture provides a good
balance between performance vs. area and
complexity.


Slide
20

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ESA AMICSA 2006



VLSI


To achieve the required performance and low power,
silicon
-
based technologies are being targeted for
fabrication.



CMOS converters are preferred as digital power
dissipation scales with sampling frequency.



SOI CMOS typically offers 30 to 50% higher
performance for the same power compared to bulk
CMOS (30% less power at the speed).



SOI offers reduced cross
-
talk for mixed
-
signal design,
immunity to latch
-
up, better tolerance of SEEs and the
absence of radiation
-
induced leakage between devices.

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21

of 34

ESA AMICSA 2006



VLSI


BiCMOS processes combine faster, higher
-
current
driving bipolar transistors with smaller, lower
-
power,
high impedance CMOS devices.



This makes BiCMOS attractive for mixed
-
signal design.



The bipolar transistor can be either Si or SiGe.



For the same operating current, a SiGe HJT has higher
speed, increased gain, lower RF noise and less 1/f
noise compared to a Si BJT


ft ~ 300 GHz.



SiGe BiCMOS allows the integration of analog, digital
and RF using existing CMOS foundries.



Currently investigating SOI and BiCMOS to minimise
noise coupling through the wafer substrate.

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22

of 34

ESA AMICSA 2006



Space Microelectronics


Heavy
-
ion strikes can trigger latchup in CMOS and
bipolar devices with the potential to damage a circuit
permanently.



In ADC/DACs, a transient generated in the analogue
part of a device can propagate into
the digital section
causing logic level shifts.



The migration to smaller geometries has helped CMOS
transistors to become inherently more resistant to
TID
radiation as thinner gate oxide layers trap less positive
charge.



R
adiation

hardening

by

design

techniques

are

being

used

to

mitigate

the

damage,

functional

upsets

and

data

loss

caused

by

radiation
.


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ESA AMICSA 2006



Radiation Hardening By Design


The

use

of

enclosed

layout

NMOS

transistors
.



The

design

of

p
ortions

of

a

circuit

using

PMOS

FETs

only
.

As

PMOS

transistors

are

not

prone

to

edge

leakage,

there

is

no

need

for

annular

layout
.




Such

structures

are

immune

to

latchup

due

to

the

absence

of

stray

silicon
-
controlled

rectifier

structures
.




Latchup

can

be

avoided

by

completely

enclosing

NMOS

and

PMOS

FETS

using

guard

rings

or

through

the

addition

of

an

epi

layer
.



Design
-
hardened

versions

of

integrated

circuits

typically

require

more

die

space

than

their

soft

counterparts!


Slide
24

of 34

ESA AMICSA 2006



Analogue Section of 12
-
bit Segmented

DAC Incorporating RHBD

63 Unary Current Sources

6 Binary Current Sources

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ESA AMICSA 2006



Radiation Hardening By Design



All NMOS transistors drawn as Enclosed Layout
Transistors (Annular)


this makes them immune
to edge leakage effects.



Guard rings isolate all n+ diffusions at different
potentials.



Current sources are all PMOS.



Solely PMOS structures are immune to latch
-
up.


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26

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ESA AMICSA 2006



PMOS Current Source


(LSB Binary)

W = 1.1 μm

L = 0.8 μm

M = 1

bias_P2

bias_P1

out

VDD

W = 1.1 μm

L = 0.8 μm

M = 1

ILSB

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27

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ESA AMICSA 2006



PMOS Current Source


(Unary)

W = 1.1 μm

L = 0.8 μm

M = 64

bias_P2

bias_P1

out

VDD

W = 1.1 μm

L = 0.8 μm

M = 64

64 * ILSB

Slide
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of 34

ESA AMICSA 2006



Mixed
Signal Processing



A

number

of

signal

processing

techniques

exist

that

potentially

could

ease

the

hardware

implementation

of

the

data

converters
:



Complex

Baseband

Sampling



RF/IF

Bandpass

Sampling





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29

of 34

ESA AMICSA 2006



Complex Baseband Sampling

Analogue Generation of I/Q Samples

i[n]


jq[n]

x(t)

x(t)

A/D

A/D

i[n]

q[n]


xi(t)


i(t)


q(t)


xq(t)

-
90
°

sin ωct

Analogue


Digital

Complex baseband sampling at a rate greater than the highest
frequency component


allows access to lower sampling
frequencies



lower power if using CMOS ADCs
.

Difficult to match frequency response of both paths

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30

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ESA AMICSA 2006



Complex Baseband Sampling

Digital Generation of I/Q Samples

x(t)

Analogue


Digital

A/D


i[n]


i’[n]


q’[n]


q[n]

sin ωct

cos ωct

Complex baseband sampling at a rate four times the
highest frequency component.

Single ADC, no matching issues, simple mixing


Slide
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ESA AMICSA 2006



RF Bandpass Sampling of L
-
band User Uplink

Zone 1 2 3 4 23 24

Fs/2

70.25

Fs

140.5

1.5 Fs

210.7

2 Fs

281

Frequency (MHz)


12 Fs

1686

11.5 Fs

1615.7

Band
-
pass AAF

Amp.


Bandpass sampling achieves digitisation and
downconversion in a single operation, without the use of
analogue mixers, local oscillators and image
-
reject filters.

Intentionally alias the RF information to baseband/IF.


The availability of wideband ADCs, e.g. bandwidths
approaching 3 GHz, makes direct sampling of L/S
-
band RF
carriers a real possibility.

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of 34

ESA AMICSA 2006



RF Bandpass Sampling


To

realise

bandpass

sampling,

the

ADC

must

have

the

necessary

analogue

input

bandwidth

to

process

the

highest

frequency

component

within

the

input

signal
.




Low

distortion

and

good

linearity

at

this

frequency

are

essential
.




ADCs

intended

for

undersampling

applications

are

more

sensitive

to

the

amount

of

noise

at

the

input

than

a

traditional

converter
.




Board

layout,

decoupling

considerations

and

minimising

jitter

on

the

sampling

clock

are

critical
.



Slide
33

of 34

ESA AMICSA 2006



Conclusions


I

have

shared

with

you

current

investigations

t
hat

research

the

develop
ment

of

low
-
power,

high
-
performance,

space
-
grade

converters

for

use

with

future

mobile

and

broadband

payloads
.



Satellite

manufactures

have

intimate

knowledge

of

payloads
.



Different

types

of

telecommunication

satellites

have

unique

mixed
-
signal

requirements,

e
.
g
.

sampling

frequency,

resolution,

dynamic

performance

and

power

consumption
.




Pipelined

ADCs

should

be

targeted

for

future

mobile

payloads

and

folding,

interpolative

flash

architectures

for

broadband

processors
.




Segmented,

current
-
steering

DACs

should

be

targeted

for

future

satellites
.




Slide
34

of 34

ESA AMICSA 2006



Conclusions


A

re
-
usable

design

and

verification

flow

and

design

trade
-
offs

at

the

systems
-
level,

the

micro
-
architectural

level,

the

circuit

level

and

at

a

technology

level

combine

to

enable

mission
-
specific,

mixed
-
signal

IP
.