The STAR Heavy Flavor Tracker

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1

The STAR Heavy Flavor Tracker


Conceptual Design Report






Version:

9

Date:


March

17
,

2009



2

Table of Content


1.

INTRODUCTION
................................
................................
................................
...............................
10

2.

FUNCTIONAL REQUIREME
NTS
................................
................................
................................
...
11

2.1.

G
ENERAL
D
ESIGN
C
ONSIDERATIONS
................................
................................
..............................
11

2.2.

P
OINTING
R
ESOLUTION
................................
................................
................................
...................
11

2.3.

M
ULTIPLE
S
CATTERING IN THE
I
NNER
L
AYERS
................................
................................
..............
12

2.4.

I
NTERNAL
A
LIGNMENT AND
S
TABILITY
................................
................................
..........................
13

2.5.

P
IXEL
I
NTEGRATION
T
IME
................................
................................
................................
..............
13

2.6.

R
EAD
-
OUT
S
PEED AND
D
EAD
T
IME
................................
................................
................................
14

2.7.

D
ETECTOR
H
IT
E
FFICIENCY
................................
................................
................................
............
14

2.8.

L
IFE
C
HANNELS
................................
................................
................................
..............................
14

3.

TECHNICAL DESIGN
................................
................................
................................
.......................
15

3.1.

O
VERVIEW
................................
................................
................................
................................
......
15

3.2.

P
IXEL
................................
................................
................................
................................
..............
16

3.2.1.

Introduction
................................
................................
................................
............................
16

3.2.2.

Detector Parameters
................................
................................
................................
..............
16

3.2.3.

Sensors and Readout
................................
................................
................................
..............
17

3.2.4.

Sensors and Readout Simulation and Prototyping
................................
................................
.
30

3.2.5.

Mechanical Design
................................
................................
................................
.................
3
2

3.2.6.

Mechanical Design Simulation and Prototyping
................................
................................
...
42

3.3.

T
HE
I
NTERMEDIATE
STAR

T
RACKER
................................
................................
.............................
43

3.3.1.

Introduction
................................
................................
................................
............................
43

3.3.2.

Requirements
................................
................................
................................
..........................
43

3.3.3.

Design choices
................................
................................
................................
........................
45

3
.3.4.

Readout system and Slow Controls
................................
................................
........................
55

3.3.5.

Spatial survey and alignment
................................
................................
................................
.
57

3.4.

T
HE
S
ILICON
S
TRIP
D
ETECTOR
................................
................................
................................
.......
59

3.4.1.

How the SSD Affects the Performance of the TPC
................................
................................
.
61

3.4.2.

Existing SSD Hardware

Before the Upgrade
................................
................................
......
65

3.4.3.

SSD Ladder Status
................................
................................
................................
..................
69

3.4.4.

Plans for repair
................................
................................
................................
......................
71

3.4.5.

Upgrade of the Electr
onics
................................
................................
................................
....
72

3.4.6.

Cooling System

Requirements, Status and Upgrade
................................
...........................
76

3.4.7.

Alignment Mounts on the Cone
................................
................................
..............................
81

3.4.8.

Cable paths
................................
................................
................................
.............................
83

3.4.9.

Cab
le Paths on the Cone
................................
................................
................................
........
85

3.4.10.

Rack space
................................
................................
................................
............................
85

3.4.11.

Staging Plan
................................
................................
................................
.........................
86

3.4.12.

Resources
................................
................................
................................
.............................
86

3.4.13.

Cost Summary
................................
................................
................................
......................
88

3.4.14.

Management Structure
................................
................................
................................
.........
90

3.5.

I
NTEGRATION INTO
STAR
................................
................................
................................
..............
91

3.5.1.

Cone and Support Structure
................................
................................
................................
...
91

3.5.2.

Beam Pipe
................................
................................
................................
..............................
91

3.5.3.

Services
................................
................................
................................
................................
...
91

3.5.4.

Controls
................................
................................
................................
................................
..
91

3.5.5.

Data Acquisition
................................
................................
................................
.....................
91

3.5.6.

SSD
................................
................................
................................
................................
.........
92

3.6.

S
OFTWARE
................................
................................
................................
................................
......
92

3.6.1.

STAR’s Software Environme
nt
................................
................................
...............................
92

3.6.2.

Online Software
................................
................................
................................
......................
93



3

3.6.3.

Offline Software
................................
................................
................................
......................
93

3.6.4.

Simulation Framework
................................
................................
................................
...........
96

3.6.5.

Physics Analysis Framework
................................
................................
...............................
100

3.6.6.

Institutional Responsibilities
................................
................................
................................
101

3.7.

C
OST AND
S
CHEDULE
................................
................................
................................
...................
102

4.

RESOURCES
................................
................................
................................
................................
.....
103

5.

APPENDIX 1
................................
................................
................................
................................
......
104

5.1.

D
ESCRIPTION O
F THE
P
IXEL
RDO

S
YSTEM
................................
................................
...................
104

5.1.1.

Phase
-
1 Readout Chain
................................
................................
................................
........
104

6.

APPENDIX 2
................................
................................
................................
................................
......
113

6.1.

M
ECHANICAL
D
ESIGN
S
IMULATION AND
A
NALYSIS
................................
................................
....
113

6.1.1.

Ladd
er support Structural analysis
................................
................................
......................
113

6.1.2.

Ladder Cooling Analysis
................................
................................
................................
......
120

7.

APPENDIX 3
................................
................................
................................
................................
......
125

REFERENCES
................................
................................
................................
................................
..........
130




4

List of Figures


F
IGURE
1:

C
OMPARISON OF THREE D
IFFERENT TYPES OF SI
MULATIONS TO DETERMI
NE THE POINTING
RESOLUTION IN R
ϕ
AND IN THE Z
-
DIRECTION AT THE VER
TEX
.

T
HE THREE METHODS ARE
THE
T
OY
M
ODEL
,
A
T
OY
S
IMULATION
,
AND THE FULL
STAR

S
IMULATION
.

E
ACH METHOD HAS DIFFE
REN
T
ASSUMPTIONS AND SLIG
HTLY DIFFERENT PARAM
ETERS BUT OVERALL
,
THE AGREEMENT IS GO
OD
.

I
N
THE FIGURE

S LEGEND
,

BP
IS SHORT HAND FOR

BEAM PIPE
”.
................................
..............................
12

F
IGURE
2:

A
SCHEMATIC VIEW OF T
HE
S
I DETECTORS THAT SUR
ROUND THE BEAM PIPE
.

T
HE

SSD
IS AN
EXISTING DETECTOR AN
D IT IS THE OUTMOST
DETECTOR SHOWN IN TH
E DIAGRAM
.

T
HE
IST
LIES INSIDE
THE
SSD
AND THE
PIXEL
LIES CLOSEST TO THE
BEAM PIPE
.

T
HE BEAM PIPE AND ITS
EXO
-
SKELETON
ARE ALSO SHOWN
.
................................
................................
................................
................................
.
15

F
IGURE
3:

D
IAGR
AM SHOWING THE SENSO
R DEVELOPMENT PATH O
F SENSORS FOR THE
STAR

P
IXEL
DETECTOR AT
IPHC
IN
S
TRASBOURG
,

F
RANCE
.

T
HE READOUT DATA PROC
ESSING REQUIRED IS S
HOWN
AS A FUNCTION OF SEN
SOR GENERATION
.

T
HE FIRST GENERATION
M
IMOSTAR SENSORS ARE
READ OUT
VIA A ROLLING
SHUTTER TYPE ANALOG
OUTPUT
.

T
HE NEXT GENERATION
P
HASE
-
1
SENSOR INTEGRATES
CDS
AND A COLUMN LEVEL
DISCRIMINATOR TO GIV
E A ROLLING SHUTTER
BINARY READOUT WITH
A
640

µ
S INTEGRATION TIME
.

T
HE FINAL GENERATION
U
LTIMATE SENSOR INTEG
RATES DATA
SPARSIFICATION AND
LOWERS THE READOUT T
IME TO
<

200

µ
S
.
................................
..........................
18

F
IGURE
4:

F
UNCTIONAL BLOCK SCHE
MATIC FOR THE READOU
T FOR THE
P
HASE
-
1
PROTOTYPE SYSTEM
.

T
HE
DETECTOR LADDERS AND
ACCOMPANYING READOU
T SYSTEM HAVE A HIGH
LY PARALLEL
ARCHITECTURE
.

O
NE SYSTE
M UNIT OF SENSOR ARR
AY
/
READOUT CHAIN IS SH
OWN
.

T
HERE ARE TEN
PARALLEL SENSOR ARRA
Y
/
READOUT CHAIN UNITS
IN THE FULL SYSTEM
.
................................
...........
20

F
IGURE
5:

P
HYSICAL LAYOUT OF TH
E READOUT SYSTEM BLO
CKS
.

T
HIS LAYOUT WILL BE T
HE SAME FOR BOTH
TH
E
P
HASE
-
1
BASED PATCH AND THE
FINAL
P
IXEL DETECTOR SYSTEM
.
................................
...............
21

F
IGURE
6:

A
SSEMBLY OF SENSORS O
N A LOW RADIATION LE
NGTH KAPTON FLEX CAB
LE WITH ALUMINUM
CONDUCTORS
.

T
HE SENSORS ARE CONNE
CTED TO THE CABLE WI
TH BOND WIRES ALONG
ON
E EDGE OF
THE LADDER
.
................................
................................
................................
................................
.........
22

F
IGURE
7:

P
OWER AND MASS
-
TERMINATION BOARD BL
OCK DIAGRAM
.

T
HE DIGITAL SIGNALS T
O AND FROM
THE SENSORS ARE ROUT
ED THROUGH THE MAIN
BOARD AND CARRIED TO
MASS TERMINATION
CONNECTORS FOR ROUTI
NG TO THE RE
ADOUT BOARDS
.

L
ATCH
-
UP PROTECTED POWER R
EGULATION IS
PROVIDED TO EACH LAD
DER BY A POWER DAUGH
TER CARD MOUNTED TO
THE MAIN BOARD
.

T
HE MAIN
POWER SUPPLIES ARE L
OCATED IN THE
STAR
RACKS
.
................................
................................
..........
23

F
IGURE
8:

R
EADOUT BOARD
(
S
).

T
HE READ
OUT SYSTEM CONSISTS
OF TWO BOARDS PER CA
RRIER OF
40

SENSORS
.

A
COMMERCIAL
X
ILINX
V
IRTEX
-
5
DEVELOPMENT BOARD I
S MATED TO A CUSTOM
MOTHERBOARD THAT PRO
VIDES ALL OF THE
I/O
FUNCTIONS INCLUDING
RECEIVING AND BUFFE
RING
THE SENSOR DATA OUTP
UTS
,
RECEIVING THE TR
IGGER FROM
STAR
AND SENDING THE BUI
LT EVENTS
TO A
STAR

DAQ
RECEIVER
PC
VIA FIBER OPTIC CON
NECTION
.
................................
...........................
24

F
IGURE
9:

F
UNCTIONAL BLOCK DIAG
RAM OF THE DATA FLOW
ON THE
RDO
BOARDS
.
................................
.
24

F
IGURE
10:

E
FFICIENC
Y AND FAKE HIT RATE
FOR A SIMPLE THRESHO
LD CUT ON PIXEL SIGN
AL LEVEL
.

T
HIS
FIGURE IS OBTAINED F
ROM BEAM DATA TAKEN
WITH
M
IMOSTAR
-
2
SENSORS
.
................................
.....
25

F
IGURE
11:

S
YSTEM LEVEL FUNCTION
ALITY DIAGRAM OF THE
READOUT OF THE
P
IXEL SENSORS
.


O
NE OF
THE TEN PARALLEL REA
DOUT CHAINS IS SHOWN
.
................................
................................
.................
26

F
IGURE
12:

D
ATA RATE REDUCTION I
N THE
P
HASE
-
1
READOUT SYSTEM
.
................................
.....................
28

F
IGURE
13:

F
UNCTIONAL BLOCK DIAG
RAM OF THE
RDO
BOARDS FOR THE READ
OUT OF THE
U
LTIMATE
DETECTOR BASED
P
IXEL DETECTOR
.
................................
................................
................................
.....
29

F
IGURE
14:

T
HREE
M
IMOSTAR
-
2
SENSORS IN A TELESC
OPE CONFIGURATION US
ED IN A BEAM
,
TEST AT
STAR.
................................
................................
................................
................................
..................
31

F
IGURE
15:

200

MH
Z
D
ATA EYE PATTERN MEAS
URED AT THE
RDO

MOTHERBOARD INPUT TO
THE
FPGA

(
AFTER ALL BUFFERS
)
AND TRIGGERED ON TH
E OUTPUT DATA FROM T
HE
FPGA.

F
ULL WIDTH OPENING
IN SYSTEM IS
~

2.3
NS
.
................................
................................
................................
...........................
32

F
IGURE
16:

P
IXEL DETECTOR MECHAN
ICS SHOWING DETECTOR
BARREL
,
SUPPORT STRUCTURES
AND

INSERTION PARTS PLUS
INTERFACE ELECTRONI
CS BOARDS
.
................................
................................
..
33



5

F
IGURE
17:

E
XPLODED VIEW OF THE
LADDER SHOWING COMPO
NENTS
.

T
HE SILICON IS COMPOS
ED OF
10

~
SQUARE CHIPS
,
BIT IT IS SHOWN HEA
R AS CONTINUOUS PIEC
E OF SILICON AS IT H
AS BEEN
MODELED
FOR ANALYSIS
.
................................
................................
................................
................................
......
34

F
IGURE
18:

T
HIN WALL CARBON SUPP
ORT BEAM
(
GREEN
)
CARRYING A SINGLE I
NNER BARREL LADDER A
ND
THREE OUTER BARREL L
ADDERS
.

T
HE BEAM IN ADDITION
TO SUPPORTING THE LA
DDERS PROVIDES A
DUCT FOR CONDUCTING
CO
OLING AIR AND ADDED
SURFACE AREA TO IMPR
OVE HEAT TRANSFER TO
THE
COOLING AIR
.
................................
................................
................................
................................
........
35

F
IGURE
19:

H
ALF MODULE CONSISTIN
G OF
5
SECTOR BEAM MODULES
.

T
HE SECTOR BEAM MODUL
ES ARE
SECURED TO A CARBON
COMPOSITE
D
TUBE USING A DOVE T
AIL S
TRUCTURE WHICH PERMI
TS EASY
REPLACEMENT OF SECTO
R MODULES
.

C
ARBON COMPOSITE PART
S ARE SHOWN IN GREEN
FOR GREATER
VISIBILITY
.
................................
................................
................................
................................
............
35

F
IGURE
20:

D
ETECTOR ASSEMBLY IN
THE INSTALLED POSITI
ON SUPPORTED WITH TH
REE KINEMATIC
MOUNTS
.
................................
................................
................................
................................
...............
36

F
IGURE
21:

D
ETAILED VIEW OF THE
KINEMATIC DOCKING MO
UNTS FOR THE PIXEL D
ETECTOR
.

T
HE MOUNTS
PROVIDE A FULLY CONS
TRAINED SUPPORT AND
OPERATE WITH A SPRIN
G LOADED OVER CENTER
LOCK
DOWN
.
................................
................................
................................
................................
...................
37

F
IGURE
22
:

T
RACK AND CAM GUIDE S
YSTEM FOR INSERTING
THE DETECTOR
.
................................
..............
38

F
IGURE
23:

I
NITIALLY THE DETECTO
R HALVES HAVE TO BE
SUFFICIENTLY OPEN TO
CLEAR THE LARGE
DIAMETER PORTION OF
THE BEAM PIPE
.

I
T THEN CLOSES DOWN S
UFFICIENTLY TO FIT
INSIDE THE
IFC

WHILE CLEARING THE B
EAM PIPE SUPPORTS AN
D THEN FINALLY IT CL
OSES DOWN TO THE FIN
AL
POSITION WITH COMPLE
TE OVERLAPPING COVER
AGE OF THE BARRELS
.
................................
...............
38

F
IGURE
24:

P
IXEL DETECTOR COOLIN
G AIR PATH
.

T
HE AIR FLOWS DOWN
THE CENTER OF THE SE
CTOR
MODULES AND RETURNS
BACK OVER THE DETECT
OR LADDERS ON THE SE
CTOR MODULES AND INT
O THE
LARGER
ISC
VOLUME WHERE IT IS
DUCTED BACK TO THE A
IR COOLING UNIT
.
................................
.....
39

F
IGURE
25:

S
CHEMATIC OUTLINE OF
AIR COOLING S
YSTEM FOR THE PIXEL
DETECTOR
.
................................
40

F
IGURE
26:

C
ABLE BUNDLE ENVELOPE
FOR LADDER CONNECTI
ONS
.

T
HE BLUE PAIRS INCLUD
E
40
SIGNAL
PAIRS
,
CLOCK AND TRIGGER L
INES AND
JTAG
COMMUNICATION
.

T
HE RED CONDUCTORS AR
E POWER
.
................................
................................
................................
................................
..............................
41

F
IGURE
27:

S
INGLE TRACK EFFICIEN
CY AS FUNCTION OF TH
E
IST
BARREL RADIUS
.

T
HE ASSUMED INTERNAL
SENSOR GEOMETRY WAS
600

µ
M IN R
-
ϕ
AND
6000

µ
M IN Z
.
................................
................................
.
45

F
IGURE
28:

IST
BARREL LAYOUT WITH
24
LADDERS OF
62
CM LONG
AT A RADIUS OF
14
CM
.
......................
46

F
IGURE
29:

S
INGLE TRACK FINDING
EFFICIENCY FOR DIFFE
RENT R
-
PHI AND Z PAD SIZES
OF THE
IST.

T
HE
SOLID LINES SHOW THE
ISO
-
LINES FOR CERTAIN AM
OUNT OF CHANNELS
(1

=

128
CH
,

2

=

256
CH
,

3

=

384
CH
,

4

=

512
CH
,

5

=

640
CH
).

T
HE LEFT PICTURE SHOW
S THE EFFICIENCY WHE
N NO HITS FROM THE
SSD
ARE INCLUDED
,
IN THE RIGHT PICTUR
E THE
SSD
HITS ARE INCLUDED I
N THE TRACK
.

P
ARTICLES
TRACKED ARE KAONS AT

750

M
E
V/
C
.
................................
................................
................................
..
47

F
IGURE
30:

IST
SILICON PAD S
ENSOR INTERNAL LAYOU
T
.
................................
................................
............
48

F
IGURE
31:

C
LOSE
-
UP OF THE
APV25
-
S1
CHIP OF WHICH THE
IST
WILL USE ABOUT
1200.
..........................
50

F
IGURE
32:

IST
HYBRID
(
LEFT
)
AND CABLE
(
RIGHT
)
ASSEMBLY
.
................................
................................
..
51

F
IGURE
33:

L
AYOUT OF AN
IST
MODULE
.
................................
................................
................................
......
51

F
IGURE
34:

D
RAWINGS OF THE
IST
LADDER
.

T
OP PICTURE IS WITH M
ODULES ATTACHED
,
MIDDLE PICTURE
SHOWS THE BARE LADDE
R AND BOTTOM PICTURE
SHOWS A CROSS SECTI
ON OF THE LADDER
.
.............
52

F
IGURE
35:

C
ROSS SECTION OF THE
LADDER AND MODULES
.

E
SPECIALLY NOTE THE K
APTON HYBRID WHICH
GETS FOLDED OVER TO
THE OTHER SIDE
.
................................
................................
..............................
53

F
IGURE
36:

L
ADDER
'
CLIP
'
MOUNTING OF THE
IST
LADDERS ONTO THE SU
PPORTING CYL
INDER
(ISC).
........
54

F
IGURE
37:

P
HI AVERAGED MATERIAL
BUDGET FOR THE
IST
AS A FUNCTION OF RA
PIDITY
.
.........................
54

F
IGURE
38:

IST

DAQ
BLOCK DIAGRAM
.
................................
................................
................................
........
56

F
IGURE
39:

IST
SLOW CONTROLS FL
OW DIAGRAM
.
................................
................................
.......................
57

F
IGURE
40:

T
HE PHOTO SHOWS THE R
OLLOUT OF THE
S
ILICON
S
TRIP
D
ETECTOR FOR ROUTINE
MAINTENANCE
.
................................
................................
................................
................................
.....
59

F
IGURE
41:

T
HE
SSD
IS SHOWN SURROUNDIN
G THE INNER SILICON
TRACKING LAYERS OF T
HE
HFT
.
..........
60

F
IGURE
42:

T
HE
DCA
RESOLUTION OF THE
TPC
AND THE
SSD
VERSUS THE INVERSE
MOMENTUM OF THE
TRACK
.

T
HE TOP LINE SHOWS TH
E
DCA
RESOLUTION OF THE
TPC,
ACTING ALONE
,
FOR ALL TRACKS
ENTERING THE
TPC

(
I
.
E
.
NO TRACK CUTS
)
DURING T
HE HIGH INTENSITY
C
U
-
C
U RUN AT
RHIC.

T
HE
RED LINE DEMONSTRATE
S HOW THE POINTING R
ESOLUTION OF THE
TPC
CAN BE IMPROVED BY
INCLUDING THE
SSD
HITS ON TRACKS
.

T
HE RESULTS ARE QUOTE
D FOR
200

G
E
V
MIN
B
IAS
C
U
-
C
U


6

COLLISIONS WITH
|Z
VERTEX
<

5
CM
|
AND
|
η
|

<

1.

T
HE
REMAINING LINES ON
EH PLOT SHOW THE
PERFORMANCE OF THE O
LD
STAR

S
ILICON
V
ERTEX
T
RACKER AND ARE NOT R
ELEVANT HERE
.
..........
61

F
IGURE
43:

K
0
SPECTRA FOR THE HIG
H INTENSITY
C
U
-
C
U RUN AT
200

G
E
V.

T
HE LEFT PANEL SHOWS
THE
RECONSTRUCTED
K
0
S USING THE
TPC
ALONE
.

T
HE RIGHT HAND PANEL
THE IMPROVEMENT IN T
HE
SIGNAL TO NOISE RATI
O WHEN THE
SSD
HITS ARE INCLUDED I
N THE TRACK FITTING
ALGORITHM
.
.....
62

F
IGURE
44:

D
ATA COMPARED TO SIMU
LATED MOMENTUM RESOL
UTION OF THE
TPC

AND
SSD
DETECTORS IN
STAR.

T
HE DATA POINTS SHOW
A SUPERPOSITION OF M
EASURED PION AND ANT
IPROTON SPECTRA AT
A MAGNETIC FIELD OF
0.25

T.

T
HE BLUE LINE
(
TOP
)
IS THE SIMULATED
0.25

T
P
T
SPECTRUM FOR ANTI
PROTONS
,
WHILE THE RED
(
MIDDLE
)
AND PINK
(
BOTTOM
)
LINE
S SHOW THE SIMULATED
MOMENTUM
RESOLUTION FOR THE
TPC
AND
TPC+SSD
AT
0.5

T,
RESPECTIVELY
.
................................
..................
62

F
IGURE
45:

S
IMULATED HIGH P
T

Λ
SPECTRA USING THE
TPC
ALONE
(
LEFT PANEL
)
OR THE
TPC+SSD

(
RIGHT
PANEL
)
AT
0.5

T
ESLA
.

T
HE STATISTICS BOX
ES IN EACH PANEL DOC
UMENT THE IMPROVED W
IDTH OF
THE PEAK WHEN THE
SSD
IS INCLUDED IN THE
TRACKING ALGORITHM
.
................................
..............
63

F
IGURE
46:

T
HE SIMULATED POINTIN
G RESOLUTION OF THE
HFT
DETECTOR SYSTEM
(
σ
);
WHERE THE R
-
φ

AND Z POINTING RESOL
UTI
ONS ARE PLOTTED SEPA
RATELY
(
TOP AND BOTTOM
,
RESPECTIVELY
).

T
HE
CALCULATIONS ASSUME
A KAON PASSING THROU
GH THE SYSTEM
.

T
HE RED LINE SHOWS TH
E POINTING
RESOLUTION OF THE
TPC
ONTO THE VERTEX
.

T
HE BLACK LINE SHOWS
THE POINTING RESOLUT
ION OF
THE
TPC
ONTO THE

SSD.

T
HE
TPC+SSD
POINTING AT THE
IST
IS THE GREEN LINE
.

T
HE
TPC+SSD+IST
POINTING AT
PXL2
IS MAGENTA
,

TPC+SSD+IST+PXL2
POINTING AT
PXL1
IS CYAN
,

AND THE FULL SYSTEM
POINTING AT THE VERT
EX IS BLUE
.

T
HE BLUE DASHED LINE
IS THE
THEORETICAL LIMIT
;
IT SHOWS
THE IDEALIZED
HFT
PERFORMANCE WITHOUT
BEAM PIPE OR OTHER
SOURCES OF
MCS
EXCEPT IN THE
PXL
LAYERS
.
................................
................................
..................
64

F
IGURE
47:

T
HE END
-
RINGS FOR THE
SSD
BARREL ARE SHOWN
.

T
HE RINGS SPLIT INTO
4
SECTORS
;
THE TOP
AND BOTTOM SECTORS S
UPPORT
3

LADDERS EACH
,
WHILE THE SECTORS O
N EACH SIDE SUPPORT
7

LADDERS EACH
.

T
HE COMPLETE DETECTOR
HAS
20
LADDERS
.

I
N THIS FIGURE
,
THREE LADDERS ARE
MOUNTED ON THE BARRE
L AT RANDOM LOCATION
S
.
................................
................................
............
66

F
IGURE
48:

A

SSD
LADDER SHOWING ITS
V
ARIOUS COMPONENTS
.
................................
...............................
67

F
IGURE
49:

E
XPLODED VIEW OF ONE
DETECTOR MODULE
.

I
T TAKES
16
MODULES TO FILL A L
ADDER
.
........
68

F
IGURE
50:

M
ODULE LAYOUT OF THE
EXISTING ELECTRONICS

(
BEFORE UPGRADE
).
................................
.....
68

F
IGURE
51:

L
EFT
:
PHOTOGRAPH OF THE H
YBRID
.

R
IGHT
:
INFRARED IMAGE OF T
HE SAME HYBRID
.

A
N
ARROW POINTS TO THE
CAPACITOR ON THE LEF
T AND ANOTHER SHOWS
THE HOT SPOT ON THE
RIGHT
.

A
S THE HOT SPOT IS AT
THE SAME POSITION O
F THE CAPACITOR
,
WE CONCLUDE THAT TH
E CAPACITOR
IS OPERATING AT A HI
GH CURRENT
(
SEVERAL
100

µA)
AND IS THEREFORE LE
AKING
.
..........................
70

F
IGURE
52:

A
PLOT OF THE PERCENT
ACTIVE AREA OF THE
SSD
AT THE PRESENT AND
WITH THE PROPOSED
REMOVAL OF THE LEAKI
NG C
APACITORS
.

T
HE CURVES ARE EXPLAI
NED IN THE TEXT
.
........................
71

F
IGURE
53:

T
HIS
SOLDERING HEAD WILL
BE USED TO REMOVE TH
E LEAKING CAPACITORS
ON SOME LADDERS
.
................................
................................
................................
................................
..............................
71

F
IGURE
54:

A
SCHEMATIC OF THE IN
TERCONNECTION
BETWEEN THE LADDER E
LECTRONICS AND THE
RDO

CARD
,

E
ACH
RDO
HANDLES
5
LADDERS
.

T
HE CONNECTION BETWEE
N THE LADDER ELECTRO
NICS AND
THE CORRESPONDING
RDO
CARD IS A DUAL OPTI
CAL FIBER
.
................................
...............................
74

F
IGURE
55:

T
HE RED BOX HIGHLIGHT
S A KINKED
COOLING HOSE THAT WA
S DISCOVERED DURING
THE
REMOVAL AND DISASSEM
BLY OF THE
SSD
IN
A
UGUST
2007.

I
DEALLY
,
THE BLUE CORRUGATED
HOSE
SHOULD HAVE PROTECTE
D THE BLACK VACUUM L
INE

BUT DID NOT IN THIS
CASE
.

T
HE EXISTING
HOSES WILL BE REPLAC
ED WITH LARGER AND S
TIFFER HOSES OR ALTE
RNATIVELY SEVERAL LI
NES CAN
BE REPLACED WITH A H
ARD
-
COVERED PLENUM
.
................................
................................
...................
78

F
IGURE
56:

E
XAMPLE OF
ADC
AND
C
ONTROL
B
OARD TEMPERATURE EVO
LUTION DURING
2
HOURS OF
RUNNING
.

T
HE ELECTRICAL POWER
WAS SWITCHED OFF AFT
ER
1.8
HOUR WHILE THE COOL
ING
REMAINED ON
.

T
HE INPUT AIR WAS HEL
D AT A CONSTANT
19

C
WHILE THE OUTPUT AI
R AVERAGED
29


C.
................................
................................
................................
................................
........................
80

F
IGURE
57:

A
TYPICAL VACUUM SYST
EM FROM
D
UST
C
OLLECTION AND
V
ACUUM
S
YSTEMS
,

I
NC
.
..................
81

F
IGURE
58:

D
ETAIL OF CENTRAL ARE
A OF CONE WITH ATTAC
HMENT AND GEOMETRICA
L TUNING PARTS OF
THE
SSD.

T
HIS PICTURE SHOWS TH
E DESIGN OF THE EXIS
TING
STAR
CONE
.
................................
......
82

F
IGURE
59:

D
ETAIL OF THE INTERFA
CE BETWEEN
SSD
AND C
ONE
(
THE ORANGE PART IS G
LUED TO THE
CONE
).
................................
................................
................................
................................
...................
82



7

F
IGURE
60:

T
HE LEFT PANEL SHOWS
THE
SSD
MOUNT BEFORE IT IS
MOUNTED ON THE CONE
.

T
HE RIGHT
PANEL SHOWS THE
SSD
MOUNT AFTER IT IS A
TTACHED TO THE CONE
.

T
HE BLACK ELECTRICAL
INSULA
TOR THAT ISOLATES TH
E
SSD
FROM THE REST OF TH
E SYSTEM IS SHOWN UN
DER THE TIP OF THE
ARROW
.
................................
................................
................................
................................
.................
82

F
IGURE
61:

C
ABLING PATHS FOR THE

SSD.
................................
................................
................................
...
84

F
IGURE
62:

(L
EFT
)
DISTRIBUTION OF NUM
BER OF DEPOSITED ELE
CTRO
NS ON PIXELS FROM A
SINGLE
CHARGED PION WITH
45
DEGREE INCIDENT ANG
LE FROM THE SLOW SIM
ULATOR
;

(
RIGHT
)
PROFILE OF
THE FRACTION OF DEPO
SITED NUMBER OF ELEC
TRONS FROM SIMULATIO
N
(
BLUE
)
AND DATA
[10]

(
RED
).
................................
................................
................................
................................
..............................
98

F
IGURE
63:

F
UNCTIO
NAL SCHEMATIC DIAGRA
M FOR ONE
P
HASE
-
1
SENSOR BASED
RDO
BOARD
.

E
ACH
RDO

BOARD SERVICES ONE I
NNER LADDER AND
3
OUTER LADDERS
.

E
ACH LADDER CONTAINS
10
SENSORS
.
................................
................................
................................
................................
............................
105

F
IGURE
64:

B
ANDWIDTH OF A SINGLE
CHANNEL OF THE
SIU

-

RORC
FIBE
R OPTIC LINK AS A FU
NCTION OF
EVENT FRAGMENT SIZE
WITH AN INTERNAL AND
EXTERNAL
(DDL)
DATA SOURCE USING T
WO
D
-
RORC

CHANNELS
.

F
ROM THE
LECC

2004

W
ORKSHOP IN
B
OSTON
.
................................
.............................
107

F
IGURE
65:

C
HRONOGRAM OF THE
P
HASE
-
1
BASED READOUT SYSTE
M
FUNCTIONS FOR A
1
K
H
Z PERIODIC
TRIGGER
.
................................
................................
................................
................................
.............
108

F
IGURE
66:

C
HRONOGRAM OF THE
P
HASE
-
1
BASED READOUT SYSTE
M FUNCTIONS FOR A
2
K
H
Z PERIODIC
TRIGGER
.
................................
................................
................................
................................
.............
108

F
IGURE
67:

F
UNCTIONAL SCHEMATIC
DIAGRAM FOR ONE
U
LTIMATE SENSOR BASED

RDO
BOARD
.

E
ACH
RDO
BOARD SERVICES ONE
INNER LADDER AND
3
OUTER LADDERS
.

E
ACH LADDER CONTAINS
10

SENSORS
.
................................
................................
................................
................................
.............
109

F
IGURE
68:

C
HRONOGRAM OF THE
U
LTIMATE SENSOR BASED
READOUT SYSTEM FUNC
TIONS FOR A
1
K
H
Z
PERIO
DIC TRIGGER
.
................................
................................
................................
.............................
111

F
IGURE
69:

C
HRONOGRAM OF THE
U
LTIMATE SENSOR BASED
READOUT SYSTEM FUNC
TIONS FOR A
2
K
H
Z
PERIODIC TRIGGER
.
................................
................................
................................
.............................
112

F
IGURE
70:

FEA
RESULTS FOR GRAVITY
DEFORMATION OF A
120
MICRON CARBO
N COMPOSITE SUPPORT
STRUCTURE CARRYING
4
DETECTOR LADDERS
.
................................
................................
...................
115

F
IGURE
71:

S
HORT SECTION OF LADD
ER STRUCTURE SHOWING
PROBLEMS WITH EXCES
SIVE THERMAL
BIMETAL EFFECT BENDI
NG WITH USING STIFF
ADHESIVE
.

T
HE
500
MICRON DISPLACEMENT
RESULTING
FROM A
20
DEG
C
TEMPERATURE CHANGE
IS DRIVEN BY THE LAR
GE
CTE
OF THE KAPTON CABLE
.
...
116

F
IGURE
72:

T
HERMALLY INDUCED DIS
PLACEMENT OF A SECTO
R BEAM WITH END REIN
FORCEMENT
.

T
HE
MAXIMUM RESULTING DI
SPLACEMENT IS
9


M
.

T
HE BEAM AND END REIN
FORCEMENT IS COMPOSE
D OF
200


M CARBON COMPOSITE
.
................................
................................
................................
..............
116

F
IGURE
73:

D
ISPLACEMENT OF AN EA
RLY INSERTION HINGE
DESIGN UNDER COCKING
LOAD OF THE
LATCHING MECHANISM
.

T
HE DISPLACEMENT IN T
HE IMAGE IS MAGNIFIE
D BY
140
AND THE MAXIMUM
DISPLACEMENT IS
210
MICRONS
.

T
HE PINK LINES SHOW T
HE POSITION OF THE R
EMOTE LOAD AS IT IS
CARRIED THROUGH THE
D
TUBE
,
NOT SHOWN
.
................................
................................
...................
117

F
IGURE
74:

D
ISTORTION OF SUPPORT
HINGE BACKER UNDER
LATCH COCKING LOAD
.


T
HE FLEXING IN THE
BEAM AXIS DIRECTION
IS
90
MICRONS
.
................................
................................
...............................
118

F
IGURE
75:

T
HIS SHOWS THE VIBRAT
ION RESPONSE OF MECH
ANICAL HARMONIC OSCI
LLATOR MOUNTED ON
THE
TPC
END CAP AS DETERMIN
ED WITH MEASUREMENTS
OF AN ACCELEROMETER
BOLTED TO
THE
TPC
END CAP
.

T
HE TWO CURVES REPRES
ENT MEASUREMENTS MAD
E USING TWO DIFFEREN
T METHODS
OF RECORDING THE DAT
A
.
................................
................................
................................
..................
119

F
IGURE
76:

S
TREAM LINES SHOWING
THE COOLING AIR FLOW
.

T
HE FLOW DIRECTION IS
FROM INSIDE TO
OUTSIDE
.

T
HE COL
OR CODE SHOWS AIR VE
LOCITY
.
................................
................................
...........
121

F
IGURE
77;

S
URFACE TEMPERATURE O
F SILICON LADDERS
.

T
HE MAXIMUM TEMPERATU
RE INCREASE ABOVE
AMBIENT IS
12
DEG
C.

T
HE COOLING AIR FLOWS
ACROSS BOTH THE INN
ER AND OUTER SURFACE
S
.

T
HE
AIR ENTERS F
ROM THE LEFT ON THE
INSIDE OF THE SUPPOR
T BEAM
,
TURNS AROUND AT THE
RIGHT AND
EXITS ON THE LEFT
.
................................
................................
................................
.............................
122

F
IGURE
78:

S
ECTOR COOLING WITH T
RANSVERSE JETS OF CO
OLING DIRECTED TO TH
E INSIDE OF THE SECT
OR
BEAM SUPPORT STRUCTU
RE THROUGH
THIN SLOTS
.

T
HE AIR VELOCITY PROF
ILE IS SHOWN IN COLO
R
.

T
HE AIR VELOCITY NEAR
THE SURFACES BENEAT
H THE LADDERS IS
11
M
/
S
.
................................
......
123

F
IGURE
79:

S
ILICON SURFACE TEMPE
RATURE PROFILE FOR T
HE TRANSVERSE COOLIN
G JET DESIGN
.
.........
124

F
IGURE
80:

P
HYSICAL LAYOUT OF TH
E
RDO
SYSTEM
.
................................
................................
................
125

F
IGURE
81:

F
UNCTIONAL BLOCK DIAG
RAM OF THE
LVDS
DATA PATH TEST SYST
EM
.
................................
126



8

F
IGURE
82:

M
OCK LADDER
PCB
AS USED IN THE TEST
S
.
................................
................................
.............
127

F
IGURE
83:

M
ASS TERMINATION BOAR
D AS USED IN THE TES
T
.

L
ADDER CONNECTION IS
TO THE LEFT OF THE
BOARD
,

6
M CABLE TO
V
IRTEX
5
INTERFACE
RDO
BOARD IS ON THE RIG
HT
.

T
HE DAUGHTER CARD
MOUNTED TO THE MIDDL
E OF THE BOARD SUPPL
IES
LATCH UP PROTECTED A
ND MONITORED POWER
.

N
OTE THAT THERE ARE T
WO DATA PATHS
.

O
NE IS UN
-
BUFFERED AND THE OTH
ER IS BUFFERED
THROUGH
F
IN
1108

LVDS
BUFFERS
.
................................
................................
................................
...
127

F
IGURE
84:

V
ERTEX
-
5
INTERFACE BOARD MOU
NTED TO THE
X
ILINX
V
IRTEX
-
5
DEVE
LOPMENT BOARD
.

T
HE
TOP VIEW IS ON THE L
EFT SHOWING THE
X
ILINX
V
IRTEX
-
5
DEVELOPMENT BOARD O
N TOP WITH THE
SIU
VISIBLE ON THE
V5IB.

T
HE PHOTOGRAPH ON THE
RIGHT SHOWS THE CAB
LE ATTACHMENT AND
TEST POINTS ON THE
V5IB.
................................
................................
................................
.................
128




9

List
of Tables


T
ABLE
1:

P
ERFORMANCE PARAMETER
S FOR THE PIXEL DETE
CTOR
.
................................
...............................
16

T
ABLE
2:

S
PECIFICATIONS OF THE

P
HASE
-
1
AND
U
LTIMATE SENSORS
.
................................
.........................
19

T
ABLE
3:

P
ARAMETERS USED TO CA
LCULATE DATA
RATES FROM A
P
HASE
-
1
BASED SYSTEM
.
.....................
28

T
ABLE
4:

P
ARAMETERS USED TO CA
LCULATE DATA RATES F
ROM A
U
LTIMATE SENSOR BASED
SYSTEM
.
.....
30

T
ABLE
5:

P
RELIMINARY ESTIMATE
OF HEAT LOAD ON THE
CHILLER FOR THE PI
XEL AIR COOLING SYST
EM
.
..
40

T
ABLE
6:

A
CALCULATION OF THE
POINTING RESOLUTION
OF THE
TPC+SSD+IST+PIXEL
DETECTORS AT
INTERMEDIATE POINTS
ALONG THE PATH OF A
750

M
E
V
KAON AS IT IS TRACK
ED FROM THE OUTSIDE


IN
.

G
OOD RESOLUTION A
T THE INTERMEDIATE P
OINTS IS NEEDED TO R
ESOLVE AMBIGUOUS HIT
S ON
THE NEXT LAYER OF TH
E TRACKING SYSTEM
.
................................
................................
.......................
64

T
ABLE
7:

E
STIMATED AND MEASURE
D POWER USED BY THE
FEE
IN THE EXISTING
SSD
ELECTRONICS
.
.......
76

T
ABLE
8:

E
STIMATED AND MEASURE
D POWER FOR THE
ADC
AND
C
ONNECTION
B
OARDS
.
..........................
76

T
ABLE
9:

E
STIMATED POWER CONSU
MPTION FOR A LADDER
................................
................................
.........
76

T
ABLE
10:

M
EAN ELECTRONICS TEMP
ERATURES MEASURED ON
THE TEST LADDE
RS WITH COOLING OFF
.

T
HE
AMBIENT AIR TEMPERAT
URE WAS
19

C.
................................
................................
...............................
79

T
ABLE
11:

M
EAN ELECTRONICS TEMP
ERATURES MEASURED ON
THE TEST LADDER WIT
H COOLING ON
.

T
HE
AMBIENT AIR TEMPERAT
URE AND INPUT AIR TE
MPERATURE WAS
19

C.
................................
..............
79

T
ABLE
12:

M
EAN
T
EMPERATURES MEASURED
AT VARIOUS POINTS A
LONG THE TEST LADDER
WITH THE
COOLING SYSTEM TURNE
D ON
.

T
HE COLUMN ON THE LEF
T IDENTIFIES THE WAF
ER NUMBER
(1
-
16).
..
79

T
ABLE
13:

A
TYPICAL VACUUM SYST
EM FROM
D
UST
C
OLLECTION AND
V
ACUUM
S
YSTEMS
,

I
NC
.
...................
81

T
ABLE
14:

SSD

C
ABLE PARAMETERS
.

T
HE AREA FOR THE CABL
E SIZE IS CALCULATED
ASSUMING IT IS
SQUARE
.
................................
................................
................................
................................
................
85

T
ABLE
15:

P
ARAMETERS FOR THE
P
HASE
-
1
BASED
DETECTOR SYSTEM USED
IN THE EXAMPLE CALC
ULATIONS
SHOWN BELOW
.
................................
................................
................................
................................
...
104

T
ABLE
16:

P
ARAMETERS FOR THE
U
LTIMATE SENSOR BASED
DETECTOR SYSTEM USE
D IN THE EXAMPLE
CALCULATIONS SHOWN B
ELOW
.
................................
................................
................................
.........
110




10

1.

Introduction

The Heavy Flavor Tracker (HFT) is a state
-
of
-
the
-
art microvertex detector utilizing
active pixel sensors and silicon strip technology. The HFT will significantly extend the
physics reach of the STAR experiment for precision measurement of the yields and
s
pectra of particles containing heavy quarks. This will be accomplished through
topological identification of D mesons by reconstruction of their displaced decay vertices
with a precision of approximately 50

m in p+p, d+A, and A+A collisions.

The HFT consi
sts of 4 layers of silicon detectors grouped into three sub
-
systems with
different technologies, guaranteeing increasing resolution when tracking from the TPC
towards the vertex of the collision. The Silicon Strip Detector (SSD) is an existing
detector in
double
-
sided strip technology. It forms the outermost layer of the HFT.
The

Intermediate Silicon Tracker (IST), consisting of a layer of single
-
sided strip
-
pixel
detectorss, is located inside the SSD. Two layers of Silicon Pixel Detector (PIXEL) are
ins
ide the IST. The PIXEL detectors have the resolution necessary for a precision
measurement of the displaced vertex.

The PIXEL detector will use CMOS Active Pixel Sensors (APS), an innovative
technology never used before in a collider experiment.
The
APS
sensors are only 50

m
thick with the first layer at a distance of only 2.5 cm from the interaction point. This
opens up a new realm of possibilities for physics measurements. In particular, a thin
detector (0.28% radiation length per layer) in STAR mak
es it possible to do the direct
topological reconstruction of open charm hadrons down to very low transverse
momentum by the identification of the charged daughters of the hadronic decay.




11

2.

Functional Requirements

2.1.

General Design Considerations

STAR is a la
rge acceptance experiment with full azimuthal coverage at mid
-
rapidity in
the pseudo
-
rapidity range |n| < 1. With the TPC as a central detector and a current read
-
out speed of about 100 Hz STAR is considered to be a “slow” detector as far as single
partic
le observables are concerned. Even after the DAQ upgrade to 1000 Hz in 2009 the
read
-
out speed will be limiting the single particle capabilities of STAR. The real strength
of STAR, good particle identification and full azimuthal coverage, come into play
when
correlations or multi
-
particle final states are studied. Good particle identification and full
azimuthal coverage have been the bases for the enormous success of the STAR physics
program.

It is obvious that when it comes to identifying rare processes
, like heavy flavor
production with multi
-
particle final states, full azimuthal coverage will be of utmost
importance. Thus, full azimuthal coverage is a prime design requirement for the HFT.

Another important requirement is to keep a very low overall mat
erial budget in order to
limit the effects of multiple scattering and of conversions. Our goal is to overall reduce
the radiation length of the inner tracking and support system compared to the status when
the SVT was the STAR inner tracking detector.

The
performance requirements listed below are selected so that if those requirements are
met by the detector, the detector will be able to achieve the physics requirements.
Fulfillment of the performance requirements can be completely determined shortly afte
r
the installation of the HFT.

2.2.

Pointing Resolution

Heavy flavor hadrons have extremely short life times (c
τ
~ 50

m). Identifying such a
short displaced vertex requires extremely good pointing resolution. This is especially
important for the identificati
on of low transverse momentum decays where small gains in
pointing resolution lead to large gains in detection efficiency. The pointing resolution in
r
ϕ
and in z
-
direction are shown in
Figure
1
as a function of p
T
.



12


Figure
1
:
Comparison of three different types of simulations to determine the pointing resolution in
r
ϕ
and in the z
-
direction at the vertex. The three methods are the Toy Model, a Toy Simulation, and
the full STAR Simulation. Each method ha
s different assumptions and slightly different parameters
but overall, the agreement is good. In the figure’s legend, BP is short hand for “beam pipe”.

We require a pointing resolution of better than 50

m for kaons of 750 MeV/c. 750
MeV/c is the mean mom
entum of the decay kaonskanos from D mesons of 1 GeV/c
transverse momentum, the peak of the D meson distribution.

The pointing resolution that will be achieved by the HFT can be calculated from the
design parameters.

2.3.

Multiple Scattering in the Inner Layer
s

The precision with which we can point to the interaction vertex is determined by the
position resolution of the pixel detector layers and by the effects of multiple scattering in
the material the particles have to traverse. The beam pipe and the first p
ixel layer are the
two elements that have the most adverse effect on pointing resolution. Therefore, it is


13

crucial to make those layers as thin as possible and to build them as close as possible to
the interaction point.

We have chosen a radius of 2 cm for
a new beam pipe. Making this radius even smaller
would make the STAR beam pipe the limiting aperture of the RHIC ring. This is not a
desirable situation. The central section of the beam pipe will be fabricated from
Beryllium. Such a beam pipe can have a
minimal wall thickness of
500


m, equivalent
to 0.xx % of a radiation length.

The two pixel layers will be at a radius of 2.5 cm and 8 cm, respectively. The sensors
will be thinned down to 50

m and the ladders will be fabricated in ultra
-
light carbon
fi
bre technology. The total thickness of the beam pipe and the fist pixel layer will be the
equivalent of 0.xx % of a radiation length. With those parameters, the contributions to
the pointing resolution from multiple scattering and from detector resolution
will be
about equal.

The radiation lengths of the two innermost structures, the beam pipe and the first pixel
layer, are design parameters.

2.4.

Internal Alignment and Stability

The Pixel and the IST positions need to be known and need to be stable over a long
time
period in order not to have a negativean effect on the pointing resolution. The quality of
the data will depend on alignment and long term stability. This is especially important for
the Pixel detector that needs to be installed and removed on a sho
rt time scale.

The alignment and stability need to be better than 300

m for the IST and better than 20

m for the Pixel.

Those parameters can be determined from a survey.

2.5.

Pixel Integration Time

Compared to the strip detectors, the Pixel is a slow device w
ith a long integration time.
All events that occur during the integration or life time of the Pixel will be recorded.
This makes assigning Pixel hits to a particular track in the TPC a difficult pattern
recognition problem.

From detailed simulations we ha
ve concluded that at RHIC II luminosities the detection
and reconstruction efficiency for D
-
mesons is not appreciably degraded due to multiple
events and tracks in the Pixel if the integration time of the detector is smaller than 200

s.

The Pixel integrat
ion time is a design parameter.



14

2.6.

Read
-
out Speed and Dead Time

In the absence of a good trigger for D
-
mesons it is imperative for the measurement of rare
processes to record as many events as possible and as required by the physics processes.
In STAR the sp
eed of the DAQ is the limiting factor for the number of events recorded.

In order not to slow down the STAR DAQ, the HFT read
-
out speed needs to be
compatible with the STAR DAQ speed and the HFT needs to be dead time free.

Read
-
out speed and dead time are
design parameters.

2.7.

Detector Hit Efficiency

The hit efficiency of the Pixel and IST detectors is essential for good detection efficiency.
In the case of secondary decay reconstruction, the hit inefficiency of each detector layer
enters with the power of t
he number of reconstructed decay particles into the total
inefficiency.

In order to keep inefficiency low, we request that each individual detector layer has a hit
efficiency of better than 95%.

The hit efficiency of each detector layer can be measured on
the bench before
installation.

2.8.

Life Channels

Dead channels in the Pixel and IST will cause missing hits on tracks and thus lead to
inefficiencies in the reconstruction of decay tracks. Therefore, the number of dead
channels needs to be as low as possible.

The impact of dead channels on the overall performance will be minimal if more than
97% of all channels are alive at any time.

The number of dead channels can be determined immediately after installation of the
detectors.



15

3.

Technical Design

3.1.

Overview

The
Hea
vy Flavor Tracker
consists of three sub
-
detectors: the silicon pixel detector
(PIXEL), the intermediate silicon tracker (IST), and the silicon strip detector (ssd). These
detectors lie inside the
radial location of the
TPC. The primary purpose of the SSD
-
IST
-
PIXEL detector is to provide graded resolution from the TPC into the interaction point
and to provide excellent pointing resolution at the interaction point for resolving
secondary particles and
displaced
decay
vertices
.
The TPC will point at the SSD
with a
resolution of about 1 mm, the SSD will point at the IST with a resolution of about 300

m, the IST will point at the PIXEL with a resolution of about 200

m, and the PIXEL
detector will point at the vertex with less than 50

m resolution.
A schema
tic
view of the
proposed detector layout
is shown in
X
Figure
2
X
.


Figure
2
: A schematic view of the Si detectors that surround the beam pipe. The SSD is an existing
detector and it is the outmost detecto
r shown in the diagram. The IST lies inside the SSD and the
PIXEL lies closest to the beam pipe. The beam pipe and its exo
-
skeleton are also shown.



16

3.2.

Pixel

3.2.1.

Introduction

The PIXEL detector is a low mass detector that will be located very close to the beam
p
ipe. It will be built with two layers of silicon pixel detectors: one layer at 2.5 cm
average radius and the other at 7.0 cm average radius. The outer layer will have 24
ladders and the inner layer will have 9 ladders; for a total of 33. Each ladder con
tains a
row of 10 monolithic CMOS detector chips and each ladder has an active area of 19.2 cm
×
1.92 cm. The CMOS chips contain a 640
×
640 array of 30

m square pixels and will
be thinned down to a thickness of 50

m to minimize Multiple Coulomb Scatter
ing
(MCS) in the detector. The effective thickness of each ladder is 0.28% of a radiation
length.

3.2.2.

Detector Parameters

The relevant performance parameters for the Pixel detector are shown in

Table
1
.


Pointing resolution

(13

19G
eV/p

c)

m

Layers

Layer 1 at 2.5 cm radius

Layer 2 at 8 cm radius

Pixel size

18.4

m
×
18.4

m

Hit resolution

10

m rms

Position stability

6

m (20

m envelope)

Radiation thickness per
layer

X/X0 = 0.28%

Number of pixels

436 M

Integration time (af
fects
pileup)


0.2 ms

Radiation tolerance

300 kRad

Rapid installation and
replacement to cover rad
damage and other
detector failure

Installation and reproducible
positioning in a shift

Table
1
: Performance parameters for the pi
xel detector.



17

3.2.3.

Sensors and Readout

Development and Deployment Plan

We intend to approach the completion of the Pixel detector for STAR as a two stage
development process with the readout system requirements tied to the stages of sensor
development effort.
The sensor development is taking place at the Institut
Pluridisciplinaire Hubert Curien (IPHC) in Strasbourg, France where we are working in
collaboration with Marc Winter’s group. In the current development path, the first set of
prototype sensors to be
used at STAR will have digital outputs and a 640 µs integration
time. We will use these sensor prototypes to construct a limited prototype detector
system for deployment at the STAR detector during the summer of 2010. This prototype
system will employ th
e mechanical design to be used for the final Pixel detector as well
as a readout system that is designed to be a prototype for the expected final readout
system to be deployed with the final Pixel sensors in a complete detector in the 2012 time
frame.

Mono
lithic Active Pixel Sensor (MAPS) Development at IPHC

The sensor development path for the Pixel detector sensors is tailored to follow the
development path of the technology as it was set by the IPHC group. In this path, MAPS
sensors with multiplexed seri
al analog outputs in a rolling shutter configuration are
envisioned as the first generation of sensors followed by a more advanced final or
ultimate sensor that had a digital output(s). The analog MAPS have been produced and
tested and our sensor developm
ent path moves to digital binary readout from MAPS with
fine grained threshold discrimination, on chip correlated double sampling (CDS) and a
fast serial LVDS readout. A diagram showing the current development path and with the
attendant evolution of the
processing and readout requirements is shown in
Figure
3
.



18



Figure
3
: Diagram showing the sensor development path of sensors for the STAR Pixel detector at
IPHC in Strasbourg, F
rance. The readout data processing required is shown as a function of sensor
generation. The first generation Mimostar sensors are read out via a rolling shutter type analog
output. The next generation Phase
-
1 sensor integrates CDS and a column level discr
iminator to give
a rolling shutter binary readout with a 640 µs integration time. The final generation Ultimate sensor
integrates data sparsification and lowers the readout time to < 200 µs.

The Mimostar series sensors are the generation of sensors that ha
ve been fabricated and
tested. These are 50 MHz multiplexed analog readout sensors with 30µm
×
30µm pixels
in variously sized arrays depending on generation. This generation has been tested and
characterized and, with the exception of some yield issues,
appears to be well understood.
Testing with these sensors is well described in a NIM paper reference.

The next generation is named “Phase
-
1”. This sensor will be based on the Mimosa
-
8 and
Mimosa
-
16 sensors and will contain on
-
chip correlated double sampl
ing and column
level discriminators providing digital outputs in a rolling shutter configuration. The
Phase
-
1 will be a full sized 640
×
640 array resulting in a full 2 cm
×
2 cm sensor size. In
order to achieve a 640 µs integration time, the Phase
-
1 sens
or will be equipped with four
LVDS outputs running at 160 MHz. The first delivery of wafers of this sensor design is
expected in late 2008.

The final sensor is named “Ultimate”. The Ultimate sensor includes all of the attributes
of the Phase
-
1 sensor wit
h the pixel sub
-
arrays clocked faster to give a <200 µs
integration time and the integration of a run length encoding based data sparsification and
zero suppression circuit. The pixel size has been reduced to 18.4 µm
×
18.4 µm to
increase the sensor radia
tion tolerance in the higher luminosity RHIC II environment.
There are two data output lines from the sensor and the data rates are low thanks to the
newly included data sparsification circuitry. The first prototypes of this design are
expected to be del
ivered in the 2010 time frame.

Sensor Series Specifications

The specifications of the sensors under development are shown in
Table
2
.

Data Processing in RDO and on chip by
generation of sensor.

The RDO system design evolves with the sensor generation.

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19


Phase
-
1

Ultimate

Pixel Size

30 µm
×
30 µm

18.4 µm
×
18.4 µm

Array size

640
×
640

1024
×
1088

Active area

~ 2
×
2 cm

~ 2
×
2 cm

Frame integration time

640 µs

100

200 µs

Noise after CDS

10 e
-

10 e
-

Readout time / sensor

640 µs

100

200 µs

Outputs / sensor

4

2

Operating mode

Column parallel readout
with all pixels read out
serially.

Column
parallel readout
with integrated serial data
sparsification.

Output type

Digital binary pixel based
on threshold crossing.

Digital addresses of hit
pixels with run length
encoding and zero
suppression. Frame
boundary marker is also
included.

Table
2
: Specifications of the Phase
-
1 and Ultimate sensors.

The Phase
-
1 is a fully functional design prototype for the Ultimate sensor which results in
the Phase
-
1 and Ultimate sensors having very similar physical characteristics. After
succ
essful development and production of the Phase
-
1 sensors, a data sparsification
system currently under development at IPHC will be integrated with the Phase
-
1 design.
With the additional enhancement of design changes allowing for faster clocking of the
su
b
-
arrays, the resulting sensor is expected to be used in the final Pixel detector. In
addition to the specifications listed above, both sensors will have the following additional
characteristics;



Marker for first pixel



Register based test output pattern J
TAG selectable for binary readout
troubleshooting.



JTAG selectable automated testing mode that provides for testing pixels in
automatically incremented masked window to allow for testing within the
overflow limits of the zero suppression system.



Independ
ent JTAG settable thresholds



Radiation tolerant pixel design.



Minimum of 3 fiducial marks / sensor for optical survey purposes.



All bonding pads located along 1 side of sensor



Two bonding pads per I/O of the sensor to facilitate probe testing before sensor

mounting.



20

Architecture for the Phase
-
1 Sensor System

The requirements for the Phase
-
1 prototype and final readout systems are very similar.
They include;



Triggered detector system fitting into existing STAR infrastructure and to interface
to the existing
Trigger and DAQ systems.



Deliver full frame events to STAR DAQ for event building at approximately the
same rate as the TPC (~ 1 KHz for the STAR DAQ1K upgrade).



Reduce the total data rate of the detector to a manageable level (< TPC rate)


We have design
ed the prototype data acquisition system to read out the large body of data
from the Phase
-
1 sensors at high speed, to perform data compression, and to deliver the
sparsified data to an event building and storage device.

The proposed architecture for the r
eadout of the Phase
-
1 prototype system is shown in
with the physical location and separation of the system blocks shown in
Figure
4
and
Figure
5
.

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Figure
4
: Functional block sche
matic for the readout for the Phase
-
1 prototype system. The detector
ladders and accompanying readout system have a highly parallel architecture. One system unit of
sensor array / readout chain is shown. There are ten parallel sensor array / readout chain
units in the
full system.



21

1
-
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Figure
5
: Physical layout of the readout system blocks. This layout will be the same for both the
Phase
-
1 based patch and the final Pixel detector system.

The architecture of the readout system is highl
y parallel. Each independent readout chain
consists of a four ladders mechanical carrier unit with each ladder containing ten Phase
-
1
sensors. The current plan is to install a patch of Phase
-
1 sensors consisting of at least two
carrier units mounted with
the final mechanical positioning structure and positioned with
a 120 degree separation. The readout system will be described as if all carriers will be
installed since this architecture also extends to the final Pixel system.

The basic flow of a ladder da
ta path starts with the APS sensors. A Pixel ladder contains
10 Phase
-
1 APS sensors, each with a 640
×
640 pixel array. Each sensor contains four
separate digital LVDS outputs. The sensors are clocked continuously at 160 MHz and
the digital data contain
ing the pixel threshold crossing information is read out, running
serially through all the pixels in the sub
-
array. This operation is continuous during the
operation of the Phase
-
1 detectors on the Pixel ladder. The LVDS digital data is carried
from the
four 160 MHz outputs in each sensor in parallel on a low mass flex printed
circuit board to discrete LVDS buffers located at the end of the ladder and out of the low
mass detector region. This electronics portion of the ladder also contains the buffers an
d
drivers for the clocks and other control signals needed for ladder operation.

Each Phase
-
1 sensor requires a JTAG connection for register based configuration, power,
ground, a 160 MHz readout clock and a synchronization signal to begin the readout.
Thes
e signals and latch
-
up protected power as well as the LVDS outputs and
synchronization and marker signals from the detectors are carried via low mass twisted
pair cables from the discrete electronics at the end of the ladder to a power / mass
termination b
oard located approximately 1 meter from the Pixel ladders. There is one
readout board per Pixel carrier (40 sensors). A diagram of a ladder is shown in

Figure
6
.



22


Figure
6
: Ass
embly of sensors on a low radiation length kapton flex cable with aluminum
conductors. The sensors are connected to the cable with bond wires along one edge of the ladder.

The flex cable parameters are shown below;



4 layer
-
150 micron thickness



Aluminum
Conductors



Radiation Length ~ 0.1 %



40 LVDS pair signal traces



Clock, JTAG, sync, marker traces.

The connection to the driver end of the ladders will be made with very fine 150 µm
diameter twisted pair wire soldered to the cable ends. These wires are also
very low
stiffness to avoid introducing stresses and distortions into the mechanical structure. The
other ends of these fine twisted pair wires will be mass terminated to allow connection to
the Power / Mass
-
termination (PM) board located approximately 1
meter away.

Latch
-
up protected power is provided to the sensors from the PM boards. Each ladder
has independently regulated power with latch up detection circuitry provided by a power
daughter card that plugs into the PM board. There are four regulati
on and latch
-
up
daughter cards per PM board and a total of ten PM boards are needed for the complete
detector system readout. A block diagram for the PM board is shown in

Figure
7
.

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23


Figure
7
: Power and mass
-
termination board block diagram. The digital signals to and from the
sensors are routed through the main board and carried to mass termination connectors for routing to
the readout boards. Latch
-
up protected power regulatio
n is provided to each ladder by a power
daughter card mounted to the main board. The main power supplies are located in the STAR racks.

The digital sensor output signals are carried with a 160 MHz clock to from the PM board
to the readout boards (RDO) whi
ch are mounted
either
on the magnet iron of the STAR
magnet structure
or in a movable electronics rack located on the cave floor. Each location
is
approximately 6 meters away
from the MTBs
. A diagram describing the attributes of
the two PCBs that make up
the RDO system can be seen in

Figure
8
. A functional block
diagram of the RDO can be seen in

Figure
9
.

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24

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4