VLSI DEsign Methodology

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26 Νοε 2013 (πριν από 3 χρόνια και 8 μήνες)

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EE415 VLSI Design

The Devices:


MOS Transistor

Dynamics

[Adapted from Rabaey’s
Digital Integrated Circuits
,
©
2002, J. Rabaey et al.]

EE415 VLSI Design

Overview
-

Transistor Dynamics


Transistor capacitances


Sub
-
Micron MOS Transistor

»
Threshold Variations

»
Velocity Saturation

»
Sub
-
Threshold Conduction and Leakage


Latchup


Process Variations


Future Perspectives

EE415 VLSI Design

Dynamic Behavior of MOS Transistor


MOSFET is a majority carrier device
(unlike
pn

junction diode)


Delays depend on the time to (dis)charge
the capacitances between MOS terminals


Capacitances originate from three sources:


basic MOS
structure

(layout)


charge present in the
channel


depletion regions

of the reverse
-
biased
pn
-
junctions of drain and source


Capacitances are
non
-
linear

and vary with
the applied voltage

D
S
G
B
C
GD
C
GS
C
SB
C
DB
C
GB
EE415 VLSI Design

MOS Structure Capacitances

Gate Capacitance



Gate isolated from channel by gate oxide

ox
ox
ox
t
C
/



t
ox

is very small <10nm



Results in
gate capacitance C
g

WL
C
C
ox
g

n+

n+

p
-
substrate

Field
-
Oxide

(SiO

2

)

p+ stopper

Polysilicon

Gate Oxide

Drain

Source

Gate

Bulk Contact

CROSS
-
SECTION of NMOS Transistor

EE415 VLSI Design

The Gate Capacitance

EE415 VLSI Design

The Gate Capacitance

Gate Capacitance depends on


channel charge (non
-
linear)


topology


Capacitance due to topology


Source and drain extend below the gate oxide by x
d

(
lateral diffusion
)


Effective length of the channel L
eff

is shorter than the
drawn length by factor of 2x
d


Cause of parasitic overlap capacitance, C
gsO
, between
gate and source (drain)

EE415 VLSI Design

The Gate Capacitance

Overlap Capacitance

Channel Capacitance

EE415 VLSI Design

The Channel Capacitance

Channel Capacitance has three components


capacitance between gate and source, C
gs


capacitance between gate and drain, C
gd


capacitance between gate and bulk region, C
gb


Channel Capacitance values


non
-
linear, depends on operating region


averaged to simplify analysis

EE415 VLSI Design

The Channel Capacitance

Most important regions in digital design: saturation and cut
-
off

Different distributions of gate capacitance for varying

operating conditions

EE415 VLSI Design

Diffusion Capacitance

Bottom Plate Capacitance

Junction Depth

EE415 VLSI Design

Capacitive Device Model

C
GS

= C
gs
+ C
gsO

C
GD

= C
gd
+ C
gdO

C
GB

= C
gb

C
SB

= C
Sdiff

C
DB

= C
Ddiff

D

S

G

B

C

GD

C

GS

C

SB

C

DB

C

GB

EE415 VLSI Design

Transistor Capacitance Values
for 0.25


C
ox

(fF/

m
2
)

C
o

(fF/

m)

C
j

(fF/

m
2
)

m
j


b

(V
)

C
jsw

(fF/

m)

m
jsw


bsw

(V)

NMOS

6

0.31

2

0.5

0.9

0.28

0.44

0.9

PMOS

6

0.27

1.9

0.48

0.9

0.22

0.32

0.9

Example: For an NMOS with L = 0.24

m
,

W = 0.36

m
, L
D

= L
S

= 0.625

m

C
GC

= C
ox

WL = 0.52 fF

C
GSO

= C
GDO

= C
ox

x
d

W = C
o

W = 0.11 fF

so C
gate_cap

=
C
ox
WL + 2C
o
W

= 0.74 fF

C
bp

= C
j

L
S

W

= 0.45 fF

C
sw

= C
jsw

(2L
S

+ W) = 0.45 fF

so C
diffusion_cap

= 0.90 fF

Overlap capacitance

Capacitance of both source and drain

EE415 VLSI Design

Review: Sources of
Capacitance

wiring (interconnect) capacitance

intrinsic MOS transistor capacitances

extrinsic MOS transistor (fanout) capacitances

V
out

C
w

V
in

C
DB2

C
DB1

C
GD12

M
2

M
1

M
4

M
3

V
out2

C
G4

C
G3

V
out2

V
in

V
out

C
L

ndrain

pdrain

EE415 VLSI Design

Gate
-
Drain Capacitance: The
Miller Effect


A capacitor experiencing identical but opposite voltage
swings at both its terminals can be replaced by a
capacitor to ground whose value is two times the
original value

V
in

C
GD1

M
1

V
out


V


V

V
in

M
1

V
out


V


V

2C
GB1


M1 and M2 are either in cut
-
off or in saturation.


The floating gate
-
drain capacitor is replaced by a
capacitance
-
to
-
ground (gate
-
bulk capacitor).

EE415 VLSI Design

Drain
-
Bulk Capacitance: K
eq
’s
(for 2.5

m
)

high
-
to
-
low

low
-
to
-
high

K
eqbp

K
eqsw

K
eqbp

K
eqsw

NMOS

0.57

0.61

0.79

0.81

PMOS

0.79

0.86

0.59

0.7


We can simplify the diffusion capacitance calculations
even

further by using a K
eq

to relate the linearized
capacitor to the value of the junction capacitance under
zero
-
bias

C
eq

= K
eq

C
j0

EE415 VLSI Design

Extrinsic (Fan
-
Out)
Capacitance


The extrinsic, or fan
-
out, capacitance is the total gate
capacitance of the loading gates M3 and M4.


C
fan
-
out

= C
gate

(NMOS) + C
gate

(PMOS)


= (C
GSOn
+ C
GDOn
+ W
n
L
n
C
ox
) + (C
GSOp
+ C
GDOp
+ W
p
L
p
C
ox
)



Simplification of the actual situation

»
Assumes all the components of C
gate

are between V
out

and
GND (or V
DD
)

»
Assumes the channel capacitances of the loading gates
are constant


EE415 VLSI Design

Layout of Two Chained Inverters

W/L

AD (

m
2
)

PD (



A匠(

m
2
)

PS (



NMOS

0.375/0.25

0.3

1.875

0.3

1.875

PMOS

1.125/0.25

0.7

2.375

0.7

2.375

0.125

In

Out

Metal1

V

DD

GND

1.2



m

=2
l

1.125/0.25

0.375/0.25

PMOS

NMOS

Polysilicon

0.5

EE415 VLSI Design

Components of C
L

(0.25

m
)

C Term

Expression

Value (fF)
H

L

Value (fF)
L



C
GD1

2
C
o
n
W
n

0.23

0.23

C
GD2

2
C
o
p
W
p

0.61

0.61

C
DB1

K
eqbpn
AD
n
C
j
+ K
eqswn
PD
n
C
jsw

0.66

0.90

C
DB2

K
eqbpp
AD
p
C
j
+ K
eqswp
PD
p
C
jsw

1.5

1.15

C
G3

(2 C
on
)
W
n
+ C
ox
W
n
L
n

0.76

0.76

C
G4

(2 C
op
)
W
p
+ C
ox
W
p
L
p

2.28

2.28

C
w

from extraction

0.12

0.12

C
L



6.1

6.0

EE415 VLSI Design

The Sub
-
Micron MOS Transistor


Actual transistor deviates substantially from model


Channel length becomes comparable to other device
parameters. Ex: depth of drain and source junctions


Referred to as a
short
-
channel

device


Influenced heavily by secondary effects


Latchup problems

EE415 VLSI Design

The Sub
-
Micron MOS Transistor

Secondary Effects:


Threshold Variations


Parasitic Resistances


Velocity Saturation


Mobility Degradation


Sub
-
threshold Conduction

EE415 VLSI Design

Threshold Variations


Part of the region below gate is depleted by
source and drain
fields
, which reduce the threshold voltage for short channel.


Similar effect is caused by increase in V
DS
, so threshold is
smaller with larger V
DS


V

T

L

Long
-
channel threshold

Low

V

DS



threshold

Threshold as a function of

the length (for low


V
DS
)

Drain
-
induced barrier lowering

V
DS

V
T

lowers V
T

for short channel device

EE415 VLSI Design

Variations in I
-
V Characteristics



The velocity of the carriers is proportional to the electric field up to
a point.


When electric field reaches a critical value, E
sat
, the velocity
saturates
.


When the channel length decreases, only a small V
DS

is needed for
saturation


Causes a
linear dependence

of the saturation current wrt the gate
voltage (in contrast to
squared dependence

of long
-
channel device)


Current drive cannot be increased by decreasing L

EE415 VLSI Design

Velocity Saturation

x


(V/µm)

x

c



= 1.5

u

n



(

m

/

s

)

u

sat



= 10

5

Constant mobility (slope = µ)

Constant velocity

EE415 VLSI Design

Velocity Saturation


We assumed carrier velocity is proportional to E
-
field

»
v

=

E
lat

=

V
ds
/L


At high fields, this ceases to be true

»
Carriers scatter off atoms

»
Velocity reaches
v
sat


Electrons: 6
-
10 x 10
6

cm/s


Holes: 4
-
8 x 10
6

cm/s

»
Better model

lat
sat sat
lat
sat
μ
μ
1
E
v v E
E
E
  

EE415 VLSI Design

Voltage
-
Current Relation:
Velocity Saturation

For short channel devices


Linear: When V
DS



V
GS



V
T

I
D

=

(V
DS
)
k’
n

W/L [(V
GS



V
T
)V
DS



V
DS
2
/2]


where



(V)

= 1/(1 + (V/(
x
c
L))) is a measure of the degree of
velocity saturation



Saturation: When V
DS

= V
DSAT



V
GS



V
T

I
DSat

=

(V
DSAT
)

k’
n

W/L [(V
GS



V
T
)V
DSAT



V
DSAT
2
/2]


EE415 VLSI Design

Velocity Saturation Effects



V
DSAT

< V
GS



V
T
so
the device enters
saturation
before

V
DS

reaches V
GS



V
T
and
operates more often in
saturation


For short channel devices
and large enough V
GS



V
T



I
DSAT

has a
linear dependence

wrt V
GS
so a reduced
amount of current is delivered for a given control voltage

0
10
EE415 VLSI Design

Velocity Saturation

V
DS
(V)
I
D

(
m
A
)
L
i
n
e
a
r

D
e
p
e
n
d
e
n
c
e
V
GS
= 5
V
GS
= 4
V
GS
= 3
V
GS
= 2
V
GS
= 1
0.0
1.0
2.0
3.0
4.0
5.0
0.5
1.0
1.5
(a)
I
D
as a function of
V
DS
(b)
I
D
as a function of
V
GS
(for
V
DS
= 5 V)
.
0.0
1.0
2.0
3.0
V
GS
(V)
0
0.5
I
D

(
m
A
)
Linear Dependence on V
GS
EE415 VLSI Design

Short Channel I
-
V Plot (NMOS)

NMOS transistor, 0.25um,
L
d

= 0.25um
, W/L = 1.5, V
DD

= 2.5V, V
T

= 0.4V

0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
V
DS

(V)

X 10
-
4

V
GS

= 1.0V

V
GS

= 1.5V

V
GS

= 2.0V

V
GS

= 2.5V

Early Velocity

Saturation


Linear

Saturation

EE415 VLSI Design

Leakage Sources


Subthreshold conduction

»
Transistors can’t abruptly turn ON or OFF


Junction leakage

»
Reverse
-
biased PN junction diode current


Gate leakage

»
Tunneling through ultrathin gate dielectric



Subthreshold leakage is the biggest source of DC
power dissipation in modern transistors

D

S

D

S

EE415 VLSI Design

Sub
-
Threshold Conduction

0

0.5

1

1.5

2

2.5

10

-
12

10

-
10

10

-
8

10

-
6

10

-
4

10

-
2

V

GS


(V)

I

D


(A)

V
T

Linear

Exponential

Quadratic

Typical values for S:

60 .. 100 mV/decade

The Slope Factor

ox
D
nkT
qV
D
C
C
n
e
I
I
GS


1

,
~
0
S

is

V
GS

for
I
D
2
/
I
D
1

=10

Slope S

EE415 VLSI Design

Gate Leakage


Carriers tunnel thorough very thin gate oxides


Exponentially sensitive to t
ox

and V
DD




»
A and B are tech constants

»
Greater for electrons


So nMOS gates leak more


Negligible for older processes (t
ox

> 20
Å
)


Critically important at 65 nm and below (t
ox

≈ 10 Å=1nm)

From [Song01]

D

S

I
G

EE415 VLSI Design

Sub
-
Threshold
I
D

vs
V
GS

V
DS

from 0 to 0.5V












kT
qV
nkT
qV
D
DS
GS
e
e
I
I
1
0
V
GS

D

-

V
S

I
D

V
G

+

EE415 VLSI Design

Sub
-
Threshold
I
D

vs
V
DS



DS
kT
qV
nkT
qV
D
V
e
e
I
I
DS
GS













l
1
1
0
V
GS

from 0 to 0.3V

V
D

V
S

V
G

I
D

EE415 VLSI Design

I
D

versus V
GS

0

0.5

1

1.5

2

2.5

0

1

2

3

4

5

6

x 10

-
4

V

GS


(V)

I

D


(A)

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

x 10

-
4

V

GS


(V)

I

D


(A)

quadratic

quadratic

linear

Long Channel

Short Channel

EE415 VLSI Design

I
D

versus V
DS

-
4

V

DS


(V)

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

x 10

I

D


(A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0

0.5

1

1.5

2

2.5

0

1

2

3

4

5

6

x 10

-
4

V

DS


(V)

I

D


(A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive

Saturation

V
DS

= V
GS

-

V
T

Long Channel

Short Channel

EE415 VLSI Design

A unified model

for manual analysis

S

D

G

B

V
T0
(V)


(V
0.5
)

V
DSAT
(V)

k’(A/V
2
)

l
(V
-
1
)

NMOS

0.43

0.4

0.63

115 x 10
-
6

0.06

PMOS

-
0.4

-
0.4

-
1

-
30 x 10
-
6

-
0.1

EE415 VLSI Design

A PMOS Transistor

-
2.5

-
2

-
1.5

-
1

-
0.5

0

-
1

-
0.8

-
0.6

-
0.4

-
0.2

0

x 10

-
4

V

DS


(V)

I

D


(A)

Assume all variables

negative!

VGS =
-
1.0V

VGS =
-
1.5V

VGS =
-
2.0V

VGS =
-
2.5V

PMOS transistor, 0.25um, L
d

= 0.25um, W/L = 1.5, V
DD

= 2.5V, V
T

=
-
0.4V

EE415 VLSI Design

Parasitic Resistances

W

L

D

Drain

Drain

contact

Polysilicon gate

D

S

G

R

S

R

D

V

GS,eff

C
SQ
D
S
D
S
R
R
W
L
R


,
,
Silicide

the bulk region

increase W

R
SQ

is the resistance per square

R
C

is the contact resistance

EE415 VLSI Design

The Transistor as a Switch

I
D
V
DS
V
GS
= V
DD
V
DD
/2
V
DD
R
0
R
mid
V

GS







V

T

R

on

S

D

EE415 VLSI Design

The Transistor as a Switch

0
1
2
3
4
5
6
7
0.5
1
1.5
2
2.5
V
DD

(V)

x10
5

S

D

R
on

V
GS



V
T

V
DD
(V)

1

1.5

2

2.5

NMOS(k

)

35

19

15

13

PMOS (k

)

115

55

38

31

(for V
GS
= V
DD
,
V
DS

= V
DD


V
DD
/2)



Resistance inversely
proportional to W/L (doubling W
halves R
on
)




For V
DD
>>V
T
+V
DSAT
/2, R
on

independent of V
DD




Once V
DD
approaches V
T
, R
on

increases dramatically

R
on

(for W/L = 1
)

For larger devices
divide R
eq

by W/L

EE415 VLSI Design

Summary of MOSFET Operating
Regions


Strong Inversion
V
GS
>

V
T

»
Linear (Resistive)
V
DS
<

V
DSAT

»
Saturated (Constant Current)
V
DS


V
DSAT


Weak Inversion (Sub
-
Threshold)
V
GS


V
T

»
Exponential in
V
GS
with linear
V
DS

dependence

EE415 VLSI Design

Latchup

(a) Origin of latchup
(b) Equivalent circuit
V
DD
R
psubs
R
nwell
p-source
n-source
n
+
n
+
p
+
p
+
p
+
n
+
p
-substrate
R
psubs
R
nwell
V
DD
n
-well
EE415 VLSI Design

Fitting level
-
1 model

to short channel characteristics

V
GS
= 5 V
V
DS
= 5 V
V
DS
I
D
Long-channel
approximation
Short-channel
I
-
V
curve
Region of
matching
Select
k


and
l
such that best matching is obtained @
V
gs
=
V
ds
=
V
DD
EE415 VLSI Design

SPICE MODELS

Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular
Berkeley Short
-
Channel IGFET Model

EE415 VLSI Design

MAIN MOS SPICE PARAMETERS

EE415 VLSI Design

SPICE Parameters for Parasitics

EE415 VLSI Design

Simple Model versus SPICE

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

x 10

-
4

V

DS


(V)

I

D


(A)

Velocity

Saturated

Linear

Saturated

V
DSAT
=V
GT

V
DS
=V
DSAT

V
DS
=V
GT

EE415 VLSI Design


Semiconductor Industry Association
forecast

»
Intl. Technology Roadmap for
Semiconductors

Technology Evolution

EE415 VLSI Design

Process Variations

Devices parameters vary between runs and even on

the same die!

Variations in the process parameters

, such as impurity concentration den
-

sities, oxide thicknesses, and diffusion depths. These are caused by non
-

uniform conditions during the
deposition and/or the diffusion

of the

impurities.
Introduces variations

in the sheet resistances and transistor

parameters such as the threshold voltage.

Variations in the dimensions

of the devices, resulting from the

limited resolution

of the photolithographic process. This causes

(W/L)

variations in MOS transistors and
mismatches

in the emitter areas of

bipolar devices.

EE415 VLSI Design

Impact of Device Variations

1.10

1.20

1.30

1.40

1.50

1.60

L

eff


(in

m)

1.50

1.70

1.90

2.10

D

e

l

a

y



(

n

s

e

c

)


0.90


0.80


0.70


0.60


0.50

V

Tp



(V)

1.50

1.70

1.90

2.10

D

e

l

a

y



(

n

s

e

c

)

Delay of Adder circuit as a function of variations in

L


and

V

T

EE415 VLSI Design

So What?


So what if transistors are not ideal?

»
They still behave like switches.


But these effects matter for…

»
Supply voltage choice

»
Logical effort

»
Quiescent power consumption

»
Pass transistors

»
Temperature of operation

EE415 VLSI Design

Parameter Variation


Transistors have uncertainty in parameters

»
Process: L
eff
, V
t
, t
ox

of nMOS and pMOS

»
Vary around typical (T) values


Fast (F)

»
L
eff
:
____

»
V
t
:
____

»
t
ox
:
____


Slow (S): opposite


Not all parameters are independent


for nMOS and pMOS

nMOS
pMOS
fast
slow
slow
fast
TT
FF
SS
FS
SF
EE415 VLSI Design

Parameter Variation


Transistors have uncertainty in parameters

»
Process: L
eff
, V
t
, t
ox

of nMOS and pMOS

»
Vary around typical (T) values


Fast (F)

»
L
eff
:
short

»
V
t
:
low

»
t
ox
:
thin


Slow (S): opposite


Not all parameters are independent


for nMOS and pMOS

nMOS
pMOS
fast
slow
slow
fast
TT
FF
SS
FS
SF
EE415 VLSI Design

Environmental Variation


V
DD

and T also vary in time and space


Fast:

»
V
DD
: ____

»
T: ____

Corner

Voltage

Temperature

F

T

1.8

70 C

S

EE415 VLSI Design

Environmental Variation


V
DD

and T also vary in time and space


Fast:

»
V
DD
:
high

»
T:
low

Corner

Voltage

Temperature

F

1.98

0 C

T

1.8

70 C

S

1.62

125 C

EE415 VLSI Design

Process Corners


Process corners describe worst case variations

»
If a design works in all corners, it will probably
work for any variation.


Describe corner with four letters (T, F, S)

»
nMOS speed

»
pMOS speed

»
Voltage

»
Temperature

EE415 VLSI Design

Important Corners


Some critical simulation corners include

Purpose

nMOS

pMOS

V
DD

Temp

Cycle time

Power

Subthrehold

leakage

EE415 VLSI Design

Important Corners


Some critical simulation corners include

Purpose

nMOS

pMOS

V
DD

Temp

Cycle time

S

S

S

S

Power

F

F

F

F

Subthrehold

leakage

F

F

F

S

EE415 VLSI Design

Future Perspectives

25 nm FINFET MOS transistor

EE415 VLSI Design

Three
-
Dimensional
Integrated Circuits


Multiple Layers of Active Devices


Driven by

»
Limited floorplanning choices

»
Desire to integrate disparate technologies (GaAs, SOI, SiGe,
BiCMOS)

»
Desire to integrate disparate signals (analog, digital, RF)

»
Interconnect bottleneck



60

2D IC

3D IC

>500µm

As small as 20µm