Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circui...

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© 1995-2008 NEC Electronics Corporation

Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI
Technology and Circuits (1/5)

The "2008 Symposia on VLSI Technology and Circuits"—widely recognized as premiere conferences for presenting research results on
the latest device, process, and circuit-related developments—were held this year at the Hilton Hawaiian Village Hotel in Hawaii, from
June 17 to 20. Here we introduce the papers presented by NEC Electronics or in collaboration with NEC Corporation.

VLSI Symposia Overview
The VLSI Symposia, along with the International Electron Devices Meeting (IEDM) and the International Solid-State Circuits Conference
(ISSCC), are premier conferences devoted to semiconductor technology. The VLSI Symposia consist of two separate events: the VLSI
Technology Symposium that focuses on device and process-related themes, and the VLSI Circuit Symposium that focuses on circuit-
related themes. Prior to the technical sessions, the Symposia also included three one-day short course lectures: "Outlook for 32-
nanometer (nm) to 22-nm generation" at the VLSI Technology Symposium and "Mixed Memory Design" and "Power Management" at
the VLSI Circuits Symposium.


Papers Presented by NEC Electronics
Seven papers from NEC Group were selected for presentation at the two symposia: four for the VLSI Technology Symposium and three
for the VLSI Circuits Symposium.
NEC Electronics researchers were engaged in four of the above: one solely by NEC Electronics researchers, and three in collaboration
with researchers from NEC Corporation.

[ Symposium on VLSI Technology ]


[ Symposium on VLSI Circuits ]



Single-metal/single-dielectric gate stack that realizes triple effective work function for embedded memory application

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Visit the VLSI symposium website
Session 5.3 (collaboration with NEC Corporation)
Single-metal/single-dielectric gate stack that realizes triple effective work function for embedded memory application
Nickel disilicide (NiSi
2
) works well in silicon processes, and for this reason, we succeeded in implementing transistors
that have three different threshold values on the same wafer by using NiSi
2
as the material for a metal gate. This is one
more step forward in the progress toward higher performance and lower cost for system LSI chips that combine DRAM,
SRAM and other types of memory.
Session 11.1 (collaboration with NEC Corporation)
A New Low-k/Cu Dual Damascene (DD) Direct Contact for Low-loss (LL) CMOS Device Platforms
We developed a new structure of scaled-down CMOS devices, of which Cu dual damascene (DD) direct contacts are
made in reliable low-dielectric-constant (k) films of Silica-Carbon Composite (SCC, k=3.1)) and organo-siloxane (SiOCH,
k=3.1).
Session 16.2
Reduction of Vth Variation by Work Function Optimization for 45 and 40 nm Node SRAM Cell
We developed a technique for reducing variation in the characteristics of transistors in LSI chips by using hafnium in the
gate insulation layer. This widens the design margin and makes possible the design of 45- and 40-nanometer (nm)
SRAM, which has previously been thought difficult.
Session 7.2 (collaboration with NEC Corporation)
A Small-Delay Defect Detection Technique That Increases Reliability of LSIs
A newly developed testing technique enables logic circuit delays in chips and test patterns to be measured quickly, and
the small delay defects often missed by conventional screening techniques to be detected, thus enabling us to increase
reliability of our LSI chips.
Summar
y
of NEC Electronics Pa
p
ers Presented at the 2008 S
y
m
p
osia VLSI Technolo
gy
and Circui...

Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI
Technology and Circuits (2/5)

Single-metal/single-dielectric gate stack that realizes triple effective work function for
embedded memory application
Nickel disilicide (NiSi
2
) works well in silicon processes, and for this reason, we succeeded in implementing transistors that have three
different threshold values on the same wafer by using NiSi
2
as the material for a metal gate. This is one more step forward in the
progress toward higher performance and lower cost for system LSI chips that combine DRAM, SRAM and other types of memory.

As we move toward the ubiquitous society in which networks can be accessed from anywhere at any time,
?
obile phones, digital home
appliances, portable digital audio players, car navigation systems and other such equipment are diversifying in function. The LSI chips
used in those devices are also required to have more advanced functionality, lower power consumption, and lower cost, and those
demands are being met by reducing the dimensions of individual transistors, such as shortening gates and making gate insulation
layers thinner. More highly integrated scales deplete the polysilicon gate material and inhibit thinning of the gate insulation layer, so the
use of metal gate material, which cannot be depleted, is expected. With non-depletion metal material, however, it is difficult to adjust
the transistor threshold voltage, and only different metal materials could be used for the n-type and p-type transistors that constitute
complementary inverters (CMOS). These different metal materials require separate fabrication stages that increase cost. Particularly for
low-power implementation of system LSI chips with mixed DRAM, SRAM or other large-capacity, high-speed memory, implementation is
very difficult, as it requires high-threshold transistors for memory cells that emphasize low leakage in addition to the low threshold-
voltage n-type and p-type transistors that are the key to high-speed operation.

In the work reported here, we succeeded in implementing transistors that have three different threshold values on the same wafer by
using nickel disilicide (NiSi
2
) (*1), which works well with silicon processes, as the material for a metal gate (Figure 1). Achieving one
high threshold voltage and two low threshold voltages with a single material makes it possible to implement high-performance system
LSI chips that have mixed high-speed DRAM and SRAM and a low power requirement. Because the NiSi
2
metal material works well with
conventional silicon processes, existing fabrication lines can be used, thus saving costs (Figure 2).


A prototype SRAM cell we fabricated using this transistor (Figure 3) demonstrated a 30% reduction in power consumption compared to
the polysilicon gate (Table 1).
Figure 1 Structure of the new metal-gate transistor (three
work functions achieved with a single metal)
Figure 2 Work function adjustment range is doubled (by
segregation of dopant (As, P, B, etc.))
Summar
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of NEC Electronics Pa
p
ers Presented at the 2008 S
y
m
p
osia VLSI Technolo
gy
and Circui...
© 1995-2008 NEC Electronics Corporation


NEC Corporation and NEC Electronics will continue with vigorous research and development with the aim of providing the low-cost,
energy-efficient system LSI chips that are essential to the ubiquitous society.


Note (*)

1.
NiSi
2
was found in the work reported here to have such features as a low coefficient of volumetric expansion for silicide
conversion, so there is little damage to the transistor when electrodes are formed, and a work function that can be varied by
dopant segregation.


A New Low-k/Cu Dual Damascene (DD) Direct Contact for Low-loss (LL) CMOS Device Platforms

| 1 2 3 4 5 |


Figure 3 Prototype SRAM cell characteristics
Table 1 Low-power index
Summar
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of NEC Electronics Pa
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p
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and Circui...

Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI
Technology and Circuits (3/5)

A New Low-k/Cu Dual Damascene (DD) Direct Contact for Low-loss (LL) CMOS Device
Platforms
We developed a new structure of scaled-down CMOS devices, of which Cu dual damascene (DD) direct contacts are made in reliable
low-dielectric-constant (k) films of Silica-Carbon Composite (SCC, k=3.1)) and organo-siloxane (SiOCH, k=3.1).

As LSI scale increases, parasitic capacitance and contact resistance (parasitic resistance) increase in scaled-down CMOS transistors,
exhibiting greater high-speed-operational losses (Figure 1). NEC Electronics and NEC Corporation have collaborated in developing a
high-speed CMOS device that reduces both contact resistance and parasitic capacitance by implementing a new structure for low-k/Cu
dual damascene direct contact. This new "low-k/Cu DD direct contact" structure embeds copper (Cu) in reliable low-k stacks of SiOCH
(k=3.1) and SCC (k=3.1), and the Cu line at the metal-1 layer is connected directly to MOSFETs (Figure 2).


This technique reduced the contact resistance by about 75%
compared to the conventional structure of high resistance W-plug
and copper wire. The low contact resistance is attained not only by
the low resistivity of Cu but also by the elimination of the hetero-
interface between the W-plug contact and the Cu with high-
resistance Ta/TaN barrier (Figure 3). Introducing low-k films into the
contact layers reduced the contact aspect ratio to less than three.
Reducing the contact aspect ratio to three, similar to the vias
between Cu multi-layer interconnects, makes it possible to use
conventional fabrication facilities for the Cu metallization process. In
other words, introducing the low-k film to the contact layer allows
implementation of the direct contact structure without requiring
investment in new facilities.

Figure 1 Problem with high integration scale CMOS devices
Figure 2 New CMOS device structure
Figure 3 Reduction of contact resistance
Summar
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of NEC Electronics Pa
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and Circui...

Here, for the interlayer insulation layer just on the CMOS device, SCC
film of k=3.1 is used due to the excellent step-coverage (*1). In an
ordinary SiOCH film of a plasma CVD, the activated precursor
materials are piled up on the rug surface of CMOS devices, resulting
in insufficient deposition on sidewalls and in valleys due to the poor
step coverage. The SCC film, however, is deposited by the plasma
polymerization method, so the source material atoms are not
immediately piled up on the surface, but move around before the
reaction takes place. This results in excellent step coverage (Figure
4). This unique SCC film is an NEC-proprietary material achieved
through many years of research on techniques for controlling the
molecular structure of low-k materials by plasma polymerization.

The surface of SiOCH is planarized by a CMP process. The surface is
hydrophobic, so we developed a new CMP process that renders the
surface hydrophilic. After the planarization, the dual damascene
patterns of the contacts and interconnect trenches were formed by
plasma etching (Figure 5). These openings in the low-k stacks were
fulfilled with Cu and Ta/TaN barriers by the conventional Cu
metallization process, resulting in the low-k/Cu DD direct contacts.

We confirmed that reductions of the contact resistance and parasitic
capacitance improved the operating speed of the CMOS transistors
by 7% (Figure 6) with no degradation of the CMOS electrical
characteristics (Figure 7) or of reliability such as NBTI (*2) or TDDB
(*3) (Figure 8).




Figure 4 Low-k contact interlayer insulation layer with
excellent coverage
Figure 5 Planarization of contact interlayer insulation layer
Figure 6 Verification of improvement in basic oscillator circuit
operating speed
Summar
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of NEC Electronics Pa
p
ers Presented at the 2008 S
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p
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and Circui...
© 1995-2008 NEC Electronics Corporation


Achieving the low-loss and high-speed CMOS devices allows higher performance in broadband wireless chips and/or digital devices
equipped with multiple-core CPUs. In future work, we will continue with vigorous research and development activities with the goal of
early development of practical devices.

Notes (*)

1.Step coverage is the ratio of the layer thickness of the step part to the planar part.
2.Abbreviation of Negative Bias Temperature Instability, a type of degradation that occurs when a negative bias is applied to the
gate of a PMOS transistor.
3.Abbreviation for Time-Dependent Dielectric Breakdown, a phenomenon in which damage occurs in the insulation layer after a high
electric field is maintained in the flash state.


Reduction of Vth Variation by Work Function Optimization for 45 and 40 nm Node SRAM Cell

| 1 2 3 4 5 |




Figure 7 Effect of introducing Cu on CMOS device
characteristics
Figure 8 Effects on CMOS reliability (NBTI and TDDB)
Summar
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of NEC Electronics Pa
p
ers Presented at the 2008 S
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m
p
osia VLSI Technolo
gy
and Circui...

Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI
Technology and Circuits (4/5)

Reduction of Vth Variation by Work Function Optimization for 45 and 40 nm Node SRAM Cell
We developed a technique for reducing variation in the characteristics of transistors in LSI chips by using hafnium in the gate insulation
layer. This widens the design margin and makes possible the design of 45- and 40-nanometer (nm) SRAM, which has previously been
thought difficult.

As the integration scale of transistors increases, the variance in
doping within a channel increases. That variance appears as variation
in the threshold voltage measurement, and the variation becomes
more apparent as transistor dimensions decrease or as dopant levels
increase (Figure 1). SRAM is particularly sensitive to threshold
voltage variation, so the circuit operating margin for writing and
reading is about zero in the 45- and 40-nanometer (nm) generation,
and the resulting difficulty of design is a problem. Therefore, to
secure an SRAM circuit operating margin, we considered a method in
which a circuit that applies a supplementary voltage that differs from
the LSI reference voltage is incorporated in advance. Although that
method can secure a circuit operating margin, it increases the area
of the chip.

To overcome that problem, we optimized the transistor channel structure on the basis of a technique developed in the 55-nm process,
in which hafnium is used in the gate insulation layer. By suppressing the short channel effect, which comes with decreased dopant
concentration in the channel and higher integration scales, we were able to both reduce the threshold voltage variation and optimize
the threshold voltage in a low-power-consuming SRAM (Figure 2). For the 45- and 40-nm generation, the threshold-voltage variation
was reduced by 18% even though the area of the SRAM cell decreased (Figure 3). The variation in the driving current was also greatly
reduced (Figure 4). Furthermore, a high yield was secured, even though the SRAM operating voltage was reduced to 0.95V (Figure 5).


Figure 1 Threshold voltage variation for various generations
Figure 2 Hafnium used to reduce threshold voltage variation—
Possible to achieve both least threshold voltage variation and
optimum threshold voltage
Figure 3 Reduction of threshold voltage variation by
hafnium—18% reduction
Summar
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of NEC Electronics Pa
p
ers Presented at the 2008 S
y
m
p
osia VLSI Technolo
gy
and Circui...
© 1995-2008 NEC Electronics Corporation

NEC Electronics continues to develop LSI fabrication processes to secure SRAM design margin and achieve high yield and low cost
fabrication.


A Small-Delay Defect Detection Technique That Increases Reliability of LSIs

| 1 2 3 4 5 |


Figure 4 Comparison of variation in SRAM cell current
Figure 5 SRAM minimum operating voltage
Summar
y
of NEC Electronics Pa
p
ers Presented at the 2008 S
y
m
p
osia VLSI Technolo
gy
and Circui...

Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI
Technology and Circuits (5/5)

A Small-Delay Defect Detection Technique That Increases Reliability of LSIs
A newly developed testing technique enables logic circuit delays in chips and test patterns to be measured quickly, and the small delay
defects often missed by conventional screening techniques to be detected, thus enabling us to increase reliability of our LSI chips.

Finer processes bring greater variation and complicate the defects that arise in LSI fabrication processes. Particularly, the small delay
defects that slightly change the circuit delay are increased, so a screening technique for that type of fault is essential to maintain LSI
reliability.

A widely used method for testing LSI logic circuits is the scan
method, which involves replacing the flip-flop (FF) (*1) in the circuit
with scan-FFs that are capable of shift register (*2) operation to
facilitate testing. That method is currently used to test for delay
faults as well (Figure 1). In delay testing by the scan method, the
initial values of the FF are set by the low-speed scan-in, and then the
test clock is applied to operate the circuit under test at its actual
operating frequency. Then, the results of the low-speed scan-out are
compared with the expected value, and that operation is repeated.

Conventional delay testing is done, however, with the decision criterion set at the actual operating speed after shipping, which results in
an increase in small delays on the short paths and outliers compared to the normal delays caused by the difference between vector-
dependent activated paths and process variations.

We therefore, devised a new delay testing method in which we
measure the delay value of the longest activated path of each
pattern and set the screening criteria according to the statistical
variance in the data (Figure 2). By repeating the testing while
continuously changing the test clock frequency for the same pattern,
we can actually measure longest activated-path delay values, which
vary from pattern to pattern.
Figure 1 Delay testing by scanning
Figure 2 Small delay testing method
Summar
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of NEC Electronics Pa
p
ers Presented at the 2008 S
y
m
p
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and Circui...
© 1995-2008 NEC Electronics Corporation

We also developed a new test circuit that is capable of realizing a
short test time (Figure 3). A self-testing scan-FF reduces the time for
performing multiple scan-outs and scan-ins of the initial values and
results for the same pattern by storing the initial values and
reference values within the scan-FF. Combining the circuit for
generating the test clock, whose frequency is varied incrementally,
with the self-testing scan-FF makes it possible to perform delay
testing at multiple frequencies in a short time.

NEC Electronics is proceeding with the development of highly accurate and low-cost testing techniques based on this new development
to realize more dependable LSIs as semiconductor fabrication processes scale.


Notes (*)

1.Flip-flop
A logic circuit that can temporarily store (remember) one bit of information as the basic binary state of "0" or "1".
2.Shift register
A digital circuit that involves a cascade connection of multiple flip-flops structured to shift data.


| 1 2 3 4 5 |




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Figure 3 Testing circuit
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Summar
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ers Presented at the 2008 S
y
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p
osia VLSI Technolo
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and Circui...

Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
>
Figure 1 Structure of the new metal-gate transistor (three work
functions achieved with a single metal)


©
NEC Electronics Corporation
Fi
g
ure 1 Structure of the new metal-
g
ate transistor
(
three work functions achieved with a sin
g
le me...

Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
>
Figure 2 Work function adjustment range is doubled (by
segregation of dopant (As, P, B, etc.))


©
NEC Electronics Corporation
Fi
g
ure 2 Work function ad
j
ustment ran
g
e is doubled
(
b
y
se
g
re
g
ation of do
p
ant
(
As, P, B, etc.
))

|
W...

Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 3 Prototype SRAM cell characteristics


©
NEC Electronics Corporation
Fi
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ure 3 Protot
yp
e SRAM cell characteristics
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Table 1 Low-power index


©
NEC Electronics Corporation
Table 1 Low-
p
ower index
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 1 Problem with high integration scale CMOS devices


©
NEC Electronics Corporation
Fi
g
ure 1 Problem with hi
g
h inte
g
ration scale CMOS devices
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Figure 2 New CMOS device structure


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ure 2 New CMOS device structure
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Figure 3 Reduction of contact resistance


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Fi
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ure 3 Reduction of contact resistance
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Figure 4 Low-k contact interlayer insulation layer with excellent
coverage


©
NEC Electronics Corporation
Fi
g
ure 4 Low-k contact interla
y
er insulation la
y
er with excellent covera
g
e
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 5 Planarization of contact interlayer insulation layer


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NEC Electronics Corporation
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ure 5 Planarization of contact interla
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er insulation la
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Figure 6 Verification of improvement in basic oscillator circuit
operating speed


©
NEC Electronics Corporation
Fi
g
ure 6 Verification of im
p
rovement in basic oscillator circuit o
p
eratin
g
s
p
eed
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 7 Effect of introducing Cu on CMOS device characteristics


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NEC Electronics Corporation
Fi
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ure 7 Effect of introducin
g
Cu on CMOS device characteristics
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 8 Effects on CMOS reliability (NBTI and TDDB)


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NEC Electronics Corporation
Fi
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ure 8 Effects on CMOS reliabilit
y

(
NBTI and TDDB
)

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Figure 1 Threshold voltage variation for various generations


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NEC Electronics Corporation
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ure 1 Threshold volta
g
e variation for various
g
enerations
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Figure 2 Hafnium used to reduce threshold voltage variation—
Possible to achieve both least threshold voltage variation and
optimum threshold voltage


©
NEC Electronics Corporation
Fi
g
ure 2 Hafnium used to reduce threshold volta
g
e variation—Possible to achieve both least thresh...

Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 3 Reduction of threshold voltage variation by hafnium—
18% reduction


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NEC Electronics Corporation
Fi
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ure 3 Reduction of threshold volta
g
e variation b
y
hafnium—18% reduction
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Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits
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Figure 4 Comparison of variation in SRAM cell current


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ure 4 Com
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arison of variation in SRAM cell current
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Figure 5 SRAM minimum operating voltage


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ure 5 SRAM minimum o
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Figure 1 Delay testing by scanning


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ure 1 Dela
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testin
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b
y
scannin
g

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Figure 2 Small delay testing method


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method
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Figure 3 Testing circuit


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