<span dir="rtl">ا اره VLSI</span>

mittenturkeyΗλεκτρονική - Συσκευές

26 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

327 εμφανίσεις

1
هرا
ا
VLSI
 
ا
اا 
2
Chapter 1
وا هو
3
 وسردع
￿
تاوداCMOS
￿
تارا!"ﺱرو$%)manufacturing technology(
￿
ه!'CMOS (ی*%+$,
ا و(Layout)
￿

ا ت-)نا/ف1/انا*،*یﻥ ا ردظ
56ﺱ، "/نز(
￿
9/ /و 9: /تارا
ا
￿
;%
تارا
ا
￿
ﺱردب=:نا$->د=ﺱادر 
￿
Text:Digital Integrated Circuits, 2
nd
Edition
Rabaeyet. al., ©2002
4
١
@
ا
VLSI
 A=%، یB، ﻥ*اC
B D/ ،ل=Fید
2
-CMOS Digital integrated circuits analysis and design,
Sung-Mo Kang and YusufLeblebici
3
-Principles of CMOS VLSI Design: A Systems
Perspective, Neil H.E. Westeand KamranEshraghian.
4
-Analysis and design of Integrated Digitals Circuits, David
Hodges.
5
-Modern VLSI Design, A System Approach, Wayne Wolf
6
-Basic VLSI Design, D. Pucknell& K. Eshraghian
Textbook
and References
5

￿
=Fتارا(IC)عﻥزا =GرازرددMOSFET$ﺵ .
￿
ICتJ6Kزاا-F:دﺵ ق1 ادهﻥM$زاﺵا /Nیو (ﻥو =(ا
دﺵ ="ﺱنOور ,رP(یترBQﻥO 9/راط6".
￿
ﺵا /ور تJ6KداJ/سﺱا ار=Fتارا(Chip) یزترBنا/ 
د :$=ﺱد:
￿
=Fتارا /یهTﻥ:
U
ltra
L
arge
S
cale
I
ntegration
S
ystem
o
n
C
hip (
SoC
)
￿
ح16Bا وVLSI!ﺱالوا=.
6
ا ,VLSI؟
￿
!ﺱا/در یزدراد9Qزﺱ=Fرد:
￿
Compactness: less area, physically smaller
￿
Higher speed: lower Parasitics(reduced interconnection length)
￿
Lower power consumption
￿
Higher reliability: improved on-chip interconnects
￿
دﺵ $ی*ه+ه:C9ﺱزﺱ=F.
￿
 (یدهﻥ!J$B،تارازﺱ=F W,+یا*%اموا/ Yارده+Zی /ی ﺱزا
!ﺱاJﺱ/وﺵر ;ﻥزانQد[=Kا.
7
Industry Trend
￿
Large
￿
Centralized
￿
Expensive
￿
Small / Portable
￿
Distributed
￿
Inexpensive
8
 Zیر/رو 
9
رو$%MOSFET
￿
MOSFET transistor -Lilienfeld(Canada) in 1925 and Heil(England)
in 1935
￿
CMOS –1960’s,
￿
ﺵهر!"ﺱردت1(GTد و
￿
PMOS in 1960’s (calculators)
￿
رددت1(GNMOSزا\%ا=ا،PMOSﺵ>د=ﺱا.
￿
NMOS in 1970’s (4004, 8080) –for speed
￿
CMOS in 1980’s –preferred MOSFET technology because of power
benefits.
￿
BiCMOS, Gallium-Arsenide, Silicon-Germanium
￿
SOI, …
10
نﻥKMOORE
￿
لﺱرد١٩^_،Gordon Moore  ه:د : $+پ١٨ودJ56ﺱردر=ی*ﻥا /داJ/>
دﺵ  ا .
￿
نﻥKیاسﺱا :
￿
ﺵم1-ا =$ٌﺱرنﻥKیاا.
￿
Ref:
11
Evolution of Minimum Feature Size
12
The First Computer
The Babbage
Difference Engine
(1832)
25,000 parts
cost:
£17,470
13
ENIAC -The first electronic computer (1946)
14
The Transistor Revolution
First transistor
Bell Labs, 1948
15
The First Integrated Circuits
Bipolar logic
1960’s ECL 3-input Gate
Motorola 1966
16
Intel 4004 Micro-Processor
1971
1000 transistors
1 MHz operation
17
Intel Pentium (IV) microprocessor
18
IBM S/390 Microprocessor
IBM S/390 Microprocessor
0.13
cm CMOS process
7 layers Cu interconnect
47 million transistors
1 GHz clock
180 mm
2
19
Evolution in Complexity
20
Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
1
19751980198519901995200020052010
8086
80286
i386
i486
Pentium
®
Pentium
®
Pro
K
1 Billion
1 Billion
Transistors
Transistors
Source: Intel
Source: Intel
Projected
Projected
Pentium
®
II
Pentium
®
III
Courtesy, Intel
21
Die Size Growth
4004
8008
8080
8085
8086
286
386
486
Pentium ®proc
P6
1
10
100
19701980199020002010
Year
Die size (mm)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law
Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
22
Frequency
P6
Pentium ®proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
19701980199020002010
Year
Frequency (Mhz)
Lead Microprocessors frequency doubles every 2 years
Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
23
Power Dissipation
P6
Pentium ®proc
486
386
286
8086
8085
8080
8008
4004
0.1
1
10
100
197119741978198519922000
Year
Power (Watts)
Lead Microprocessors power continues to increase
Lead Microprocessors power continues to increase
Courtesy, Intel
24

ا de=Zح6ﺱ
n+n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
25
 یزراهرJ
￿
$ی*ه)(Cost
￿
ن$ ا!eK)Reliability(
￿
دJارد یfپ g/!eK)Scalability(
￿
!- ﺱ)Speed (delay, operating frequency)(
￿
نا/)Power dissipation(
￿
ر:NیندادمFﻥاا مزhژ ﻥا)Energy to perform a function(
26
Cost of Integrated Circuits
￿
NRE (non-recurrent engineering) costs
￿
design time and effort, mask generation
￿
one-time cost factor
￿
Recurrent costs
￿
silicon processing, packaging, test
￿
proportional to volume
￿
proportional to chip area
27
Die Cost
Single die
Wafer
From http://www.amd.com
Going up to 12”(30cm)
28
Yield
%100
per wafer chips ofnumber Total
per wafer chips good of No.
×=Y
yield Dieper wafer Dies
costWafer
cost Die
×
=
(
)
area die2
diameterwafer
area die
diameter/2wafer
per wafer Dies
2
×
×π

×π
=
29
Defects
α







α
×
+=
area dieareaunit per defects
1yield die
α
is approximately 3
4
area) (die cost dief=
30
Yield Example
Example:
￿
wafer size of 12 inches, die size of 2.5 cm
2, 1 defects/cm
2
, α= 3
(measure of manufacturing process complexity)
￿
252 dies/wafer (remember, wafers round & dies square)
￿
die yield of 16%
￿
252 x 16% = only 40 dies/wafer die yield !
Die cost is strong function of die area
31
32
DC Operation
Voltage Transfer Characteristic
V
IL
V
IH
V
in
Slope = -1
Slope = -1
V
OL
V
OH
V
out
“0”
V
OL
V
IL
V
IH
V
OH
Undefined
Region
“1”
Input and output voltage:
￿
VOH
: Maximum
output voltage when
the output level is logic
“1”
￿
VOL
: Minimum output
voltage when the
output level is logic “0”
￿
VIL
: Maximum input
voltage which can be
interpreted as logic “0”
￿
VIH
: Minimum input
voltage which can be
interpreted as logic “1”
33
Definition of Noise Margins
Noise margin high
Noise margin low
V
IH
V
IL
Undefined
Region
"1"
"0"
V
OH
VOL
NM
H
NM
L
Gate Output
Gate Input
NM
H
= V
OH
–V
IH
NM
L
= V
IL
–V
OL
34
Key Reliability Properties
Conditions for Regeneration
v1
= f(v
0) ⇒v1
= finv(v
2)
v0
v1
v2
v3
v4
v5
v6
v0
v1
v2
v3
f(v)
finv(v)
Regenerative Gate
v0
v1
v2
v3
f(v)
finv(v)
NonregenerativeGate
￿
To be regenerative, the VTC must have a transient region with a
gain
greater
than 1 (in absolute value) bordered by two valid zones
where the gain is
smaller
than 1.
￿
Such a gate has two stable operating points.
35
The Regenerative Property
v0
v1
v2
v3
v4
v5
v6
￿
A gate with regenerative property ensure that a disturbed
signal converges back to a nominal voltage level
-1
1
3
5
0246810
t (nsec)
V (volts)
v0
v2
v1
36
Fan-in and Fan-out
37
The Ideal Gate
Ri
=

R
o
= 0
Fanout = ∞
NM
H
= NM
L
= V
DD
/2
g
= ∞
V
in
V
out
38
Delay Definitions
t
Vout
Vin
input
waveform
output
waveform
t
Vin
Vout
Propagation delay?
signal slopes?
39
Delay Definitions
t
Vout
Vin
input
waveform
output
waveform
tp
= (t
pHL
+ t
pLH
)/2
Propagation delay
t
50%
tpHL
50%
tpLH
tf
90%
10%
tr
signal slopes
Vin
Vout
40
Ring Oscillator
v
0
v1
v5
v1
v2
v
0
v3
v
4
v
5
T = 2
´
t
p
´
N
41
A First-Order RC Network
vout
vin
C
R
tp
= ln(2) τ= 0.69 RC
(ﻥزVout
(t=t
P)=0.50V
42
Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupply
i(t)
Peak power:
Ppeak
= Vsupply
ipeak
Average power:
()
∫∫
++
==
Tt
t
Tt
t
supply
supply
ave
dtti
T
V
dttp
T
P)(
1
43
Energy and Energy-Delay
Power-Delay Product (PDP)
=
E = Energy per operation = Pav
×
tp
Energy-Delay Product (EDP)
=
quality metric of gate = E
×
tp
44
!"ﺱو
ا VLSI
￿
تارا!"ﺱو
ا رد!Kﺱزاا-FVLSI$=هT"د.
￿

ا -اK(design rule)!"ﺱژ$(/سﺱا >ﻥزﺱ\ﺱ/
دﺵ lارا=Fتارا.
￿
ن
ا ICهرا*ازاNﺱ!"ﺱا CAD$$: >د=ﺱا.
45

ا VLSI
￿

ا T
ا VLSI 
￿
رو$%بZ=ﻥا) (Technology
￿
ر=%ر
ا وdB/(Behavioral design)
￿
ر="ﺱ
ا (Structural design)
￿
 6=
ا (Logic design)
￿
 (ی*%
ا (physical design)
￿
زﺱ9ﺵ(simulation)
￿
!"ﺱ(Fabrication)
￿
$=(Packaging)
￿

ا ردیا $VLSIتارا
ا /QیدهﻥNی*%زا /-1 ا: یرادزﻥ
ﺵ=ﺵاد 6$.
46
رو$%
￿
!"ﺱTKدJای =(,:(manufacturablefeature size )رد 
ل
رد:
>زاﻥارددرادجاور!J$B0.05-0.18 micron !ﺱا.
￿
م=$پلnنا$-III،٢٨نOرد>زاﻥای =(,::درادر=ی*ﻥا /نe
0.18µ!ﺱا>د.
￿
 ;ﻥدازا=FتاراSi،GeوGaAs ﻥﺵ ="ﺱ.
￿
 ;ﻥهرو$%

TTL

CMOS
￿
CMOSJی =(,:وh :ا / W,Tد(minimum feature size)
درادارد ر:ی =G.
47
ر=%ر
ا (Behavioral (Functional) Design)
￿
!ﺱا ;ﻥدرراد (e->Aﻥند :qZG
ا ردم'وا.
￿
وهد rﺱپQیدوروﻥW,را: $: qZGF$یاردط9/رانو ﻥد
$: را K .
￿
را*%ا!ZﺱdB/نزNیزا>د=ﺱای (%ا 'شورhJ(VHDL)ز 
دﺵ 5ی G/راد (-.
48
ر="ﺱ
ا (Structural (Architectural) Design) 
￿
>ﺵ=ﺱا"T-ندروO !Qرد e"ادط9/را WﻥW,،
ا یارددﺵ qZG.
￿
زا>د=ﺱار="ﺱ
ا dB/شورNی
schematic diagram
!ﺱا.
￿
G/ارر="ﺱ
ا نا/  یﻥﻥ هنز DJ$tهد :5ی .
49
 (ی*%
ا (Physical design)
￿
دﺵ="ﺱﻥW,ً1-را:دﺵ qZG
ا عﻥیارد.
￿
T
ا ردزﻥدرNﺱند : ها %e
یارد QTlزا (ی!"ﺱde=ZIC
!ﺱا.
￿
اﻥیارهرا*%ام ﻥیو =ﺱدترBارهNﺱیا(CAD)!"ﺱ.
￿
ﺵ دﻥZ=:ترBیپتارازا e".
50
 6$
ا
￿
هد نGﻥار =ﺱ و "ودورو 6$\اور
ا عﻥیا.