National Institute of Electronics and Information Technology (NIELIT ...

mittenturkeyΗλεκτρονική - Συσκευές

26 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

126 εμφανίσεις


National Institute of Electronics and Information Technology (NIELIT)
(formerly DOEACC)
( Autonomous Scientific Society , Department of IT,
Ministry of Communications & Information Technology, Govt. of India)
ISTE Complex, 25 Gandhi Mandapam Road, Anna University Campus, Chennai – 600 025 India

Tel: 044-24421445, 24421446 ; Fax: 044-24421441


“VLSI SYSTEM DESIGN AND VERIFICATION”

Objective:

This three month certification program aims at imparting job-oriented training in “VLSI
design and Verification” using Hardware Description Languages (HDLs), FPGAs and
Application Specific Integrated Circuit (ASICs) from an industry perspective. The course
curriculum is designed to provide strong foundation in Digital Design, HDL Languages,
prototyping cum debugging of designs using FPGA boards and perform design migration from
FPGAs-to-ASICs. More emphasis shall be given to hands-on (practical) sessions to so as to
enhance the chances of immediate employability.

Target Audience
: PG/UG in ECE/EEE/E&I/CSE branches
Pre-requisites:
Candidates are expected to be strong in fundamental topics of Digital Design
and Verilog coding.
Topics covered
:
• Advanced Digital Design
• Semiconductor Technology
• CMOS Circuit design
• Introduction to VLSI
• Hardware Modeling with Verilog (HDL) language
• Verilog coding styles for Synthesis
• FPGA architecture and design methodology
• Advanced FPGA design implementation and prototyping
• RTL Verification & On-chip debugging
• Introduction to Application Specific Integrated Circuits (ASICs)
• Steps involved in Digital ASIC Design
• Functional and Formal Verification
• Project Management
• Mini-Project
EDA Tools & boards
:
• Xilinx ISE v13.1 System Edition
• Spartan 6 FPGA Development Board
• Altera Quartus II v 11.0
• Cyclone IV FPGA Development Board
• Cadence EDA tool

National Institute of Electronics and Information Technology (NIELIT)
(formerly DOEACC)
( Autonomous Scientific Society , Department of IT,
Ministry of Communications & Information Technology, Govt. of India)
ISTE Complex, 25 Gandhi Mandapam Road, Anna University Campus, Chennai – 600 025 India

Tel: 044-24421445, 24421446 ; Fax: 044-24421441


Duration
: 7
th
March to 25
th
May,2012 (120 hours , 3 days per week Wednesday to Friday, 10
hours per week)
Timing
: 1.30 pm to 5 pm
Venue & lab
: NIELIT, Chennai Centre
Course fee
: Rs.16,545 inclusive of all taxes
(Tuition fee – Rs 13000, Registration fee – Rs 2000, Service Tax – 10.3%)
• Registration fee is non-refundable
• Full tuition fee exemption for limited no.of SC/ST candidates

Course in-charge:
T.Mullai, Scientist ‘C’,
tmullai@doeaccchennai.edu.in

(Phone number: 044-24421445 Extn: 206)

￿ For special/weekend batches, contact course in-charge

COURSE STRUCTURE:


This course has a total of 14 modules. Candidates who undergo this course are required to
execute an application-oriented project work.

Sl.No
Module Name
Theory
Hours
Practical
Hours
1.

Advanced Digital Design 5 3
2.

Semiconductor Technology
5 2
3.

CMOS Circuit design
4.

Introduction to VLSI
5.

Hardware Modeling with Verilog
(HDL) language
10 10
6.

Verilog coding styles for Synthesis 5 5
7.

FPGA architecture and design
methodology
5 0
8.

Advanced FPGA design
implementation and prototyping
10 10
9.

RTL Verification & On-chip
debugging
5 5
10.

Introduction to Application Specific
Integrated Circuits (ASICs)
5 5
11.

Steps involved in Digital ASIC Design
12.

Functional and Formal Verification 5 0

National Institute of Electronics and Information Technology (NIELIT)
(formerly DOEACC)
( Autonomous Scientific Society , Department of IT,
Ministry of Communications & Information Technology, Govt. of India)
ISTE Complex, 25 Gandhi Mandapam Road, Anna University Campus, Chennai – 600 025 India

Tel: 044-24421445, 24421446 ; Fax: 044-24421441


13.

Project Management
14.

Mini-Project 5 20
Total Duration – 120 hours
(Theory - 60 hours + Practical - 60 hours)
60 hours 60 hours


DETAILED COURSE CONTENT:


1. Advanced Digital Design
a. Basics of Digital design
b. Combinational circuit design
c. Synchronous / Asynchronous circuit design
d. Finite State Machines (Mealy and Moore)
e. Sequence Detectors
f. Clock Dividers
g. Design Examples

2. Semiconductor Technology
a. Bipolar and MOS technology
b. Fundamentals of MOS transistors
c. MOS V-I Characteristics
d. MOS principle of operation (NMOS,PMOS and CMOS)

3. CMOS Logic Design
a. CMOS Manufacturing Process
b. Importance of Packaging, yield reliability, testing and speed-power product
c. CMOS Switches & Transmission gates
d. Combinational and Sequential logic design using CMOS
e. Design Examples

4. Introduction to VLSI
a. VLSI and its applications
b. VLSI design flow
c. PLDs, CPLDs, FPGAs
d. Full custom/Semi-custom ASICs & SoC
e. Importance of Hardware Description Languages (HDLs)

5. Programming with Verilog (HDL) language
a. Introduction to digital design with Verilog HDL
b. Concepts in Hierarchical Modeling

National Institute of Electronics and Information Technology (NIELIT)
(formerly DOEACC)
( Autonomous Scientific Society , Department of IT,
Ministry of Communications & Information Technology, Govt. of India)
ISTE Complex, 25 Gandhi Mandapam Road, Anna University Campus, Chennai – 600 025 India

Tel: 044-24421445, 24421446 ; Fax: 044-24421441


c. Verilog basic topics – Lexical conventions, data types, system tasks & compiler
directives
d. Modules, Ports and Instantiation methods
e. Gate-Level Modeling
f. Dataflow Modeling
g. Structural Modeling
h. Behavioral Modeling
i. Switch-Level Modeling
j. Tasks and Functions
k. Advanced Topics in Verilog
l. Design Examples

6. Verilog coding styles for Synthesis
a. Combinational logic design using Verilog
b. Sequential logic design using Verilog
c. Useful modeling techniques for RTL design
d. Logic Synthesis & its importance
e. RTL design and Logic Synthesis issues
f. Verilog Constructs – Synthesizable and Non-Synthesizable
g. Design Examples

7. FPGA architecture and design methodology
a. Field Programmable Gate Arrays (FPGAs) – Introduction
b. Popular FPGA vendors – Xilinx & Altera
c. Xilinx / Altera FPGA families & their architecture
d. FPGA Design Flow using Xilinx ISE & Quartus II

8. Advanced FPGA design implementation and prototyping
a. Design implementation steps
b. Design implementation for Xilinx FPGAs
c. Design implementation for Altera FPGAs
d. Steps to download digital design into FPGA
e. Design examples

9. RTL Verification & On-chip debugging
a. Design Verification – Importance
b. Types of Verification
c. Verification methodologies in industry
d. Scripting languages – Perl & Tcl
e. Verification examples

National Institute of Electronics and Information Technology (NIELIT)
(formerly DOEACC)
( Autonomous Scientific Society , Department of IT,
Ministry of Communications & Information Technology, Govt. of India)
ISTE Complex, 25 Gandhi Mandapam Road, Anna University Campus, Chennai – 600 025 India

Tel: 044-24421445, 24421446 ; Fax: 044-24421441



10. Introduction to Application Specific Integrated Circuits (ASICs)
a. ASIC design concepts
b. Front-end and Back-end ASIC Design Flow
c. EDA tools for ASIC Design

11. Steps involved in Digital ASIC Design
a. Linux commands
b. ASIC Digital Design Flow
c. ASIC Digital Design using Cadence packages

12. Functional and Formal Verification
a. Test Vectors and types of Test Benches (TBs)
b. Basic Verification Environment
c. Importance of Functional Verification
d. Difference between Functional and Formal Verification
e. Verification Plan

13. Project Management
a. Project development cycle in Industries
b. Strategies of Project management
c. Database Configuration and version control system
d. CMMI/ ISO Standards and their importance

14. Mini-Project


How to apply:

￿ Registration needs to be done at our centre before Feb 29, 2012 by bringing the
following:
1. Duly filled in registration form
2. Course fees
3. Copy of identity proof