lecture 1 - VLSI Systems Lab - KAIST

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26 Νοε 2013 (πριν από 3 χρόνια και 8 μήνες)

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Introduction to

CMOS VLSI

Design


Introduction

Chong
-
Min Kyung

KAIST

CMOS VLSI Design

0: Introduction

Slide
2

Overall Strategy



예습과

질문을

하자



28 lectures altogether


3 special topics (2/21,26,28)


Chapters 4, 6
-
12


3 lectures for major chapters (4,6,7,8,9,10)


2 lectures for minor chapters (11,12)


Lecture in English, QnA bilingual


Course evaluation : (20% each)


5 take home’s,


5 quiz,


midterm,


final,


course dynamics ; weekly QnA report

CMOS VLSI Design


Weekly QnA report



Write ‘your questions’ and ‘how they were answered.’


Office hour ; Tue, Thu 2:30
-
4:00


Web site, phone x3423


Available by appointment


In either English of Korean


Due next Tuesday class


Paper submission only, no page limit

0: Introduction

Slide
3

CMOS VLSI Design

Introduce yourself


In Korean


Paper submission, no page limit


Due : 2/19 class hour


Contents


Goal of my life, including


What I want to be in ten years


What I want from this course


What I already have about SoC (experience, expertise)


C, SPICE, HDL, layout, SystemC, internship


What I will do to achieve what I want (plan, determination,
strategy)

0: Introduction

Slide
4

CMOS VLSI Design

For Chapters 1,2,3


Read through Ch 1
-
3 until this weekend


Based on your reading,


Submit three questions to the web site, and


Ask one in the class

0: Introduction

Slide
5

CMOS VLSI Design

0: Introduction

Slide
6

Why Silicon ?


Transistors are built on a silicon substrate


Silicon is a Group IV material


Forms crystal lattice with bonds to four neighbors

Si
Si
Si
Si
Si
Si
Si
Si
Si
CMOS VLSI Design

Why CMOS?


Why CMOS?


Bipolar for analog


GaAs for RF


NMOS for high speed, low area


Low power


Mass production brings low cost (scale of economy)


Integration on a single substrate


Why SoC (System on a Chip)?


SiP (Silicon in a Package)

0: Introduction

Slide
7

CMOS VLSI Design

0: Introduction

Slide
8

Dopants


Silicon is a semiconductor


Pure silicon has no free carriers and conducts poorly


Adding dopants increases the conductivity


Group V: extra electron (n
-
type)


Group III: missing electron, called hole (p
-
type)

As
Si
Si
Si
Si
Si
Si
Si
Si
B
Si
Si
Si
Si
Si
Si
Si
Si
-
+
+
-
CMOS VLSI Design

0: Introduction

Slide
9

nMOS Transistor


Four terminals: gate, source, drain, body


Gate


oxide


body stack looks like a capacitor


Gate and body are conductors


SiO
2

(oxide) is a very good insulator


Called metal


oxide


semiconductor (MOS)
capacitor

n+
p
Gate
Source
Drain
bulk Si
SiO
2
Polysilicon
n+
CMOS VLSI Design

0: Introduction

Slide
10

CMOS Inverter

A

Y

0

1

V
DD
A
Y
GND
A
Y
CMOS VLSI Design

0: Introduction

Slide
11

CMOS Inverter

A

Y

0

1

0

V
DD
A=
1
Y=
0
GND
ON
OFF
A
Y
CMOS VLSI Design

0: Introduction

Slide
12

CMOS Inverter

A

Y

0

1

1

0

V
DD
A=
0
Y=
1
GND
OFF
ON
A
Y
CMOS VLSI Design

0: Introduction

Slide
13

CMOS NAND Gate

A

B

Y

0

0

0

1

1

0

1

1

A
B
Y
CMOS VLSI Design

0: Introduction

Slide
14

CMOS NAND Gate

A

B

Y

0

0

1

0

1

1

0

1

1

A=
0
B=
0
Y=
1
OFF
ON
ON
OFF
CMOS VLSI Design

0: Introduction

Slide
15

CMOS NAND Gate

A

B

Y

0

0

1

0

1

1

1

0

1

1

A=
0
B=
1
Y=
1
OFF
OFF
ON
ON
CMOS VLSI Design

0: Introduction

Slide
16

CMOS NAND Gate

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

A=
1
B=
0
Y=
1
ON
ON
OFF
OFF
CMOS VLSI Design

0: Introduction

Slide
17

CMOS NAND Gate

A

B

Y

0

0

1

0

1

1

1

0

1

1

1

0

A=
1
B=
1
Y=
0
ON
OFF
OFF
ON
CMOS VLSI Design

0: Introduction

Slide
18

CMOS NOR Gate

A

B

Y

0

0

1

0

1

0

1

0

0

1

1

0

A
B
Y
CMOS VLSI Design

0: Introduction

Slide
19

Inverter Cross
-
section


Typically use p
-
type substrate for nMOS transistors


Requires n
-
well for body of pMOS transistors

n+
p substrate
p+
n well
A
Y
GND
V
DD
n+
p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor
pMOS transistor
CMOS VLSI Design

0: Introduction

Slide
20

Well and Substrate Taps


Substrate must be tied to GND and n
-
well to V
DD


Metal to lightly
-
doped semiconductor forms poor
connection called Shottky Diode


Use heavily doped well and substrate contacts / taps

n+
p substrate
p+
n well
A
Y
GND
V
DD
n+
p+
substrate tap
well tap
n+
p+
CMOS VLSI Design

0: Introduction

Slide
21

Inverter Mask Set


Transistors and wires are defined by
masks


Cross
-
section taken along dashed line

GND
V
DD
Y
A
substrate tap
well tap
nMOS transistor
pMOS transistor
CMOS VLSI Design

0: Introduction

Slide
22

Detailed Mask Views


Six masks


n
-
well


Polysilicon


n+ diffusion


p+ diffusion


Contact


Metal

Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
CMOS VLSI Design

0: Introduction

Slide
23

Metalization


Sputter on aluminum over whole wafer


Pattern to remove excess metal, leaving wires


p substrate
Metal
Thick field oxide
n well
n+
n+
n+
p+
p+
p+
Metal
CMOS VLSI Design

0: Introduction

Slide
24

Layout


Chips are specified with a set of masks


Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)


Feature size
f

= distance between source and drain


Set by minimum width of polysilicon


Feature size improves 30% every 2
-
3 years


Normalize for feature size when describing design
rules


Express rules in terms of
l

=
f
/2


E.g.
l

= 0.3
m
m in 0.6
m
m process

CMOS VLSI Design

0: Introduction

Slide
25

Simplified Design Rules


Conservative rules to get you started

CMOS VLSI Design

0: Introduction

Slide
26

Inverter Layout


Transistor dimensions specified as Width / Length


Minimum size is 4
l

/ 2
l,
sometimes called 1 unit


In
f

= 0.6
m
m process, this is 1.2
m
m wide, 0.6
m
m
long

CMOS VLSI Design

Chapter 4

Circuit Characterization
and Performance
Estimation

CMOS VLSI Design

Issues in Ch. 4


Delay estimation


Power estimation


Interconnect


Design margin, reliability, scaling

Copyright © 2005 Pearson Addison
-
Wesley. All rights reserved.

4
-
28

CMOS VLSI Design

Delay Estimation


Architecture level


Logic


Circuit


Layout


Copyright © 2005 Pearson Addison
-
Wesley. All rights reserved.

4
-
29

CMOS VLSI Design

Waveform & delay


Rise time/fall time


Propagation delay/contamination delay

Copyright © 2005 Pearson Addison
-
Wesley. All rights reserved.

4
-
30

CMOS VLSI Design

Linear delay model, d = gh + p



d = f + p ;


propagation delay (d) =


effort delay (f) + parasitic delay (p)


f = g h


g : logical effort


h : electrical effort , or fan
-
out effort

Copyright © 2005 Pearson Addison
-
Wesley. All rights reserved.

4
-
31