Επαναπρογραμματιζόμενο Υλικό - Μνήμη - Σύστημα Επικοινωνίας

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13 Ιουλ 2012 (πριν από 4 χρόνια και 9 μήνες)

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Εξάμηνο

2009

∆ΙΑΛΕΞΗ
5:
Επαναπρογραμματιζόμενο

Υλικό



Μνήμη

Σύστημα

Επικοινωνίας
ΧΑΡΗΣ

ΘΕΟΧΑΡΙ∆ΗΣ
Λέκτορας

ΗΜΜΥ

(ttheocharides@ucy.ac.cy)
Slides adopted from Prof. Peter Marwedel

and Shih-Hao

Hung
and textbook:
Embedded Systems Design: A Unified hardware/software Introduction
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“Traditional”

Software Embedded Systems = CPU + RTOS
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Generic Architecture
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“Traditional”

Hardware Embedded Systems =
ASIC
ASIC Features
Area: 4.6 mm x 5.1 mm
Speed: 20 MHz @ 10 Mcps
Technology: HP 0.5 μm
Power: 16 mW - 120 mW (mode
dependent) @ 20 MHz, 3.3 V
Avg. Acquisition Time: 10 μs to 300 μs
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Modern Embedded Systems?

Embedded systems employ a combination of

application-specific h/w (boards, ASICs, FPGAs etc.)
- performance, low power

s/w on prog. processors: DSPs, μcontrollers etc.
- flexibility, complexity

mechanical transducers and actuators
Application
Specific Gates
Processor
Cores
Analog
I/O
Memory
DSP
Code
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Complexity and Heterogeneity

Heterogeneity within H/W & S/W parts as well

S/W: control oriented, DSP oriented

H/W: ASICs, COTS ICs
μcontroller
control panel
Real-time
OS
controller
processes
UI
processes
ASIC
Programmable
DSP
Programmable
DSP
DSP
Assembly
Code
DSP
Assembly
Code
Dual-ported
RAM
CODEC
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Increasingly on the Same Chip

System-on-Chip (SoC)

SC3001 DIRAC chip (Sirius Communications)
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More SoCs
Camera-on-chip (Bell Labs)
Solar-power Wireless Sensor (Berkeley)
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SoCs with Mechanics: Berkeley’s Smart Dust
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Trade-off: Hardware vs. Software

Hardware = functionality implemented via a custom architecture (e.g.
datapath + FSM)

Software = functionality implemented in software on a programmable
processor

Key differences:

Multiplexing
- software modules multiplexed with others on a processor
– e.g. using an OS
- hardware modules are typically mapped individually on dedicated hardware

Concurrency
- processors usually have one “thread of control”
- dedicated hardware often has concurrent datapaths
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Many Implementation Choices

Microprocessors

Domain-specific processors

DSP

Network processors

Microcontrollers

ASIPs

Reconfigurable SoC

FPGA

Gatearray

ASIC
SpeedPower
Cost
High Low
Volume
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Architectural Choices
Source: Kastner (UCSB)
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Many Types of Programmable Processors

Past

Microprocessor

Microcontroller

DSP

Graphics
Processor

Now / Future

Network Processor

Sensor Processor

Cryptoprocessor

Game Processor

Wearable Processor

Mobile Processor
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General Purpose Microprocessors

Programmable device used in a variety of
applications

Also known as “microprocessor”

Features

Program memory

General datapathwith large register file
and general ALU

User benefits

Low time-to-market and NRE costs

High flexibility
Source: Vahid/ Givargix
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Application-Specific Instruction Processors
(ASIPs)

Processors with instruction-sets tailored to specific applications or
application domains
- instruction-set generation as part of synthesis
- e.g. Tensilica

Pros:
- customization yields lower area, power etc.

Cons:
- higher h/w & s/w development overhead
» design, compilers, debuggers
» higher time to market
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Reconfigurable Devices
Triscend’s

A7 CSoC
Other Examples
Atmel’s FPSLIC
(AVR + FPGA)
Altera’s

Nios
(configurable
RISC on a PLD)
Xilinx’s Virtex
(multiple RISC
cores, distributed
DRAM, FPGA)
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ASICs

Digital circuit designed to execute one
program

Features

Contains only the components needed to
execute a single program

No program memory

Benefits

Fast

Low power

Small size
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ASIC Design

Extremely complex task

Must manage close to one billion transistors

This continues to exponentially increase

Transistors are smaller, but much more complicated
- Leakage current
- Interconnect coupling

Must perform required task(s)

Applications expect complicated tasks to be done in hardware

Mix of hardware and software components

Users continually demand better products

Lower power, longer battery, smaller, faster, …
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H/W-S/W Architecture

A significant part of the problem is deciding which parts shouldbe in
s/w on programmable processors, and which in specialized h/w

Today:

Ad hoc approaches based on earlier experience with similar products, &
on manual design

H/W-S/W partitioning decided at the beginning, and then designs
proceed separately
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Embedded System Design

CAD tools take care of h/w fairly well

Although a productivity gap emerging

But, S/W is a different story…

HLLssuch as C help, but can’t cope with complexity and
performance constraints
Holy Grail for Tools People: H/W-like synthesis & verification from a
behavior description of the whole system at a high level of abstraction
using formal computation models
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Embedded System Design from a Design
Technology Perspective

Intertwined subtasks

Specification/modeling

H/W & S/W partitioning

Scheduling & resource allocations

H/W & S/W implementation

Verification & debugging

Crucial is the co-design and joint
optimization of hardware and software
Processor
Analog I/O
Memory
ASIC
DSP
Code
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Embedded System Design Flow

Modeling

the system to be designed, and experimenting with
algorithms involved;

Refining (or “partitioning”)

the function to be implemented into smaller,
interacting pieces;

HW-SW partitioning: Allocating

elements in the refined model to either (1) HW units,
or (2) SW running on custom hardware or a suitable
programmable processor.

Scheduling

the times at which the functions are executed. This is
important when several modules in the partition share
a single hardware unit.

Mapping (Implementing)

a functional description into (1) software that runs on
a processor or (2) a collection of custom, semi-
custom, or commodity HW.
Processor
Analog I/O
Memory
ASIC
Environ
-ment
DSP
Code
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Reconfigurable Logic
Full custom chips may be too expensive, software too slow.
Combine the speed of HW with the flexibility of SW

HW with programmable functions and interconnect.

Use of configurable hardware;
common form: field programmable gate arrays (FPGAs)
Applications: bit-oriented algorithms like

encryption,

fast “object recognition“(medical and military)

Adapting mobile phones to different standards.
Very popular devices from

XILINX (XILINX Vertex II are recent devices)

Actel, Altera and others
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Energy Efficiency of FPGAs
Courtesy: Philips
©Hugo De Man, IMEC, 2007
GOPs/J
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Floor-plan

of VIRTEX II FPGAs
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Virtex II Configurable Logic Block (CLB)
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Virtex II Slice (simplified)
Look-up tables LUT F and G can be used to
compute any Boolean function of ≤

4 variables.
abcdG
00000
00011
00101
00110
01001
01010
01100
01111
10001
10010
10100
10111
11000
11011
11101
11110
Example:
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Virtex II
(Pro) Slice
[© and source: Xilinx Inc.:
Virtex-II Pro™ Platform
FPGAs: Functional
Description, Sept. 2002,
//www.xilinx.com]
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Number of resources

available in Virtex II Pro devices
[© and source: Xilinx Inc.: Virtex-II Pro™ Platform FPGAs:
Functional Description, Sept. 2002, //www.xilinx.com]
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Interconnect

Hierarchical Routing Resources
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Virtex II Pro Devices
include

up to 4 PowerPC
processor cores
[© and source: Xilinx Inc.: Virtex-II Pro™ Platform
FPGAs: Functional Description, Sept. 2002,
//www.xilinx.com]
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Memory

For the memory, efficiency is again a concern:

speed (latency and throughput); predictable timing

energy efficiency

size

cost

other attributes (volatile vs. persistent, etc)

Memories?

Oops!
Memories!
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Access times and energy consumption
increases with the size of the memory
Example (CACTI Model):
"Currently, the size of
some applications is
doubling every 10
months"
[STMicroelectronics,
Medea+ Workshop,
Stuttgart, Nov. 2003]
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Access times and energy consumption

for multi-ported register files
Rixner’set al. model [HPCA’00], Technology of 0.18 μm
Cycle Time (ns)
Area (λ2x106)
Power (W)
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
163264128
Register File Size
0
1
2
3
4
5
6
7
163264128
GP6M2
GP6M3
0
2
4
6
8
10
12
14
163264128
Register File Size
Source and ©H. Valero, 2001
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How much of the energy consumption of
a system is memory-related?
Mobile PC
Thermal Design (TDP) System Power
Note: Based on Actual Measurements
600/500 MHz uP
37%
LCD 10"
19%
HDD
9%
Memory+Graphics
12%
Power Supply
10%
Other
13%
Mobile PC
Average System Power
600/500 MHz uP
13%
LCD 10"
30%
HDD
19%
Memory+Graphics
15%
Power Supply
10%
Other
13%
CPU Dominates Thermal
Design Power
Multiple Platform
Components Comprise
Average Power
[Courtesy: N. Dutt; Source: V. Tiwari]
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Energy consumption in mobile devices
[O. Vargas (Infineon Technologies): Minimum power consumption inmobile-phone memory subsystems; Pennwell
Portable Design -September 2005;] Thanks to Thorsten Koch (Nokia/ Univ. Dortmund) for providing this source.
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Access-times will be a problem
Speed gap between processing and main DRAM increases
2
4
8
24
5
Performance
years
CPU (1.5-
2 p.a
.)
DRAM (1.07 p.a.)
31
early 60ties (Atlas):
page fault ~ 2500 instructions
2002 (2 GHz µP):
access to DRAM ~ 500
instructions
penalty for cache miss about
same as for page fault in Atlas
Similar problems for PCs and
MPSoCs
[P. Machanik: Approaches to Addressing the
Memory Wall, TR Nov. 2002, U. Brisbane]


2x
every 2
years
1
0
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Hierarchical memories

using scratch pad memories (SPM)

Address
space
ARM7TDMI
cores, well-
known for
low power
consumption
scratch pad memory
0
FFF..
main
SPM
processor
Hierarchy
Hierarchy
Example
Example
no tag memory
SPM
select
Selection is by an
appropriate address
decoder (simple!)
SPM is a small,
physically separate
memory mapped
into the address
space
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Comparison of currents using measurements
E.g.: ATMEL board with
ARM7TDMI and
ext. SRAM
Current
32 Bit-Load Instruction (Thumb)
48,2
50,9
44,4
53,1
116
77,2
82,2
1,16
0
50
100
150
200
Prog Main/ Data
Main
Prog Main/ Data
SPM
Prog SPM/ Data
Main
Prog SPM/ Data SPM
mA
Core+SPM (mA)
Main Memory Current (mA)
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Why not just use a cache ? (1)
0
1
2
3
4
5
6
7
8
9
256512102420484096819216384
memory size
Energy per access [nJ] .
Scratch pad
Cache, 2way, 4GB space
Cache, 2way, 16 MB space
Cache, 2way, 1 MB space
[R. Banakar, S. Steinke, B.-S. Lee, 2001]
2. Energy for parallel access of sets, in comparators, muxes.
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Influence of the associativity
Parameters different from
previous slides
[P. Marwedel et al., ASPDAC, 2004]
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Communication
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Communication
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Communication:

Hierarchy

Inverse relation between volume and urgency quite
common:
Sensor/actuator busses
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Communication

-

Requirements -

Real-time behavior

Efficient, economical
(e.g. centralized power supply)

Appropriate bandwidth and communication delay

Robustness

Fault tolerance

Maintainability

Diagnosability

Security

Safety
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Basic techniques:Electrical

robustness

Single-ended vs. differential
signals
Voltage at input of Op-Amp positive →'1'; otherwise →'0'
Combined with twisted pairs; Most noise added to both wires.
ground
Local ground
Local ground
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Evaluation

Advantages:

Subtraction removes most of the noise

Changes of voltage levels have no effect

Reduced importance of ground wiring

Higher speed

Disadvantages:

Requires negative voltages

Increased number of wires and connectors

Applications:

USB, FireWire, ISDN

Ethernet (STP/UTP CAT 5 cables)

differential SCSI

High-quality analog audio signals
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Real-time behavior
Carrier-sense multiple-access/collision-detection
(CSMA/CD, Standard Ethernet) no guaranteed response time.
Alternatives:

token rings, token busses

Carrier-sense multiple-access/collision-avoidance (CSMA/CA)
- WLAN techniques with request preceding transmission
- Each partner gets an ID (priority). After each bus transfer, all partners try
setting their ID on the bus; partners detecting higher ID disconnect
themselves from the bus. Highest priority partner gets guaranteed response
time; others only if they are given a chance.
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Other basic techniques

Fault tolerance:
error detecting and error correcting bus protocols

Privacy:
encryption, virtually private networks
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Sensor/actuator busses
1.

Sensor/actuator busses: Real-time behavior very
important; different techniques:
Many wires less wires expensive & flexible
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Field busses: Profibus
More powerful/expensive than sensor interfaces; mostly
serial. Emphasis on transmission of small number of bytes.
Examples:
1.

Process Field Bus (Profibus)
Designed for factory and process automation.
Focus on safety; comprehensive protocol mechanisms.
Claiming 20% market share for field busses.
Token passing.
≦93.75 kbit/s (1200 m);1500 kbits/s (200m);
12 Mbit/s (100m)
Integration with Ethernet via Profinet.
[http://www.profibus.com/]
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Controller area network (CAN)
2. Controller area network (CAN)

Designed by Bosch and Intel in 1981;

used in cars and other equipment;

differential signaling with twisted pairs,

arbitration using CSMA/CA,

throughput between 10kbit/s and 1 Mbit/s,

low and high-priority signals,

maximum latency of 134 µs for high priority signals,

coding of signals similar to that of serial (RS-232) lines of PCs, with
modifications for differential signaling.

See //www.can.bosch.com
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Time-Triggered-Protocol (TTP)
3.
The Time-Triggered-Protocol (TTP) [Kopetz et al.]
for fault-tolerant safety systems like airbags in cars.
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FlexRay
4.

FlexRay: developed by the FlexRay consortium
(BMW, Ford, Bosch, DaimlerChrysler, …)
Combination of a variant of the TTP and the Byteflight [Byteflight
Consortium, 2003] protocol.
Specified in SDL.
- Improved error tolerance and time-determinism
- Meets requirements with transfer rates >> CAN std.
High data rate can be achieved:
– initially targeted for ~ 10Mbit/sec;
– design allows much higher data rates
- TDMA (Time Division Multiple Access) protocol:
Fixed time slot with exclusive access to the bus
- Cycle subdivided into a static and a dynamic segment.
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http://www.computer.org/micro/mi2002/pdf/m4010.pdf
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Other field busses

LIN

MAP:MAP is a bus designed for car factories.

EIB:The European Installation Bus (EIB) is a bus designed for
smart homes. European Installation Bus (EIB)
Designed for smart buildings; CSMA/CA; low data rate.

IEEE 488: Designed for laboratory equipment.

Attempts to use standard Ethernet.
However, timing predictability remains a serious issue.
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Wireless communication
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Wireless communication: Examples

IEEE 802.11 a/b/g/n

UMTS

DECT

Bluetooth

ZigBee
Timing predictability of wireless communication?
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Summary

FPGAs

Memories
- “Small is beautiful”
(in terms of energy consumption, access times, size)

Communication structures