Lecture 2: Basic Fabrication Steps and

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VLSI Design

Lecture 2: Basic Fabrication Steps and
Layout

Mohammad
Arjomand


CE Department

Sharif Univ. of Tech.


Adapted with modifications from Harris’s lecture notes


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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2

of 50

Outline


How to make a transistor or a gate


Cross
-
section


Top view (masks)


Fabrication process


Layout


Design rules


Standard
c
ell
l
ayouts


Stick Diagrams


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Our technology


We will study a generic 180 nm technology (SCMOS
rules).


Assume 1.2V supply voltage.


Parameters are typical values.


Parameter sets/Spice models are often available for 180
nm, harder to find for 90 nm.

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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4

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Fabrication services


Educational services:


U.S.: MOSIS (has defined SCMOS rules)


EC:
EuroPractice


Taiwan: CIC


Japan: VDEC


Foundry = fabrication line for hire.


Foundries are major source of
fab

capacity today.

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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5

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Silicon Lattice


Transistors are built on a silicon substrate


Silicon is a Group IV material


Forms crystal lattice with bonds to four neighbors

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Dopants


Silicon is a semiconductor


Pure silicon has no free carriers and conducts poorly


Adding
dopants

increases the conductivity


Group V
(Arsenic, Phosphorus)
: extra electron (n
-
type)


Group III
(Boron)
: missing electron, called hole (p
-
type)

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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7

of 50

p
-
n

Junctions


A junction between p
-
type and n
-
type semiconductor
forms a diode.


Current flows only in one direction


N
-
Diff


P
-
Diff


anode

cathode

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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of 50

Fabrication processes


IC built on silicon substrate:


some structures diffused into substrate;


other structures built on top of substrate.


Substrate regions are doped with n
-
type and p
-
type
impurities. (n+ = heavily doped)


Wires made of polycrystalline silicon (poly), multiple
layers of aluminum (metal).


Silicon dioxide (SiO
2
) is insulator.

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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9

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CMOS Fabrication


CMOS transistors are fabricated on silicon wafer


Lithography process similar to printing press


On each step, different materials are deposited or
etched


Easiest to understand by viewing both top and cross
-
section of wafer in a simplified manufacturing process

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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of 50

CMOS Inverter

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Inverter Cross
-
section


Typically use p
-
type substrate for nMOS transistors


Requires n
-
well for body of pMOS transistors

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Well and Substrate Taps


Substrate must be tied to GND and n
-
well to V
DD


Metal to lightly
-
doped semiconductor forms poor
connection called Shottky Diode


Use heavily doped well and substrate contacts / taps

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Inverter Mask Set


Transistors and wires are defined by
masks


Cross
-
section taken along dashed line

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Detailed Mask Views


Six masks


n
-
well


Polysilicon


n+ diffusion


p+ diffusion


Contact


Metal

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Fabrication Steps


Start with blank wafer


Build inverter from the bottom up


First step will be to form the n
-
well


Cover wafer with protective layer of SiO
2

(oxide)


Remove layer where n
-
well should be built


Implant or diffuse n dopants into exposed wafer


Strip off SiO
2

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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of 50

Oxidation


Grow SiO
2

on top of Si wafer


900


1200 C with H
2
O or O
2

in oxidation furnace

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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17

of 50

Photoresist


Spin on photoresist


Photoresist is a light
-
sensitive organic polymer


Softens where exposed to light

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Lithography


Expose photoresist through n
-
well mask


Strip off exposed photoresist

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Etch


Etch oxide with hydrofluoric acid (HF)


Seeps through skin and eats bone; nasty stuff!!!


Only attacks oxide where resist has been exposed

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Strip Photoresist


Strip off remaining photoresist


Use mixture of acids called piranah etch


Necessary so resist doesn’t melt in next step

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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n
-
well


n
-
well is formed with diffusion or ion implantation


Diffusion


Place wafer in furnace with arsenic gas


Heat until As atoms diffuse into exposed Si


Ion Implanatation


Blast wafer with beam of As ions


Ions blocked by SiO
2
, only enter exposed Si

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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of 50

Strip Oxide


Strip off the remaining oxide using HF


Back to bare wafer with n
-
well


Subsequent steps involve similar series of steps

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Polysilicon


Deposit very thin layer of gate oxide


< 20
Å

(6
-
7 atomic layers)


Chemical Vapor Deposition (CVD) of silicon layer


Place wafer in furnace with Silane gas (SiH
4
)


Forms many small crystals called polysilicon


Heavily doped to be good conductor


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Polysilicon Patterning


Use same lithography process to pattern polysilicon


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Self
-
Aligned Process


Use oxide and masking to expose where n+ dopants
should be diffused or implanted


N
-
diffusion forms nMOS source, drain, and n
-
well
contact


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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N
-
diffusion


Pattern oxide and form n+ regions


Self
-
aligned process

where gate blocks diffusion


Polysilicon is better than metal for self
-
aligned gates
because it doesn’t melt during later processing

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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N
-
diffusion cont.


Historically dopants were diffused


Usually ion implantation today


But regions are still called diffusion


Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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N
-
diffusion cont.


Strip off oxide to complete patterning step

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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P
-
Diffusion


Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Contacts


Now we need to wire together the devices


Cover chip with thick field oxide


Etch oxide where contact cuts are needed

Modern VLSI Design 4e: Chapter
2

Sharif University of Technology

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Metalization


Sputter on aluminum over whole wafer


Pattern to remove excess metal, leaving wires


Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Simple cross section

substrate

n+

n+

p+

substrate

metal1

poly

SiO
2

metal2

metal3

transistor

via

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Photolithography

Mask patterns are put on wafer using photo
-
sensitive
material:

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Process steps


First place tubs (wells) to provide properly
-
doped
substrate for n
-
type, p
-
type transistors.


a twin
-
tub process:

p
-
tub

n
-
tub

substrate

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Process steps, cont’d.

Pattern polysilicon before diffusion regions:

p
-
tub

n
-
tub

poly

poly

gate oxide

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Process steps, cont’d

Add diffusions, performing self
-
masking:

p
-
tub

n
-
tub

poly

poly

n+

n+

p+

p+

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Process steps, cont’d

Start adding metal layers:

p
-
tub

n
-
tub

poly

poly

n+

n+

p+

p+

metal 1

metal 1

vias

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Transistor structure

n
-
type transistor:

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

0.25 micron transistor (Bell Labs)

poly

silicide

source/drain

gate oxide

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Transistor layout

n
-
type (tubs may vary):

w

L

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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NMOS Transistor


Four terminals: gate, source, drain, body


Gate


oxide


body stack looks like a capacitor


Gate and body are conductors


SiO
2

(oxide) is a very good insulator


Called metal


oxide


semiconductor (MOS) capacitor

»
Even though gate is

no longer made of metal

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

NMOS Operation


Body is commonly tied to ground (0 V)


When the gate is at a low voltage:


P
-
type body is at low voltage


Source
-
body and drain
-
body diodes are OFF


No current flows, transistor is OFF

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

NMOS Operation (cont’d.)


When the gate is at a high voltage:


Positive charge on gate of MOS capacitor


Negative charge attracted to body


Inverts a channel under gate to n
-
type


Now current can flow through n
-
type silicon from source
through channel to drain, transistor is ON

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

PMOS Transistor


Similar, but doping and voltages reversed


Body tied to high voltage (V
DD
)


Gate low: transistor ON


Gate high: transistor OFF


Bubble indicates inverted behavior

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Drain current characteristics

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Drain current


Linear region (
V
ds

<
V
gs

-

V
t
):


I
d

= k’ (W/L)[(
V
gs

-

V
t
)
V
ds

-

0.5

V
ds
2
]


Saturation region (
V
ds



V
gs

-

V
t
):


I
d

= 0.5k’ (W/L)(
V
gs

-

V
t
)
2

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

180 nm transconductances

Typical values:


n
-
type:


k
n
’ = 170

A/V
2


V
tn

= 0.5 V


p
-
type:


k
p
’ = 30

A/V
2


V
tp

=
-
0.5 V

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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48

of 32

Current through a transistor

Use 180 nm parameters. Let W/L = 3/2. Measure at
boundary between linear and saturation regions.


V
gs

= 0.7V:

I
d

= 0.5k’(W/L)(
V
gs
-
V
t
)
2
=
0.5(170

A/V
2
)(3/2)(0.7
-
0.5)
2

= 5.1

A


V
gs

= 1.2V:

I
d

= 62

A

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Basic transistor parasitics


Gate to substrate, also gate to source/drain.


Source/drain capacitance, resistance.

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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Basic transistor parasitics, cont’d


Gate capacitance C
g
. Determined by active area.


Source/drain overlap capacitances C
gs
, C
gd
.
Determined by source/gate and drain/gate overlaps.
Independent of transistor L.


C
gs

= C
ol

W


Gate/bulk overlap capacitance.

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Latch
-
up


CMOS ICs have parastic silicon
-
controlled rectifiers
(SCRs).


When powered up, SCRs can turn on, creating low
-
resistance path from power to ground. Current can
destroy chip.


Early CMOS problem. Can be solved with proper
circuit/layout structures.

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Parasitic SCR structure


There exist parasitic bipolar transistors (
pnp

and
npn
) in a CMOS
structure.


Additionally, the well and substrate have resistances R
W

and R
S
,
respectively.

n+

p substrate

p+

A

Y

GND

V

DD

n+

p+

substrate tap

well tap

n+

p+

n well

R

sub

R

well

V

sub

V

well

Twin tub

n tub

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Parasitic SCR

circuit

I
-
V behavior

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Solution to latch
-
up

Use tub ties to connect tub to power rail. Use enough to
create low
-
voltage connection.

Modern VLSI Design 4e: Chapter 2

Sharif University of Technology

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of 32

Tub tie layout

metal (V
DD
)

p
-
tub

p+