MCU core - Electrical, Electronic and Computer Engineering

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Electrical, Electronic & Computer Engineering


EMK310 Application


Lecture 8

Introduction
to PIC32

Prac

3


Prof. Tania
Hanekom



References:


PIC32MX1XX/2XX
Family Data Sheet


PIC32 Family Reference Manual


Programming 32
-
bit Microcontrollers in C

Electrical, Electronic & Computer Engineering


PIC32 sample


PIC32MX220F032B
-
I


Datasheet:
PIC32MX1XX/2XX Family Data Sheet


Reference manual:
PIC32 family reference manual

Electrical, Electronic & Computer Engineering


Pin diagram

Datasheet

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Device features


CTMU = Charge Time Measurement Unit


RTCC = Real Time Clock Calendar


PMP = Parallel Master Port

Datasheet

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Device block diagram

Datasheet

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Device structure


PIC32MX architecture functional blocks:


MCU Core

Datasheet

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Core block diagram


MIPS16e Support


Multiply/Divide Unit (MDU
)


Dual
Internal Bus interfaces


System Control Coprocessor (CP0)


Fixed Mapping Translation (FMT)


Power Management


Enhanced JTAG (EJTAG) Controller

Datasheet

Electrical, Electronic & Computer Engineering


MIPS architecture



32
-
bit RISC MIPS32 M4K Core


MIPS (Microprocessor without Interlocked
Pipeline

Stages)


RISC instruction set architecture developed by MIPS Computer
Systems

MIPS architecture
-

Wikipedia, the free
encyclopedia

Electrical, Electronic & Computer Engineering


MIPS architecture

Pipelining


CPUs built up from number of dedicated sub
-
units, e.g.
instruction decoders, ALUs (for integer
arithmetics

and logic),
load/store units (handling memory).


Execution of instructions pass data from one to the next.


Traditional non
-
optimized design:

a particular instruction in a
program sequence must be (almost) completed before the next
can be issued for execution


Pipelined architecture:

successive instructions can overlap in
execution, e.g., at the same time a math instruction is fed into
the floating point unit, the load/store unit can fetch the next
instruction.


MIPS architecture
-

Wikipedia, the free encyclopaedia

Electrical, Electronic & Computer Engineering


MIPS architecture

Pipelining (2)


Barrier to pipelining: some instructions (e.g. division) take longer
to complete; CPU has to wait before passing next instruction
into pipeline.


One solution: series of interlocks that allows stages to indicate
that they are busy, pausing the other stages upstream.


Interlocks: major performance barrier since they have to
communicate to all the modules in the CPU which takes time


MIPS design: fit every sub
-
phase, including cache
-
access, of all
instructions into one cycle, thereby removing any needs for
interlocking, and permitting a single cycle throughput.

MIPS architecture
-

Wikipedia, the free encyclopaedia

Electrical, Electronic & Computer Engineering


MIPS Architecture

PIC32 MCU core pipeline


5
-
Stage Pipeline


Instruction (I ) Stage


instruction is fetched


Execution (E) Stage


Operands are fetched


ALU begins arithmetic or
logical operation


Memory (M) Stage


ALU operation completes


data SRAM access performed


Align (A) Stage


separate aligner aligns loaded
data with its word boundary


http://en.wikipedia.org/wiki/Da
ta_structure_alignment


Writeback

(W) Stage


result is written back to the
register file


PIC32 Family reference manual Section 2

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MIPS architecture

Subroutine calls



Another difference between MIPS & RISC: handling
of subroutine calls


RISC uses "register windows"


hardware implementation limits the maximum depth of multi
-
level calls


Each subroutine call requires its own set of registers =
required more real estate on the CPU + more complexity in
design


MIPS: compiler find free registers for subroutines


facilitated by increasing the number of registers


increases the performance of all tasks

MIPS architecture
-

Wikipedia, the free encyclopaedia

Electrical, Electronic & Computer Engineering


MCU core

Execution unit


Load
-
store architecture


values in memory must be brought into the register file
before they can be operated upon


Single
-
cycle ALU operations (logical, shift, add,
subtract)


Autonomous multiply/divide unit.


Datasheet

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MCU core

Buses & GPRs


32
-
bit Address and 32
-
bit Data Buses


One shadow set of 32
-
element, 32
-
bit General
Purpose Register Files


used for integer operations and address calculation


copy of the General Purpose Registers (GPR) for use by
high
-
priority interrupts = shadow register set


shadow set minimize context switching overhead during
interrupt/exception processing




Datasheet

Electrical, Electronic & Computer Engineering


MCU core

FMT


MIPS core uses
memory management unit
(MMU)


advanced features to allow separation of memory space dedicated
to application(s) from that of operating system


two distinct modes of operation:
user
and
kernel
.


PIC32 uses
Fixed Mapping Translation

(FMT) memory
management


MMU replaced by simpler FMT unit and a
bus matrix
(BMX) control
mechanism because embedded applications are less complex.


FMT allows PIC32 to conform to programming model used by all
other MIPS
-
based designs so that standardized address spaces
are used.


compatible scheme simplifies design of tools, applications and
porting of code to PIC32

Datasheet

Electrical, Electronic & Computer Engineering


MCU core

MDU


MDU

Multiply/Divide Unit


PIC32 contains separate pipeline for multiply and divide
operations.


Pipeline operates in parallel with integer unit (IU) pipeline


supports execution of one 16x16 or 32x16 multiply operation
every clock cycle; 32x32 multiply operations can be issued
every other clock cycle.


Divide operations implemented with 1 bit per clock iterative
algorithm.


Datasheet

Electrical, Electronic & Computer Engineering


MCU core:
CP0


System control
coprocessor
responsible for


the virtual
-
to
-
physical address translation


exception* control system


processor’s diagnostics capability


operating modes (Kernel, User and Debug)


whether interrupts are enabled or disabled.



* Exceptions on p. 36 of datasheet

Datasheet

Electrical, Electronic & Computer Engineering


MCU core

Instruction set


MIPS32® Compatible Instruction Set


MIPS16e™ Code Compression Instruction Set
Architecture Support


Refer to MIPS documents on module webpage

Datasheet

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Connection diagram

Datasheet

Homework for next lecture:

Build a demo circuit according to the
diagram on the right with


four LEDs connected to RB2 to RB5
so we can play with port I/O


a push
-
button switch connected to
INT0 so we can play with interrupts


a 10 k


potentiometer with terminals
connected to VDD and VSS and
wiper connected to AN0 so we can
play with the ADC.


PICkit

3 connection for programming
& debugging

TEST your circuit before coming to
class using the example provided.

Electrical, Electronic & Computer Engineering


How does MPLAB work for PIC32?


Same as for PIC18


Use PIC32 C compiler

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Practical 3

Motor control and
navigation



Motors
required for translation (i.e. to make the ARV drive in a
straight line) and rotation (i.e. to make the ARV turn).


Any
motors may be used.


The
code required to drive the motors must be developed from
first principles
.


One of two translation and rotation methods may be used:


one motor is used for translation (driving forward) and the
other for rotation (turning) of the ARV, or


two motors are used to separately drive the two front
wheels and the difference in rotation speed between two
motors is used to control translation and rotation.



Studyguide

Electrical, Electronic & Computer Engineering


Practical 3

Vehicle
construction


Design
and assemble a simple chassis with wheels (vehicle) and
install motors to drive this structure/vehicle.


Everything
besides the wheels, electronics and motors has to be
constructed from recycled materials.


The
vehicle may not be larger than 200 mm x 300 mm x 200
mm (W x H x L) and must use its own power source.

Studyguide