Dr.Vivek Kumar Sehgal

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20 Οκτ 2013 (πριν από 4 χρόνια και 18 μέρες)

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Dr.Vivek Kumar Sehgal




Contact

Information

Dr.VivekSehgal, Asst.

Professor

(Senior Grade)
.

Deptt. of
CSE & IT

Jaypee University of Information
Technology,

Waknaghat,

Solan, (H.P.)

Pin
-
173 234, INDIA.


Voice: +91
-
9418800200 (Mob
)


Voice: +91
-
1792
-
239358

(off)

E
-
mail:
vivekseh
@ieee.org,
vivekseh@acm.org


Education:




Ph.D.

(Computer Science and Engineering)

Uttarakhand Technical University, Dehradun, India
in (2007
-

2010).

Title: Stochastic Communication and Packets Flow Control in Networks
-
on
-
Chip.



M. Tech.

(Process Control)

NetajiSubhas Institute of Technology (NSIT),

(Formerly Delhi Institute of Technology
-

a division of Instrumentation & Control
Engine
ering, University of Delhi) in 2002.



B. Tech.

(Instrumentation Engineering)

SantLongowal Institute of Engineering Technology Longowal (Deemed University
Est. by Govt. of India) in 2000.


Research Interests:



Embedded Systems



Networks on Chip (NoC)



MEMS
(Power Generating IP in SoC)



On

C
hip Instrumentation


Research Interests:



Implementation of Graphene based Nano Wires as Horizontal Interconnect and
Multiwall Carbon Nano Tubes as vertical Interconnect in 3
-
D Networks

On
-
Chip:

According to ITRS 2005
predictions, the gap between interconnection delay and gate delay
will increase to 9:1 at the 65 nm technology. This is in sharp contrast to the 2:1 gap between
interconnection delay and gate delay at the 180 nm technology. This indicates that
communicatio
n, and not computation, will be the key performance bottleneck in DSM
technologies. In addition, total wire length on a chip is expected to amount to 2.22 km/cm
2

by
the year 2012. This productivity gap between fast devices and slow interconnects can be
red
uced by replacing the conventional interconnects with smart material interconnects or high
speed interconnects.




Fig. 17.1 Relative delay comparison of wires versus process technology

Carbon Nano Tubes for High Speed Vertical Interconnect

Franz Kreupl
@ all, briefly review the status of the application of carbon nanotubes (CNTs)
for future interconnects and present results concerning possible integration schemes. Growth
of single nanotubes at lithographically defined locations (vias) has been achieved w
hich is a
prerequisite for the use of CNTs as future interconnects. For the 20 nm node a current density
of 5·108 A/cm2 and a resistance of 7.8 kΩ could be achieved for a single multi
-
walled CNT
vertical interconnect.



Fig:

a different type of vertical interconnects [ref]. (a) Conventional Cu
-
via with voids at the bottom.

(b) Proposed replacement of the Cu
-
via by an array of CNTs.

(c) Proposed replacement of the Cu
-
via by a single MWCNT.


Graphene for High Speed Horizontal
Interconnect:

Graphene, the one
-
atom
-
thick gauze of carbon atoms resembling chicken wire

first isolated in
2004, continues to find new and wondrous applications. It has already been used to create
the

world’s smallest transistor

and now researchers at the
Georgia Institute of Technology
have experimentally demonstrated the potential for graphene to replace copper for
interconnects in future generations of integrated circuits.

Interconnects are tiny wires that are used to connect transistors and other device
s on
integrated circuits. As copper interconnects are made narrower and narrower, their resistivity
increases


nearly doubling as the interconnect sizes shrink to 30 nanometers. Interconnects at
a scale of 20 nanometers could happen in the next five years
, but since the increased
resistance of copper interconnects at that scale could offset performance increases, higher
density wouldn’t produce faster integrated circuits without other improvements.



Reduced

Order MEMS Design as IP for Heterogeneous Networ
ks
-
on
-
Chip

The involvement of MEMS in System
-
On
-
chip as one of the IP core rises more issues like
high power dissipation, conversion of pneumatic / hydraulic (micro fluid) signals in to the
communication data packets for on
-
chip actuating and controlling p
rocess. The complexities
of on chip interfaced MEMS make its analysis rather difficult and possibly a non desirable
task, mainly due to difficult economical and computational considerations involved. This


makes the use of reduced
-
order MEMS design, which
constitutes a good approximation of
full order control system. In this work we developed a method which preserves time domain
as well as the frequency domain characteristics of original high order MEMS.



Delay Estimation in Graphene Based Interconnects in N
etworks
-
On
-
Chip

Today’s SoCs are more complex as they can accommodate several hundred processors on a
single chip, due to this, on
-
chip wire delays have become more critical than gate delays and
recently synchronization problems between IPs are more appare
nt. Graphene based
interconnect is the best solution to reduce this productivity gap between gate delay and
interconnect delay. In this work the delay can be estimated by RLC modeling of interconnect
and Kalman estimation.

Research Profile
:

1.

Google Scholar:

http://scholar.google.co.in/citations?hl=en&user=Wf6KJJgAAAAJ&view_op=list_works&pagesize
=100

2.

DBLP:

http://www.informatik.uni
-
trier.de/~ley/pers/hd/s/Sehgal:Vivek_Kumar.html

3.

ACM:

http://dl.acm.
org/author_page.cfm?id=81339526886&coll=DL&dl=ACM&trk=0&cfid=256845427
&cftoken=97093137

4.

IEEE:

http://ieeexplore.ieee.org/search/searchresult.jsp?matchBoolean=true&newsearch=true&searc
hWithin=p_First_Names%3Avivek&searchWithin=p_Last_Names%3Asehgal

5.

Arnetminer:

http://arnetminer.org/person/vivek
-
kumar
-
sehgal
-
1119281.html

6.

Microsoft academic:

http://65.54.113.26/Author/3563854/vivek
-
kumar
-
sehgal





Research
Publications
:

Journals/Book Chapters:



Vivek Kumar Sehgal
, Durg Singh Chauhan, “State Observer Controller Design for
Packets Flow Control in Networks
-
on
-
Chip", The Journal of Supercomputing 54(3):
298
-
329 , 2010.




Vivek Kumar Sehgal
, "Stochastic communication in application specific networks
-
on
-
chip”. In Innovative algorithms and techniques in automation, industrial electronics and
telecommunication, Edited by TarekSobh, KhaledElleithy, AusifMahmood, Mohamed
Karim, ISBN: 978
-
1
-
4020
-
6265
-
0, pp10
-
17, Springer, 2007.




Vivek Kumar Sehgal
, “Reduced
-
O
rder Controller Design in Discrete Time Domain”,
Springer
-
Innovative Algorithms and Techniques in Automation, Industrial Electronics
and Telecommunications, Edited by TarekSobh, KhaledElleithy, AusifMahmood,
Mohamed Karim, ISBN: 978
-
1
-
4020
-
6265
-
0 pp 481
-
4
86, Springer, 2007.






Vivek Kumar Sehgal

and Nitin, “An Embedded Application for Driverless Metro
Train”, Lecture Notes in Electrical Engineering
-
28, Springer
-
Verlag, Volume 27, ISBN:
978
-
0
-
387
-
84813
-
6, pp. 1451
-
1457 , April 2009.




Vivek Kumar Sehgal
,
Nitin, and Durg Singh Chauhan, “Embedded Controller Based
Smart Card Access" Lecture Notes in Engineering and Computer Science, ISBN:
20780958 EIssn: 20780966, Vol. 2173 (1), pp. 863
-
868, 2008.




Pardeep Kumar,
Vivek Kumar Sehgal

, Durg Singh Chauhan, P. K
. Gupta and
ManojDiwakar,“Effective Ways of Secure, Private and Trusted Cloud Computing”,IJCSI
International Journal of Computer Science Issues, Vol. 8, Issue 3, No. 2, May 2011ISSN
(Online): 1694
-
0814




Pardeep Kumar,
Vivek Kumar Sehgal

and Durg Singh Chau
han. Article: Knowledge
Discovery in Databases (KDD) with Images: A Novel Approach toward Image Mining
and Processing.

International Journal of Computer Applications

27(6):10
-
13, August
2011. Published by Foundation of Computer Science, New York, USA.




Nit
in,
Vivek Kumar Sehgal
, Durg Singh Chauhan, MunishSood, and VikasHastir
“Image Based Authentication System with Sign
-
In Seal" Lecture Notes in Engineering
and Computer Science, ISBN: 20780958 EIssn: 20780966, Vol. 2173 (1), pp. 263
-
266,
2008.




Nitin,
Vivek

Kumar Sehgal

and Pawan Kumar Bansal, “On MTTF Analysis of a Fault
-
tolerant Hybrid MINs", WSEAS Transactions on Computer Research, ISSN 1991
-
8755,
Issue 2, Volume 2, pp. 130
-
138, 2007.




Nitin, Durg Singh Chauhan and
Vivek Kumar Sehgal
, “On a Software Archi
tecture of
JUIT
-
Image Based Authentication System" IAENG Transactions on Electrical and
Electronics Engineering, IEEE Computer Society Press, ISBN: 978
-
0
-
7695
-
3555
-
5, pp.
35
-
46 , 2009.




Nitin, Durg Singh Chauhan and
Vivek Kumar Sehgal
, “Two O(n2) time Faul
t
-
tolerant
Parallel Algorithm for Inter NoC communication in NiP”, Springer
-
Verlag, ISBN: 978
-
3
-
540
-
79186
-
7, pp. 267
-
282, Invited, May 2008.


Conferences/workshops:



Vivek Kumar Sehgal
, “Surveillance Through Automatic Signaling in Cloud
Computing” in 28th
International Conference on Computers and Their Applications
(CATA)



2013 , Hawaii, USA.





Vivek Kumar Sehgal
, Nitin, RachitKhanna, GauravGarg, NitikaSinghal “Modern
Control System Mapping on Networks
-
on
-
Chip”, ISMS 2012.



Vivek Kumar Sehgal
, MuditSinghal ,B
hartMangla, Sudeep Singh,
ShivangiKulshrestha


“An Embedded Interface for GSM Based Car Security System”,
CICSy 2012.



Pardeep Kumar,
Vivek Kumar Sehgal
, Nitin, Durg Singh Chauhan “Performance
Evaluation of Evolutionary and Artificial Neural Network based C
lassifiers in Diversity
of Data Sets” Iccsea


2012.



Pardeep Kumar,
Vivek Kumar Sehgal
, Nitin, Durg Singh Chauhan “Performance
Evaluation of Evolutionary andDecision Tree based Classifiers in Diversity ofData Sets”
CNC


2012



Pardeep Kumar, Nitin,
Vivek Kuma
r Sehgal
, D.S. Chauhan, “Selection of evolutionary
approach based hybrid data mining algorithms for decision support systems and business
intelligence”, in: Proceedings of the (ICACCI
-
2012), August 2012, in Press, ACM
proceedings



Vivek Kumar Sehgal
, Shubh
rangshu Naval, AbhinavGulharSayedJeeshan Ali and
MuditSinghal “An Embedded Platform for Patient Monitoring andCare System”, pp.
236
-
240, ESA 2011




PardeepKumar,Nitin, Vivek Kumar Sehgal and Durg Singh Chauhan “Clouds: Concept
to Optimize the Quality of Ser
vice (QOS) for Clusters”, WICT 2011.



Pardeep Kumar, Nitin,
Vivek Kumar Sehgal

and Durg Singh Chauhan“

Performance
Evaluation of Decision Tree versus Artificial Neural Network based Classifiers in
Diversity of Data Sets”, WICT 2011.




Pardeep Kumar, Nitin,
V
ivek Kumar Sehgal

and Durg Singh Chauhan “A Novel
Approach for Security in Cloud Computing using Hidden Markov Model and
Clustering”, WICT 2011.




Vivek Kumar Sehgal
, "An Embedded Platform for Intelligent Traffic Control," ems,
pp.541
-
545, 2010 UKSim Fourth

European Modelling Symposium on Computer
Modelling and Simulation, 2010.




Vivek Kumar Sehgal
, "Electronic Energy Meter with Instant Billing," ems, pp.27
-
31,
2010 UKSim Fourth European Modelling Symposium on Computer Modelling and
Simulation, 2010.



Vivek K
umar Sehgal
,
Sahil Jain
,
ShantanuAgarwal
,
UjjawalKhandelwal
,
Karan Jain
:
“Parameteric coding of speech signals” pp. 1
-
5,
ICUMT 2009
.




Vivek Kumar Sehgal
,
Rohit Sharma
,
NitinChanderwal
,
DeepankarBhardwaj
,
YarasAgarwal
,
MehboobShrivastava
,
PrashantSrivastava
,
Avinash Kumar

“D
-
Torus
Topology in Networks
-
on
-
Chip: A Perspective Study” pp. 163
-
168,
ESA 2009
.






Vivek Kumar Sehgal
,
Rohit Sharma
,
NitinChanderwal
,
AbhishekSrivastava
,
Anshul
Bora
: “Emergency Shutdown Procedure for Applications in Mass Rapid Transit System”
pp. 92
-
97,
ESA 2009
.




Rohit Sharma
,
NitinChanderwal
,
Viv
ek Kumar Sehgal
,
Amit Kumar
,
Preity Gupta
,
AshishNandanLal

“DELSIC: A Delay Simulator for Interconnect Circuits” pp. 52
-
56
C
DES 2009
.




Rohit Sharma,
Vivek Kumar Sehgal
, Nitin, ChandanBhardwaj, KanchakNegi, and
Tarun Kumar Thakur “An Intelligent Water Management and Distribution System”
IKE09, Las Vegas, USA, pp 66
-
70, 2009.




NitinChanderwal
,
GitanjaliChauhan
,
Vivek Kumar Sehgal
,
Rohit Sharma
,
Abhishek
Gupta
,
Aditya Patel
,
Amanpreet Singh Arora
,
Aprajita Gupta
,
UtkarshShrivastava
,
RajanVaish

“A Single Tape Deterministic Turing Machine of Adaptive Deterministic
Routing Algorithm Designed for Torus Network” pp. 37
-
40,
FCS
2009
.




NitinChanderwal
,
GitanjaliChauhan
,
Rohit Sharma
,
Vivek Kumar Sehgal
,
RohitVerma
,
Gaurav Kumar
,
UtkarshShrivastava
,
RajanVaish

“Single Tape Deterministic Turing
Machine of Routing Algorithms Designed for Torus Network” pp. 47
-
52,
FCS 2009
.




Vivek Kumar Sehgal, Durg Singh Chauhan, Nitin, Rohit Sharma and AnkitSrivastava

Obstacle Sensing and Anti
-
Falling Sensor Robot Using Embedded Processor
” pp.579
-
584 ,UKSim


2009.



Rohit Sharma,
Vivek Kumar Sehgal
, Nitin,
PranavBhasker
,

and
IshitaVerma

“Design
and Implementation of a 64
-
bit RISC Processor using VHDL” pp.568
-
573,UKSim


2009.



Nitin, Rohit Sharma,
Vivek Kumar Sehgal
” Asymptotic Analysis of Dynamic
Algorithms Designed to Provide Parallel Communication among NoC in NiP using
MIN” pp.443
-
448, UKSim


2009.



Rohit Sharma,
Vive
k Kumar Sehgal
,

Nitin, Abhinav Thakur, Adnan Munir Khan,
Ashish Sharma, and Pankaj Sharma, “Peltier effect based Solar Powered Airconditioning
System”, (CSSim
-
EUROSIM/CSSS), Brno, Czech Republic, 2009.



Vivek Kumar Sehgal
,

Nitin, Durg Singh Chauhan and Roh
it Sharma, “Smart Wireless
Temperature Data Logger using IEEE 802.15.4/ZigBee Protocol”, IEEE TENCON 2008,
INDIA, pp.1
-
6, 2008.



Nitin ,
Vivek Kumar Sehgal
, Durg Singh Chauhan, and Rohit Sharma, “Modified Fault
tolerant Combining Switches Multistage Intercon
nection Networks with Chaining:
Algorithm, Design and Cost Issues” IEEE TENCON 2008, INDIA.



Rohit Sharma ,
Vivek Kumar Sehgal
, Nitin, and Durg Singh Chauhan, “Closed
-
form
Expressions for Extraction of Capacitances in Multilayer VLSI Interconnects” IEEE
TE
NCON 2008, INDIA





Vivek Kumar Sehgal
, Nitin, and DurgSingh.Chauhan, “A New Approach for Inter
Networks

on

Chip Communication in Networks

in

Package” ESA08, Las Vegas, USA,
pp 16
-
23, 2008.



Vivek Kumar Sehgal
, Durg Singh Chauhan, Nitin, AbhishekShreevats, Ank
itKhare,
Sunny Kapoor, Avishek Gupta and AbhishekMisra, “Optimal Dynamic Routing and
Flow Control in Interconnection Networks
-
on
-
Chip”ESA08, Las Vegas, USA, pp 193
-
199, 2008.



Vivek Kumar Sehgal
, Nitin, Rohit Sharma, VikasHastir,

Yogeshwar Singh Dadwhal,
Mi
teshBansal, RohitPuri, ShreyAbhiPathania, and Abhay Thakur, “Smart Wireless
Temperature Data Logger”ESA08, Las Vegas, USA, pp 140
-
144, 2008.



Rohit Sharma,
Vivek Kumar Sehgal
, Nitin, MunishSood,

PuneetDhawan, Anupam
Prasad, ManasSrivastava and AyushiAgarwal
, “An Embedded Platform For
GSM/CDMA Controlled Surveillance Robot”ESA08, Las Vegas, USA, pp 145
-
150,
2008.




Rohit Sharma,
Vivek Kumar Sehgal
, Nitin, SomyaRawat, VinodiniKapoor, and Sonia
Chadha, “Time
-
Domain Analysis of VLSI Interconnects Considering Osci
llatory
Inputs”CDES08, Las Vegas, USA, pp 57
-
60, 2008.



Nitin, Rohit Sharma,
Vivek Kumar Sehgal
, ShrutiGarhwal, NehaSrivastava and Kumar
Vaibhav, “CSMIN Revisited: Accurate Algorithms and Strategic Design
Issues”PDPTA08, Las Vegas, USA, pp 218
-
223, 2008.



Ni
tin, Durg Singh Chauhan,
Vivek Kumar Sehgal
, SohitAhuja, Pallavi Singh and
AnkitMahanot,”Security Analysis and Implementation of *JUIT IBA System using
Kerberos Protocol”, IEEE/ACIS, USA, pp 575
-
580, 2008.



Nitin, Durg Singh Chauhan,
Vivek Kumar Sehgal
,
ManishaRana, UtkarshShrivastava,
AnkitMahanot, Pallavi Singh and SohitAhuja.” Finite State Modeling and Testing of
Image Based Authentication System” , IEEE/ACIS, USA, pp 427
-
432, 2008.



Nitin,
Vivek Kumar Sehgal
, Nakul Sharma, Kunal Krishna and Abhishek B
hatia, “On
Path
-
length and Routing
-
tag Algorithm for Hybrid Irregular Multi
-
stage Interconnection
Networks”, Proceedings of 8th ACIS (SNPD), Qingdao, CHINA, IEEE Computer
Society Press, pp. 652
-
657, July 30
-
August 1, 2007.




Vivek Kumar Sehgal
, Nitin, Amit
Jain, Neeraj Shah, SachinGarg, and Sumit Gupta,
“RJ
-
11 Interfaced Embedded Platform for DTMF Based Remote Control System”
ESA07, Las Vegas, USA, pp 239
-
244, 2007.


Teaching:



Advanced Computer Architecture (UG)



Signals and Systems (UG)



Digital Electronics
Design (UG)



Control System (PG)



Digital Hardware Design using SystemC (PG)



Embedded

Systems (UG, PG)





System on Chips using ARM Processors (PG)



Microprocessor and Interfacing (UG
)

Ph.D. Supervision
:

1.

Pradeep Kumar in the field of Data Mining.
-

Completed

Topic :
-

Linear, Hybrid and Parallel Classification Models in Diversity of Data sets.

2.

DhirendraYadav in
Mobile Security on Android Platform.

Honors and awards
:



Young Scientist Scholarship Award 2009 from Department of Science and
Technology (D
ST), SERC Division, Government of India, New Delhi.



Appointed as Vice President for INTERNATIONAL ACCREDITATION
ORGANIZATION
www.iao.org/
.



Invited to Conduct and Chair two day Workshop, IEEE SDR
-
GCC 2010:
International Workshop

on Scalable Distributed Research for Grids, Clusters and
Clouds, Moscow, Russia, 2010.



Identified as a Leader in Engineering Education and selected to participate in the
IUCEE 2010 Indo
-
US Faculty Leadership Institute, JUIT, July 12
-
16, 2010.



Ministry of
Human Resource Development (MHRD) Scholarship during M.Tech.



Qualified Graduate Aptitude Test of Engineering (GATE
-

Instrumentation
Engineering) in 2000.



National Cadets Core
-

A, B, & C certificate holder.



First Doctoral Graduate of Uttarakhand Technical

University, in the field of Computer
Science and Engineering.



B.Tech. (Instrumentation Engineering) with Honors.

Visiting Professor at Uttarakhand Technical University, 2010
-
Present.


Professional Membership:



IEEE



ACM



SIAM



IAENG

Committee Member:



Program
Committee Member in

First International Conference on Intelligent Systems in
the

Middle East (ISME2013).



Program Committee Member in


First International Conference on Systems Informatics,
Modelling and Simulation (SIMS 2013).



Program Committee Member in

IEEE Business Engineering and Industrial Applications
Colloquium 2013.





Program Committee Member in
Second International Symposium on Intelligent
Informatics (ISI'13)



Program Committee Member in 2
nd

International conference on Intelligent System,
Modeling
and Simulation (ISMS 2012) Malaysia.



Program Committee Member in 1st International Conference on. Signal Processing,
Computing and Control ISPCC
-

2012



Program Committee Member in 3
rd
International Conference on Computational
Intelligence, Communication Sy
stems and Networks (CICSyN 2011), Bali, Indonesia.



Program Committee Member in Asia ModelingSymposium(AMS 2011), Manila,
Philippines.



Program Committee Member in 13
th

International conference on Computer Modeling
and Simulation (UKSim 2011) UK Cambridge.



Program Committee Member in 2
nd

International conference on Intelligent System,
Modeling and Simulation (ISMS 2011) Kuala Lumpur (Malaysia).



Program Committee Member in IEEE International Congress on Ultra
-
Modern
Telecommunications and Control Systems (IEE
E ICUMT 2010), Moscow, Russia.



Program Committee Member in 2nd International Conference on Computational
Intelligence, Communication Systems and Networks (CICSyN 2010), Liverpool, UK.



Invited Expert for Future Processing Chips by Intel in 2010 at Hotel Rad
isson,
Shimla,India.



Program Committee Member in IEEE
-
ANVIT(2009), St. Peterburg, Russia.



Invited Expert for Future Processing Chips by Intel in 2009 at Hotel Wild Flower,
Shimla, India.

Reviewer in
Jour
-

nals/Conferen
ces



Journal of
Super
Computing
-

Sprin
ger



Journal of
Engineering
and Computer
Innovations
(JECI)



SME2013



SIMS2013



Journal of
Parallel,
Emergent and
Distributed
Systems,
Taylor and
Francis.



PDGC 2012



ICEED2012



ICUMT 2013



APACE 2012



CHUSER 2012



ICEDSA 2012



PECON 2012



SCOReD 2012



ISBEIA 2012



ISCAIE 2012



ISCI 2012



ISIEA 2012



ISWTA 2012



ISI'12



BEIAC 2013



ISCI 2013



ISI2013
-

Mysore



ISMS2013



EUROSIM2013



IJSSST
-
V13



ICUMT 2012



UKSim2013



ICUMT
-
Workshop
-
40



CICSyN2012



SDR
-
GCC 2010


Program Co
-
Chairs:

The Second International Conference on

Parallel, Distributed and Grid Computing

(PDGC
-
2012) INDIA



Lead Guest Editor:

special issue on
:

Design and Automation for Integrated Circuits and Systems
in Journal of
Electrical and Computer Engineering Hindawi.