271
M .E BRANCH: APPLIED ELECTRONICS
NOTE:
L

LECTURE T

TUTORIALS P

PRACTICALS
CA

CONTINUOUS ASSESSMEN
T
FE

FINAL EXAM
Sl.
No
Code
Course
Hours/week
Cred
its
Maximum Marks
L
T
P
CA
F
E
Total
Semester No: I THEORY
1
11PSM101
Applied Mathematics for
Electronics Engineers
3
1
0
4
20
80
100
2
11PEK101
Advanced Digital Signal
Processing
3
1
0
4
20
80
100
3
11PEK102
Advanced Digital Systems
Design
3
1
0
4
20
80
100
4
11PEK103
MEMS
3
0
0
3
20
80
100
5
11PEK104
VLSI Design Techniques
3
0
0
3
20
80
100
6
11PEK105
Embedded
Systems
3
0
0
3
20
80
100
PRACTICAL
1
11PEK106
VLSI Lab
0
0
3
2
20
80
100
Total
18
3
3
23
24
Sl.
No
Code
Course
Hours/week
Cred
its
Maximum Marks
L
T
P
CA
FE
Total
Semester No: II
THEORY
1
11PEK201
Analog Integrated
Circuit Design
3
1
0
4
20
80
100
2
11PEK202
Computer Architecture
and
Parallel Processing
3
1
0
4
20
80
100
3
11PEK203
Digital Control
Engineering
3
1
0
4
20
80
100
4
11PBK204
Low Power VLSI
Design
3
1
0
4
20
80
100
5
11PBE2XX
Elective I
3
0
0
3
20
80
100
6
11PBE2XX
Elective II
3
0
0
3
20
80
100
PRACTICAL
1
11PEK205
Embedded System Lab
0
0
3
2
20
80
100
Total
1
8
4
3
24
25
272
NOTE:
L

LECTURE T

TUTORIALS P

PRACTICALS
CA

CONTINUOUS ASSESSMEN
T
FE

FINAL EXAM
Sl.
No
Code
Course
Hours/week
Cre
d
its
Maximum Marks
L
T
P
CA
FE
Total
Semester No: III THEORY
1
11PBE3XX
Elective III
3
0
0
3
20
80
100
2
11PBE3XX
Elective IV
3
0
0
3
20
80
100
3
11PBE3XX
Elective V
3
0
0
3
20
80
100
PRA
CTICAL
1
11PEK301
Project Work Phase
–
I
0
0
6
6
20
80
100
2
11PEK302
Technical Seminar
0
0
3
1
100

100
Total
9
0
9
16
18
Sl.
No
Code
Course
Hours/week
Cre
dits
Maximum Marks
L
T
P
CA
FE
Total
Semester No: IV
1
11PEK401
Project W
ork Phase
–
II
0
0
24
12
20
80
100
Total
0
0
24
12
24
273
LIST OF ELECTIVES
SL.
NO
COURSE
CODE
COURSE TITLE
L
T
P
C
1.
11PEEX01
ASIC Design
3
0
0
3
2.
11PEEX02
Neural Networks and Its Applications
3
0
0
3
3.
11PEEX03
Hardware Softw
are Co

Design.
3
0
0
3
4.
11PEEX04
Signal Integrity for high speed design
3
0
0
3
5.
11PEEX05
Advanced microprocessors and
microcontrollers
3
0
0
3
6.
11PEEX06
Electromagnetic Interference and
Compatibility in System Design
3
0
0
3
7.
11PEEX07
Power Electronics
3
0
0
3
8.
11PEEX08
Testing of VLSI Circuits
3
0
0
3
9.
11PEEX09
CAD of VLSI Circuits
3
0
0
3
10.
11PEEX10
Selected Topics in IC design
3
0
0
3
11.
11PEEX11
Design and analysis of real time
algorithms
3
0
0
3
12.
11PEEX12
Embedded Processors
3
0
0
3
13.
11PEEX13
Fault Tolerant Computing
3
0
0
3
14.
11PEEX14
VLSI Signal Processing
3
0
0
3
15.
11PEEX15
RF System design
3
0
0
3
16.
11PEEX16
Synthesis and Optimization of Digital
C
ircuits
3
0
0
3
17.
11PEEX17
Statistical Signal Processing
3
0
0
3
18.
11PEEX18
Wavelet Transforms and applications
3
0
0
3
19.
11PEEX19
Mathematics for Computing Research
3
0
0
3
20.
11PEEX20
Genetic algorithms and applications
3
0
0
3
2
74
11PSM101
APPLIED MATHEMATICS
(Common to M.E. Communication Systems and Applied Electronics)
L
T
P
C
3
1
0
4
Course Objectives
To provide strong foundation to the students to expose various emerging new areas of applied
mathematics and apprais
e them with their relevance in Engineering and Technological field.
UNIT

I
LINEAR ALGEBRA
(9)
Vector spaces and sub spaces
–
Null spaces, column spaces and linear transformations
–
Linear independent sets; Bases

Coordinate systems
–
Dimensions of a
vector space
–
Rank

Change of basis

Inner product, Length and Orthogonality
–
Orthogonal sets
–
Orthogonal
projections
–
Gram

Scimidt Process.
UNIT

II
WAVE EQUATION
(9)
Solution of initial and boundary value problems
–
Characteristics
–
D’Alembert’s Solution
–
Significance of characteristic curves
–
Laplace transform solutions for displacement in a long
string
–
Free vibrations of a string.
UNIT
–
III
SPECIAL FUNCTIO
NS
(9)
Bessel’s equation
–
Bessel Functions
–
Legendre’s equation
–
Legendre’s polynomials
–
Rodrigue’s formula
–
Recurrence relations
–
generating functions and orthogonal property for
Bessel functions.
UNIT

IV
STOCHASTIC PROCESSES
(9)
Ran
dom Variable
–
Moments and MGF
–
Binomial, Poisson, Normal Distributions(Concepts only).
Introduction and classification of stochastic processes, possion processes

Discrete marginal chain,
Computation of n

step transition probalities,state classification and
continuous time Markov chain

Birth and death processes, pure birth processes and death process applications.
UNIT

V
QUEUEING THEORY
(9)
Markovian models
–
Birth and Death Queuing models

Steady state results: Single and
multiple server queueing mo
dels

queues with finite waiting rooms

Finite source models

Little’s Formula, M/G/1 queue (steady state solutions only),Pollaczek
–
Khintchine formula.
TOTAL HOURS:
45 + 15=60
REFERENCES:
1.David C Lay,
“
Linear Algebra and
its Applications
”,Pearson Education
Asia,NewDelhi,2003
2. Greweal B.S. “Higher Engineering Mathematics”, Khanna Publishers, 2005
3. K.S. Trivedi, “Probability and Statistics with Reliability, Queueing and Computer Science
Applications”, John Wiley and Son
s, 2nd edition, 2002
4. Sankara Rao.K. “Introduction to Partial Differential Equation “, PHI, 1995.
5. D.Gross and C.M. Harris, “Fundamentals of Queueing Theory”, Wiley Student edition,
2004.
275
11PEK101
ADVANCED DIGITAL SIGNAL PROCESSING
(Common t
o M.E. Communication Systems and Applied Electronics)
L
T
P
C
3
1
0
4
Course Objectives
At the end of the course, student should be able to know
Discrete Random Signal Processing
Spectrum Estimation ,Linear Estimation and Prediction
Adaptive Filtering
Concepts , Multirate Signal Processing Concepts
{Review of discrete

time signals and systems

DFT and FFT, Z

Transform, Digital Filters is
recommended}
UNIT

I
DISCRETE RANDOM SIGN
AL PROCESSING
(9)
Discrete Random Processes

Ensemble averages, stationa
ry processes, Autocorrelation and
Auto covariance matrices. Parseval's Theorem, Wiener

Khintchine Relation

Power Spectral
Density Periodogram, Spectral Factorization, Filtering random processes. Low Pass Filtering
of White Noise. Parameter estimation: Bi
as and consistency.
UNIT

II
SPECTRUM ESTIMATION
(9)
Estimation of spectra from finite duration signals, Non

Parametric Methods

Correlation
Method, Periodogram Estimator, Performance Analysis of Estimators

Unbiased, Consistent
Estimators

Modified pe
riodogram, Bartlett and Welch methods, Blackman
–
Tukey method.
Parametric Methods

AR, MA, ARMA model based spectral estimation. Parameter
Estimation

Yule

Walker equations, solutions using Durbin’s algorithm
UNIT

III
LINEAR ESTIMATION AN
D PREDICTION
(
9)
Linear prediction

Forward and backward predictions, Solutions of the Normal equations

Levinson

Durbin algorithms. Least mean squared error criterion

Wiener filter for filtering
and prediction , FIR Wiener filter and Wiener IIR filters ,Discrete Kalm
an filter
UNIT

IV
ADAPTIVE FILTERS
(9)
FIR adaptive filters

adaptive filter based on steepest descent method

Widrow

Hoff LMS
adaptive algorithm, Normalized LMS. Adaptive channel equalization

Adaptive echo
cancellation

Adaptive noise cancellation

A
daptive recursive filters (IIR). RLS adaptive
filters

Exponentially weighted RLS

sliding window RLS.
UNIT

V
MULTIRATE DIGITAL SI
GNAL PROCESSING
(9)
Mathematical description of change of sampling rate

Interpolation and Decimation,
Decimation by an
integer factor

Interpolation by an integer factor, Sampling rate conversion
by a rational factor, Filter implementation for sampling rate conversion

Direct form FIR
structures, Polyphase filter structures, time

variant structures. Multistage implementat
ion of
multirate system. Application to sub band coding

Wavelet transform and filter bank
implementation of wavelet expansion of signals.
TOTAL HOURS=45+15=60
REFERENCES:
1. Monson H.Hayes, “Statistical Digital Signal Processing and Modeling”, John Wiley
and
Sons, Inc.,Singapore, 2002.
2. John G.Proakis, Dimitris G.Manolakis, “Digital Signal Processing”, Pearson Education,
2002.
3. John G.Proakis et.al.,”Algorithms for Statistical Signal Processing”, Pearson Education,
2002.
4. Dimitris G.Manolakis et.al.
,”Statistical and adaptive signal Processing”, McGraw Hill,
Newyork,2000.
276
11PEK102
ADVANCED
DIGITAL SYSTEMS DESIGN
L
T
P
C
3
1
0
4
Course Objectives
To learn how to design programmable logic circuits.
To determine the types of fault that occurs in d
igital circuits.
To describe and simulate the logic design using VHDL.
UNIT

I
SEQUENTIAL CIRCUIT DESIGN
(9)
Analysis of Clocked Synchronous Sequential Networks (CSSN)

Modeling of CSSN
–
State
Stable Assignment and Reduction
–
Design of CSSN
–
Design
of Iterative Circuits
–
ASM
Chart
–
ASM Realization.
UNIT

II
ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN
(9)
Analysis of Asynchronous Sequential Circuit (ASC)
–
Flow Table Reduction
–
Races in ASC
–
State Assignment
–
Problem and the Transition Table
–
Design
of ASC
–
Static and Dynamic
Hazards
–
Essential Hazards
–
Data Synchronizers
–
Designing Vending Machine Controller
–
Mixed Operating Mode Asynchronous Circuits.
UNIT

III
FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS
(9)
Fault Table Method
–
Path Se
nsitization Method
–
Boolean Difference Method
–
Kohavi
Algorithm
–
Tolerance Techniques
–
The Compact Algorithm
–
Practical PLA’s
–
Fault in
PLA
–
Test Generation
–
Masking Cycle
–
DFT Schemes
–
Built

in Self Test.
UNIT

IV
SYNCHRONOUS DESIGN USING PROGRAM
MABLE DEVICES
(9)
EPROM to Realize a Sequential Circuit
–
Programmable Logic Devices
–
Designing
Synchronous Sequential Circuit using a GAL
–
EPROM
–
Realization State machine using
PLD
–
FPGA
–
Xilinx FPGA
–
Xilinx 2000

Xilinx 3000
UNIT

V
SYSTEM DESIGN US
ING VHDL
(9)
VHDL Description of Combinational Circuits
–
Arrays
–
VHDL Operators
–
Compilation
and Simulation of VHDL Code
–
Modeling using VHDL
–
Flip Flops
–
Registers
–
Counters
–
Sequential Machine
–
Combinational Logic Circuits

VH
DL Code for
–
Serial
Adder, Binary Multiplier
–
Binary Divider
–
complete Sequential Systems
–
Design of a
Simple Microprocessor.
TOTAL HOURS=45+15=60
REFERENCES:
1.
Donald G. Givone “Digital principles and Design” Tata McGraw Hill 2002.
2.
John M Yarbrough “Digita
l Logic applications and Design” Thomson Learning, 2001
3.
Nripendra N Biswas “Logic Design Theory” Prentice Hall of India, 2001
4.
Charles H. Roth Jr. “Digital System Design using VHDL” Thomson Learning, 1998.
5.
Charles H. Roth Jr. “Fundamentals of Logic design”
Thomson Learning, 2004.
6.
Stephen Brown and Zvonk Vranesic “Fundamentals of Digital Logic with VHDL
Design” Tata McGraw Hill, 2002.
7.
Navabi.Z.“VHDL Analysis and Modeling of Digital Systems” McGraw International,
1998
8.
Parag K Lala, “Digital System design usin
g PLD” BS Publications, 2003
9.
Peter J Ashendem, “The Designers Guide to VHDL” Harcourt India Pvt Ltd, 2002
10.
Mark Zwolinski, “Digital System Design with VHDL” Pearson Education, 2004
277
11PEK103
MEMS
L
T
P
C
3
0
0
3
Course Ob
jectives
To learn about MEMS materials, fabrication techniques, and MEMS filters, phase
shifters and antennas
To introduce NEM
S
UNIT

I
MEMS MATERIALS AND F
ABRICATION TECHNIQUE
S
(9)
Introduction to MEMS
–
materials for MEMS
–
metals
–
semiconduc
tors
–
thin films for
MEMS and their deposition techniques
–
materials for polymer MEMS
–
bulk
micromachining for silicon

based MEMS
–
silicon surface micromachining

microstereolithography for polymer MEMS.
UNIT

II
RF MEMS SWITCHES
(9)
Introdu
ction
–
switch parameters
–
basics of switching
–
switches for RF and microwave
applications
–
Electrostatic switching
–
approaches for low

actuation
–
voltage switches
–
thermal switching
–
MEMS switch design, modeling and evaluation
–
MEMS switch design
c
onsiderations
UNIT

III
MICROMACHINED RF FIL
TERS
(9)
Introduction

modeling of mechanical filters
–
micro machined filters
–
Electrostatic comb
drive
–
micromechanical filters using comb drives, electrostatic coupled beam structure
s
–
SAW filters basics
–
design of inter digital transducers
–
capabilities, limitations and
applications
–
micro machined filters for microwave frequencies.
UNIT

IV
MEMS PHASE SHIFTERS
(9)
Introduction
–
types of pha
se shifters
–
limitations
–
MEMS phase shifters
–
switched delay
line, distributed and polymer based
–
Ferro electric phase shifters
–
distributed and bilateral
interdigitated
–
micromachined transmission lines
–
coplanar lines
–
microshield and
membrane
supported transmission lines
–
micromachined directional coupler and mixer
design, fabrication and evaluation
UNIT

V
MICROMACHINED ANTENNAS
(9)
Introduction
–
overview of microstrip antenna

design parameters
–
micromachining to
improve antenna
performance
–
micromachining as a fabrication process
–
reconfigurable
antennas
–
packaging for plastic multiplier
–
embedded overlay and self packaging
–
flipchip
assembly
–
multichip module packaging
–
reliability issues, thermal issues

Introduction t
o
NEMS
TOTAL HOURS=45
REFERENCES:
1. Vijay K.Varadhan, Vinoy K.J and Jose K.A, “RF MEMS and their Applications”, John
Wiley and Sons Inc., 2002.
2. Gabriel M. Rebeiz, “RF MEMS Theory, Design and Technology”, John Wiley and Sons
Inc., 2002.
3. Hector J De
Los Santos, “RF MEMS circuit design for Wireless Communication”, Artech
house, 2002.
278
11PEK104
VLSI DESIGN TECHNIQUES
L
T
P
C
3
0
0
3
Course Objectives
The purpose of this course is
To learn the CMOS processing technology and basic CMOS circuits, CMO
S transistor
theory and logic design.
To study about Verilog HDL programming
UNIT

I
MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY
(9)
NMOS and PMOS transistors, Threshold voltage

Body effect

Design equations

Second
order effects. MOS models and s
mall signal AC characteristics. Basic CMOS technology
UNIT

II
INVERTERS AND LOGIC GATES
(9)
NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics ,
switching
times, Super buffers, Driving large capacitance loads,
CMOS logic structures ,
Transmission gates, Static CMOS design, dynamic CMOS design.
UNIT

III CIRCUIT CHARACTERISATION AND PERFORMANCE
ESTIMATION(9)
Resistance estimation, Capacitance estimation, Inductance, switching characteristics,
transistor sizin
g, power dissipation and design margining. Charge sharing, Scaling.
UNIT

IV SUBSYSTEM DESIGN
(9)
Multiplexers, Decoders, comparators, priority encoders, Shift registers

Arithmetic circuits
–
Ripple carry adders, Carry look ahead
adders, High

speed adders, Multipliers. Physical
design
–
Delay modeling, cross talk, floor planning, power distribution, Clock distribution,
Basics of CMOS testing.
UNIT

V
VERILOG HARDWARE DESCRIPTION LANGUAGE
(9)
Overview of digit
al design with Verilog HDL, hierarchical modeling concepts, modules and
port definitions, gate level modeling, data flow modeling, behavioral modeling, task &
functions, Test Bench.
TOTAL HOURS=45
REFERENCES:
1.
Neil H.E. Weste and Kamran Eshraghian, Princip
les of CMOS VLSI Design, Pearson
Education ASIA, 2
nd
edition, 2000.
2.
John P.Uyemura, “Introduction to VLSI Circuits and Systems”, John Wiley & Sons,
Inc., 2002.
3.
Samir Palnitkar, “Verilog HDL”, Pearson Education, 2
nd
Edition, 2004.
4.
Eugene D. Fabricius, In
troduction to VLSI Design McGraw Hill International Editions,
1990.
5.
J.Bhasker, B.S.Publications, “A Verilog HDL Primer”, 2
nd
Edition, 2001.
6.
Pucknell, “Basic VLSI Design”, Prentice Hall of India Publication, 1995.
7.
Wayne Wolf “Modern VLSI Design System on ch
ip. Pearson Education.2002.
8.
Skahill. K, “VHDL for Programmable Logic” Pearson education, 1996
279
11PEK105
EMBEDDED SYSTEMS
L
T
P
C
3
0
0
3
Course Objectives
To give sufficient background for undertaking embedded systems design.
To introduce students to
the embedded systems, its hardware and software.
To introduce devices and buses used for embedded networking.
To explain real time Characteristics and System design technique.
UNIT

I
EMBEDDED ARCHITECTURE
(9)
Embedded Computers, Characteristics of
Embedded Computing Applications, Challenges in
Embedded Computing system design, Embedded system design process

Requirements,
Specification, Architectural Design, Designing Hardware and Software Components, System
Integration, Formalism for System Design

Structural Description, Behavioral Description,
Design Example: Model Train Controller
UNIT

II
EMBEDDED PROCESSOR AND COMPUTING PLATFORM
(9)
ARM processor

processor and memory organization, Data operations, Flow of Control,
SHARC processor

Memory or
ganization, Data operations, Flow of Control, parallelism with
instructions, CPU Bus configuration, ARM Bus, SHARC Bus, Memory devices, Input/output
devices, Component interfacing, designing with microprocessor development and debugging,
Design Example : A
larm Clock.
UNIT

III
NETWORKS
(9)
Distributed Embedded Architecture

Hardware and Software Architectures, Networks for
embedded systems

I2C, CAN Bus, SHARC link ports, Ethernet, Myrinet, Internet, Network

Based design

Communication Analysis, sy
stem performance Analysis, Hardware platform
design, Allocation and scheduling, Design Example: Elevator Controller.
UNIT

IV
REAL

TIME CHARACTERISTICS
(9)
Clock driven Approach, weighted round robin Approach, Priority driven Approach, Dynamic
Versus
Static systems, effective release times and deadlines, Optimality of the Earliest
deadline first (EDF) algorithm, challenges in validating timing constraints in priority driven
systems, Off

line Versus On

line scheduling.
UNIT

V
SYSTEM DESIGN TECHNIQUES
(9)
Design Methodologies, Requirement Analysis, Specification, System Analysis and
Architecture Design, Quality Assurance, Design Example: Telephone PBX

System
Architecture, Ink jet printer

Hardware Design and Software Design, Personal Dig
ital
Assistants, Set

top Boxes.
TOTAL HOURS=45
REFERENCES
1.
Wayne Wolf
,”
Computers as Components: Principles of Embedded Computing System
Design”, Morgan Kaufman Publishers, 2001.
2.
Jane.W.S. Liu “Real

Time systems”, Pearson Education Asia,
2000
3.
C.
M. Krishna and K. G. Shin , “Real

Time Systems” ,McGraw

Hill, 1997
4.
Frank Vahid and Tony Givargi” Embedded System Design: A Unified
Hardware/Software Introduction”, John Wiley & Sons, 2000.
280
11PEK106
VLSI
LAB
L
T
P
C
0
0
3
2
LIST OF EXPERIMENT
S
A.
Front end Design using VHDL
Combinational Logic:
4

bit parallel adder
4

bit serial adder
Parallel multipliers
Multiply Accumulate unit
Sequential logic:
M
ulti

bit pre

settable, up/down counters
FIFO buffer
Sequence detectors
Real

time Clock
B.
Back end Design using back end software
4

bit parallel adder
4

bit serial adder
4

bit up/down count
ers
3

bit Sequence detectors
TOTAL HOURS=30
281
11PEK201
ANALOG INTEGRATED CIRCUIT DESIGN
L
T
P
C
3
1
0
4
Course objectives
To learn the design and analysis of single stage amplifiers.
To learn about various operationa
l amplifiers and biasing circuits.
UNIT

I
SINGLE STAGE AMPLIFIERS
(9)
Common source stage, Source follower, Common gate stage, Cascode stage, Single ended and
differential operation, Basic differential pair, Differential pair with MOS loads
UNIT

II
FREQUENCY RESPONSE AND NOISE ANALYSIS
(9)
Miller effect, Association of poles with nodes, frequency response of common source stage,
Source followers, Common gate stage, Cascode stage, Differential pair, Stati
stical
characteristics of noise, noise in single stage amplifiers, noise in differential amplifiers.
UNIT

III
OPERATIONAL AMPLIFIERS
(9)
Concept of n
egative feedback, Effect of loading in feedback networks, operational amplifier
performance parameters, One

stage Op Amps, Two

stage Op Amps, Input range limitations,
Gain boosting, slew rate, power supply rejection, noise in Op Amps.
UNIT

IV
STABILITY
AND FREQUENCY COMPENSATION
(9)
General considerations, Multipole systems, Phase Margin, Frequency Compensation,
Compensation of two stage Op Amps, Slewing in two stage Op Amps, Other compensation
techniques.
UNIT

V
BIASING CIRCUITS
(9)
Basic current mirrors, cascode current mirrors, active current mirrors, voltage references,
supply independent biasing, temperature independent references,
PTAT current generation,
Constant

Gm Biasing.
TOTAL HOURS=45+15=60
REFERENCES
1. Behzad Razavi,“Design of Analog CMOS Integrated Circuits”,Tata McGraw Hill,2001
2. Willey M.C. Sansen, “Analog design essentials”, Springer, 2006.
3.
Greb
ene, “Bipolar and MOS Analog Integrated circuit design”, John Wiley &
sons,Inc., 2003.
4.
Phillip E.Allen, DouglasR.Holberg, “CMOS Analog Circuit Design”, Second edition,
Oxford University Press, 2002
282
11PEK202
COMPUTER ARCHITECTURE AND PARALL
EL
PROCESSING
L
T
P
C
3
1
0
4
Course Objectives:
To understand the basics of parallel processing and Mechanisms used in parallel
processing.
To discuss in detail the principle and classification of pipeline processors.
To study the software and paralle
l programming concepts.
UNIT

I
PRINCIPLES OF PARALLEL PROCESSING
(9)
Multiprocessors and Multi

computers
–
Multi

vector and SIMD Computers

PRAM and VLSI
Models

Conditions of Parallelism

Program Partitioning and scheduling

program flow
mechanisms

parallel processing applications

speed up performance law.
UNIT

II
PROCESSOR AND MEMORY ORGANIZATION
(9)
Advanced processor technology
–
Superscalar and vector processors

Memory hierarchy
technology

Virtual memory technology

Cache memory organizat
ion

Shared memory
organization.
UNIT

III
PIPELINE AND PARALLEL ARCHITECTURE
(9)
Linear pipeline processors

Non linear pipeline processors

Instruction pipeline design

Arithmetic design

Superscalar and super pipeline design

Multiprocessor system
inte
rconnects

Message passing mechanisms.
UNIT

IV
VECTOR, MULTITHREAD AND DATAFLOW ARCHITECTURE
(9)
Vector Processing principle

Multi

vector Multiprocessors

Compound Vector processing

Principles of multithreading

fine grain multi

computers

scalable and
multithread
architectures
–
Dataflow and hybrid architectures.
UNIT

V
SOFTWARE AND PARALLEL PROCESSING
(9)
Parallel programming models

parallel languages and compilers

parallel programming
environments

synchronization and multiprocessing modes

m
essage passing program
development

mapping programs onto multi

computers

multiprocessor UNIX design goals

MACH/OS kernel architecture

OSF/1 architecture and applications.
TOTAL HOURS=45+15=60
REFERENCES:
1.
Kai Hwang, “Advanced Computer Architecture”, T
MH 2001.
2.
William Stallings, “Computer Organization and Architecture”, McMillan Publishing
Company, 1990.
3.
M.J. Quinn, “Designing efficient Algorithms for parallel computer”, McGraw Hill
International, 1994.
283
11PEK203
DIGITAL CONTROL ENGINEERING
L
T
P
C
3
1
0
4
Course objectives:
To introduce the basic concepts and models of digital control systems, to learn the state
variable and stability analysis of discrete time systems and to design digital control systems.
UNIT I
INTRODUCTION
(9)
Ove
rview of frequency and time response analysis and specifications of control systems

Digital control systems
–
basic concepts of sampled data control systems
–
principle of
sampling, quantization and coding
–
Reconstruction of signals
–
Sample and Hold c
ircuits
–
Practical aspects of choice of sampling rate
–
Basic discrete time signals
–
Time domain
models for discrete time systems.
UNIT

II
MODELS OF DIGITAL CONTROL DEVICES AND SYSTEMS
(9)
Z domain description of sampled continuous time plants
–
models
of A/D and D/A converters
–
Z Domain description of systems with dead time
–
Implementation of digital controllers
–
Digital PID controllers
–
Position, velocity algorithms
–
Tuning
–
Zeigler
–
Nichols tuning
method.
UNIT
–
III
STATE VARIABLE ANALYSIS
(9)
State space representation of discrete time systems
–
Solution of discrete time state space
equation
–
State transition matrix
–
Decomposition techniques
–
Controllability and
Observability
–
Multi variable discrete systems.
UNIT

IV
STABILITY ANAL
YSIS
(9)
Mapping between S plane and Z plane

Jury's stability test

Bilinear transformation and
extended Routh array

Root Locus Method
–
Liapunov Stability Analysis of discrete time
systems.
UNIT

V
DESIGN OF DIGITAL CONTROL SYSTEM
(9)
Z pla
ne specifications of control system design
–
Digital compensator design
–
Frequency
response method

State feed back
–
Pole placement design
–
State Observers
–
Digital filter
properties
–
Frequency response
–
Kalman’s filter.
REFERENCES:
1. Gopal M. ‘ D
igital Control and State Variable methods’, Tata McGraw Hill Publishing
Company Ltd., New Delhi, India, 2003.
2. Kuo B.C. ‘ Digital Control Systems’, Oxford University Press, Inc., 2003
3. Ogata K. ‘Discrete Time Control Systems’, Prentice Hall Internat
ional, New Jersey, USA,
2002.
4 Houpis C.H. and Lamont C.B., ‘Digital Control Systems’, Tata McGraw Hill, New Delhi,
India, 1999.
284
11PEK204
LOW POWER VLSI DESIGN
Course objectives:
Upon completion of this course, stude
nts will be able to
analyze
and to
design
low

power VLSI circuits using different circuit technologies and design levels.
UNIT I
POWER DISSIPATION IN CMOS
(9 )
Hierarchy of limits of power
–
Sources of power consumption
–
Physics of power dissip
ation
in CMOS FET devices

Basic principle of low power design.
UNIT II
POWER OPTIMIZATION
(9)
Logical level power optimization
–
Circuit level low power design
–
Circuit techniques for
reducing power consumption in adders and multipliers.
UNIT I
II
DESIGN OF LOW POWER CMOS CIRCUITS
(9)
Computer Arithmetic techniques for low power systems
–
Reducing power consumption in
memories
–
Low power clock, Interconnect and layout design
–
Advanced techniques
–
Special techniques
UNIT IV
POWER ESTIMATION
(9)
Power estimation techniques
–
Logic level power estimation
–
Simulation power analysis
–
Probabilistic power analysis.
UNIT V
SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER
(9)
Synthesis for low power
–
Behavioral level transforms

Software design f
or low power
TOTAL HOURS= 45+15=60
REFERENCES
1.
K.Roy and S.C. Prasad ,” LOW POWER CMOS VLSI circuit design”, Wiley,2000
2.
Dimitrios Soudris, Chirstian Pignet, Costas Goutis, “DESIGNING CMOS
CIRCUITS FOR LOW POWER”, Kluwer,2002
3.
J.B. Kuo and J.H Lou, “Low voltage CMOS VLSI Circuits”, Wiley 1999.
4.
A.P.Chandrakasan and R.W. Broadersen, “Low power digital CMOS design”,
Kluwer,1995.
5.
Gary Yeap, “Practical low power digital VLSI design”, Kluwer,1998.
6.
Abdellatif Bellaouar,Mohamed.I. Elmasry,” Low power digital VLSI design”,
Kluwer, 1995.
7.
James B. Kuo, Shin
–
chia Lin,” Low voltage SOI CMOS VLSI Devices and
Circuits”, John Wiley and sons, inc 2001
L
T
P
C
3
1
0
4
285
11PEK205
EMBEDDED SYSTEMS LAB
L
T
P
C
0
0
3
2
1. Board development using 8051 microcontroller
2. Assembly and High level language programs for 8051

ports
–
timers

Seven
Segment display
–
UART
–
LCD interface
3. RTOS
–
Simple task creatio
n, Round Robin Scheduling, Preemptive
scheduling, Semaphores, Mailboxes.
4. Assembly and High level language programs for R8C

ports
–
timers

Seven
Segment display
–
UART
–
LCD interface
–
Stepper Motor control
5. Assembly and High level language programs for MSP 430

ports
–
timers

Seven Segment display
–
UART
–
LCD interface
–
Stepper Motor control
TOTAL HOURS=30
286
11PEEX01
ASIC DESIGN
L
T
P
C
3
0
0
3
Course Objectives:
To introduce the concepts of ASIC Design, types of programmable ASIC logic, I/O cells,
interconnects, design software and placement and routing
UNIT

I INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY
DESIGN
(9)
Types of ASICs

Design flow

CMOS transistors

CMOS Design rules

Combinational
Logic Cell
–
Sequential logic cell

Data path logic ce
ll

Transistors as Resistors

Transistor
Parasitic Capacitance

Logical effort
–
Library cell design

Library architecture
UNIT

II PROGRAMMABLE ASICS, LOGIC CELLS AND I/O CELLS
(9)
Anti fuse

static RAM

EPROM and EEPROM tech
nology

PREP benchmarks

Actel ACT

Xilinx LCA
–
Altera FLEX

Altera MAX DC & AC inputs and outputs

Clock & Power
inputs

Xilinx I/O blocks.
UNIT

III PROGRAMMABLE ASIC INTERCONNECT, DESIGN SOFTWARE
AND LOW LEVEL DESIGN ENTRY
(9)
Actel ACT

Xilinx LCA

Xilinx EPLD

Altera MAX 5000 and 7000

Altera MAX 9000

Altera FLEX
–
Design systems

Logic Synthesis

Half gate ASIC

Schematic entry

Low
level design language

PLA tools

EDIF

CFI design representation.
UNIT

IV LOGIC
SYNTHESIS, SIMULATION AND TESTING
(9)
Verilog and logic synthesis

VHDL and logic synthesis

types of simulation

boundary scan
test

fault simulation

automatic test pattern generation.
UNIT

V ASIC CONSTRUCTION, FLOOR
PLANNING, PLACEMENT AND
ROUTING
(9)
System partition

FPGA partitioning

partitioning methods

floor planning

placement

physical design
flow
–
global routing

detailed routing

special routing

circuit extraction

DRC.
TOTAL HOURS : 45
REFERENCES:
1.
M.J.S .Smith,
" Application

Specific Integrated Circuits "

Addison

Wesley
Longman Inc., 1997.
2.
Andrew Brown, " VLSI Circuits and Systems in Silicon", McGraw Hill, 1991
3.
S.D. Brown, R.J. Francis, J. Rox, Z.G. Uranesic, " Field Programmable Gate Arrays ",
Kluwer Acade
mic Publishers, 1992.
4.
Mohammed Ismail and Terri Fiez, " Analog VLSI Signal and Information Processing
", Mc Graw Hill, 1994.
5.
S. Y. Kung, H. J. Whilo House, T. Kailath, " VLSI and Modern Signal Processing ",
Prentice Hall, 1985.
6.
Jose E. France, Yannis Tsivi
dis, " Design of Analog

Digital VLSI Circuits for
Telecommunication and Signal Processing ", Prentice Hall, 1994.
287
11PEEX02
NEURAL NETWORKS AND ITS APPLICATIONS
L
T
P
C
3
0
0
3
Course Objectives
To introduce the techniques of adaptive neuro

fuzz
y inferencing systems which differ from
conventional AI and computing in terms of its tolerance to imprecision and uncertainty. To
become familiar with neural networks that can learn from available examples and
generalize to form appropriate rules for infe
rencing systems
UNIT

I
INTRODUCTION TO ARTIFICIAL NEURAL NETWORKS
(9)
Neuro

physiology

General Processing Element

ADALINE

LMS learning rule

MADALINE

MR2 training algorithm.
UNIT

II
BPN AND BAM
(9)
Back Propaga
tion Network

updating of output and hidden layer weights

application of BPN
–
associative memory

Bi

directional Associative Memory

Hopfield memory

traveling
sales man problem.
UNIT

III
SIMULATED ANNEALING AND CPN
(9)
Anneali
ng, Boltzmann machine

learning

application

Counter Propagation network

architecture

training

Applications.
UNIT

IV SOM AND ART
(9)
Self organizing map

learning algorithm

feature map classifier

applicatio
ns

architecture
of Adaptive Resonance Theory

pattern matching in ART network.
UNIT

V
NEOCOGNITRON
(9)
Architecture of Neocognitron

Data processing and performance of architecture of spacio

temporal networks for speech recognition.
TOTAL HOURS: 45
REFERENCES:
1. J.A. Freeman and B.M.Skapura , "Neural Networks, Algorithms Applications and
Programming Techniques", Addison

Wesely,2003.
2. Laurene Fausett, "Fundamentals of Neural Networks: Architecture, Algorithms a
nd
Applications", Prentice Hall, 1994
288
11PEEX03
HARDWARE

SOFTWARE CO

DESIGN
L
T
P
C
3
0
0
3
Course Objectives
To introduce the techniques of embedded systems and software

hardware co design..
To introduce the ideas of
prototyping an
d emulation
To familiarize with
design specification and verification
UNIT

I
SYSTEM SPECIFICATION AND MODELLING
(9)
Embedded Systems, Hardware/Software Co

Design, Co

Design for System Specification and
Modelling, Co

Design for Heterogene
ous Implementation

Processor Synthesis, Single

Processor Architectures with one ASIC, Single

Processor Architectures with many ASICs,
Multi

Processor Architectures , Comparison of Co

Design Approaches, Models of
Computation, Requirements for Embedded Syste
m Specification .
UNIT

II
HARDWARE/SOFTWARE PARTITIONING
(9)
The Hardware/Software Partitioning Problem, Hardware

Software Cost Estimation,
Generation of the Partitioning Graph, Formulation of the HW/SW Partitioning Problem,
Optimization, HW/S
W Partitioning based on Heuristic Scheduling, HW/SW Partitioning
based on Genetic Algorithms .
UNIT

III
HARDWARE/SOFTWARE CO

SYNTHESIS:
(9)
The Co

Synthesis Problem, State

Transition Graph, Refinement and Controller Generation,
Distributed Sy
stem Co

Synthesis
UNIT

IV
PROTOTYPING AND EMULATION
(9)
Introduction, Prototyping and Emulation Techniques , Prototyping and Emulation
Environments, Future Developments in Emulation and Prototyping, Target Architecture

Architecture Specializ
ation Techniques, System Communication Infrastructure, Target
Architectures and Application System Classes, Architectures for Control

Dominated Systems,
Architectures for Data

Dominated Systems ,Mixed Systems and Less Specialized Systems
UNIT

V
DESIGN SPE
CIFICATION AND VERIFICATION
(9)
Concurrency, Coordinating Concurrent Computations, Interfacing Components, Verification,
Languages for System

Level Specification and Design System

Level Specification ,Design
Representation for System Level Synthe
sis, System Level Specification Languages,
Heterogeneous Specification and Multi

Language Co

simulation
TOTAL HOURS: 45
REFERENCES:
1.
Ralf Niemann , “Hardware/Software Co

Design for Data
Flow Dominated Embedded
Systems”, Kluwer Academic Pub, 1998.
2.
Jorgen Staunstrup , Wayne Wolf ,”Hardware/Software Co

Design: Principles and
Practice” , Kluwer Academic Pub,1997.
3.
Giovanni De Micheli , Rolf Ernst Morgon,” Reading in Hardware/Software Co

Desi
gn
“ Kaufmann Publishers,2001.
289
11PEEX04
SIGNAL INTEGRITY FOR HIGH SPEED DESIGN
L
T
P
C
3
0
0
3
Course Objectives
To introduce idea of signal propagation and transmission line properties.
UNIT

I
SIGNAL PROPAGATION ON TRANSMISSION LINES
(9)
Transmission line equations, wave solution, wave
vs
. circuits, initial wave, delay time,
Characteristic impedance, wave propagation, reflection and bouncediagram

Reactive
terminations
–
L, C, static field maps of micro strip and strip line cross

secti
ons, per UNIT

length parameters, PCB layer stackups and layer/Cu thicknesses, cross

sectional analysis
tools, Zo and Td equations for microstrip and stripline Reflection and terminations for logic
gates, fan

out, logic switching, input impedance, reflect
ion coefficient, skin

effect, dispersion
UNIT

II
MULTI

CONDUCTOR TRANSMISSION LINES AND CROSS

TALK
(9)
Multi

conductor transmission

lines, coupling physics, per UNIT

length parameters, Near and
far

end cross

talk, minimizing cross

talk (stripline an
d microstrip) Differential signalling,
termination, balanced circuits, S

parameters, Lossy and Lossles models
UNIT

III
NON

IDEAL EFFECTS
(9)
Non

ideal signal return paths
–
gaps, BGA fields, via transitions, Parasitic inductance and
capaci
tance, Transmission line losses
–
Rs, tanδ, routing parasitic, Common

mode current,
differential

mode current, Connectors
UNIT

IV
POWER CONSIDERATIONS AND SYSTEM DESIGN
(9)
SSN/SSO, DC power bus design, layer stack up, SMT decoupling ,, Logic famil
ies, power
consumption, and system power delivery , Logic families and speed Package types and
parasitic, SPICE, IBIS models,Bit streams, PRBS and filtering functions of link

path
components , Eye diagrams , jitter , inter

symbol interference Bit

error rat
e ,Timing analysis
UNIT

V
CLOCK DISTRIBUTION AND CLOCK OSCILLATORS
(9)
Timing margin, Clock slew, low impedance drivers, terminations, Delay Adjustments,
canceling parasitic capacitance, Clock jitter.
TO
TAL HOURS:
45
REFERENCES
1. H. W. Johnson and M. Graham, “High

Speed Digital Design: A Handbook of Black
Magic”, Prentice Hall, 1993.
2. Douglas Brooks,” Signal Integrity Issues and Printed Circuit Board Design”,Prentice Hall
PTR, 2003.
3. S. Hall, G.
Hall, and J. McCall, “High

Speed Digital System Design: A Handbook of
Interconnect Theory and Design Practices”, Wiley

Interscience, 2000.
4. Eric Bogatin , “Signal Integrity
–
Simplified “, Prentice Hall PTR, 2003.
TOOLS REQUIRED
1. SPICE, source

htt
p://www

cad.eecs.berkeley.edu/Software/software.html
2. HSPICE from synopsis, www.synopsys.com/products/ mixedsignal/hspice/hspice.html
3. SPECCTRAQUEST from Cadence,
http://www.specctraquest.com
290
11PEEX05
ADVAN
CED MICROPROCESSORS AND MICRO
CONTROLLERS
L
T
P
C
3
0
0
3
Course Objectives:
To learn the architecture and programming of advanced Intel family microprocessors and
microcontrollers.
To introduce the basic architecture of Pentium family of processors.
To
introduce the architecture programming and interfacing of
MOTOROLA 68HC11
microcontrollers and architecture of RISC processor and ARM.
UNIT

I
MICROPROCESSOR ARCHITECTURE
(9)
Instruction set
–
Data formats
–
Instruction formats
–
Addressing modes
–
Memory hier
archy
–
register file
–
Cache
–
Virtual memory and paging
–
Segmentation
–
Pipelining
–
instruction
pipeline
–
pipeline hazards
–
Instruction level parallelism
–
reduced instruction set
–
Computer
principles
–
RISC versus CISC
–
RISC properties
–
RISC evaluation
–
On

chip register
files
versus cache evaluation
UNIT

II
HIGH PERFORMANCE CISC ARCHITECTURE
–
PENTIUM
(9)
Software model
–
functional description
–
CPU pin descriptions
–
RISC concepts
–
bus operations
–
Super scalar architecture
–
pipe lining
–
Branch prediction
–
The instruction and
caches
–
Floating point unit
–
protected mode operation
–
Segmentation
–
paging
–
Protection
–
multitasking
–
Exception and interrupts
–
Input /Output
–
Virtual 8086 model
–
Interrupt
processing

Instruction types
–
Addressing modes
–
Processor flags
–
Instruction set

programming the Pentium processor.
UNIT

III
HIGH PERFORMANCE RISC ARCHITECTURE :ARM
(9)
ARM architecture
–
ARM assembly language program
–
ARM organization and implementation
–
The ARM instruction set

The thumb instruction set
–
ARM CPU cores.
UNIT

IV
MOTOROLA 68HC11 MICROCONTROLLERS
(9)
Instructions and addressing modes
–
operating modes
–
Hardware reset
–
Interrupt system
–
Parallel I/O ports
–
Flags
–
Real time clock
–
Programmable timer
–
pulse accumulator
–
serial communication interface
–
A/D conv
erter
–
hardware expansion
–
Assembly language
Programming
UNIT

V
PIC MICRO CONTROLLER
(9)
CPU architecture
–
Instruction set

Interrupts
–
Timers
–
I/O port expansion
–
I2C bus for
peripheral chip access
–
A/D converter
–
UART
TOTAL HOURS=45
REFERENCES
:
1. Daniel Tabak , ‘’ Advanced Microprocessors” McGraw Hill.Inc., 1995
2. James L. Antonakos, “The Pentium Microprocessor ‘’ Pearson Education, 1997.
3. Steve Furber, ‘’ ARM System
–
On
–
Chip architecture “Addison Wesley, 2000.
4. Gene .H.Miller.” Micro C
omputer Engineering,” Pearson Education, 2003.
5. John .B.Peatman, “Design with PIC Microcontroller, Prentice hall, 1997.
6. James L.Antonakos,” An Introduction to the Intel family of Microprocessors ‘’ Pearson
Education 1999.
7. Barry.B.Breg,” The Intel M
icroprocessors Architecture , Programming and Interfacing “,
PHI, 2002.
8. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprint 2001
Web links
www.ocw.nit.edu
,
www.
arm.com
291
11PEEX06
ELECTROMAGNETIC INTERFERENCE AND
COMPATIBILITY IN SYSTEM
L
T
P
C
3
0
0
3
Course Objectives
To understand different electromagnetic Interference problems occurring in
Intersystem and in inter system and their possible mitigation techni
ques in Electronic
design
To understand EMI Sources, EMI problems and their solution methods in PCB level /
Subsystem and system level design.
To measure the emission. immUNIT

y level from different systems to couple with the
prescribed EMC standards
UNI
T

I
DESIGN EMI ENVIRONMENT
(9)
EMI/EMC concepts and definitions, Sources of EMI, conducted and radiated EMI, Transient
EMI, Time domain Vs Frequency domain EMI, UNIT

s of measurement parameters,
Emission and immUNIT

y concepts, ESD.
UNIT

II
EMI COU
PLING PRINCIPLES
(9)
Conducted, Radiated and Transient Coupling, Common Impedance Ground Coupling,
Radiated Common Mode and Ground Loop Coupling, Radiated Differential Mode Coupling,
Near Field Cable to Cable Coupling, Power Mains and Power Supply coup
ling.
UNIT

III
EMI/EMC STANDARDS AND MEASUREMENTS
(9)
Civilian standards

FCC, CISPR, IEC, EN, Military standards

MIL STD 461D/462, EMI Test
Instruments/Systems, EMI Shielded Chamber, Open Area Test Site, TEM Cell,
Sensors/Injectors/Couplers, Test beds f
or ESD and EFT, Military Test Method and Procedures
(462).
UNIT

IV
EMI CONTROL TECHNIQUES
(9)
Shielding, Filtering, Grounding, Bonding, Isolation Transformer, Transient Suppressors,
Cable Routing, Signal Control, Component Selection and Mounting.
UNI
T

V
EMC DESIGN OF PCBs
(9)
PCB Traces Cross Talk, Impedance Control, Power Distribution Decoupling, Zoning,
Motherboard Designs and Propagation Delay Performance Models.
TOTAL HOURS=45
REFERENCES:
1. Henry W.Ott, "Noise Reduction Techniques in Elec
tronic Systems", John Wiley and Sons,
NewYork. 1988.
2. C.R.Paul, “Introduction to Electromagnetic Compatibility” , John Wiley and Sons, Inc,
1992
3. V.P.Kodali, "Engineering EMC Principles, Measurements and Technologies", IEEE Press,
1996.
4. Bernhard Kei
ser, "Principles of Electromagnetic Compatibility", Artech house, 3rd Ed,
1986.
292
11PEEX07
TESTING OF VLSI CIRCUITS
L
T
P
C
3
0
0
3
Course objectives:
The purpose of introducing this course is to describe the fundamentals of testing the VLSI
circu
its
–
both combinational and sequential. Various testing methodologies are also
introduced.
UNIT

I
INTRODUCTION TO TESTING
(9)
Introduction to Testing

Faults in digital circuits

Modeling of faults

Logical Fault Models
–
Fault detection

Faul
t location

Fault dominance

Logic Simulation

Types of simulation

Delay models

Gate level Event

driven simulation.
UNIT

II
TESTING SEQUENTIAL AND COMBINATIONAL CIRCUITS
(9)
Test generation for combinational logic circuits

Testable combinational
logic circuit design
–
Test generation for sequential circuits

design of testable sequential circuits.
UNIT

III
TESTING APPROACHES
(9)
Design for Testability

Ad

hoc design

Generic scan based design

Classical scan based
design
–
System level
DFT approaches.
UNIT

IV
BIST
(9)
Built

In Self Test

Test pattern generation for BIST

Circular BIST

BIST Architectures
–
Testable Memory Design

Test algorithms

Test generation for Embedded RAMs
UNIT

V
DIAGNOSIS
(9)
Logic Lev
el Diagnosis

Diagnosis by UUT reduction

Fault Diagnosis for Combinational
Circuits
–
Selfchecking design

System Level Diagnosis.
TOTAL HOURS=45
REFERENCES
1. M. Abramovici, M.A. Breuer and A.D. Friedman, "Digital Systems and Testable Design"
Jaico Pu
blishing House, 2002.
2. P.K. Lala, "Digital Circuit Testing and Testability", Academic Press, 2002.
3. M.L. Bushnell and V.D. Agrawal, "Essentials of Electronic Testing for Digital, Memory
and Mixed

Signal VLSI Circuits", Kluwar Academic Publishers, 2002.
4. A.L. Crouch, "Design for Test for Digital IC's and Embedded Core Systems",Prentice Hall
International, 2002.
293
11PEEX08
CAD OF VLSI CIRCUITS
L
T
P
C
3
0
0
3
Course objectives:
Upon completion of this course, students will be able to
ana
lyze
and to
design
VLSI circuits
using different circuit technologies and design levels.
UNIT

I
INTRODUCTION TO VLSI DESIGN
(9)
Introduction to VLSI Design methodologies

Review of Data structures and algorithms

Review
of VLSI Design automation t
ools

Algorithmic Graph Theory and Computational Complexity

Tractable and Intractable problems

general purpose methods for combinatorial optimization.
UNIT

II
LAYOUT
(9)
Layout Compaction

Design rules

problem formulation

algorithms for constrain
t graph
compaction

placement and partitioning

Circuit representation

Placement algorithms

partitioning
UNIT

III
FLOOR PLAN
(9)
Floorplanning concepts

shape functions and floorplan sizing

Types of local routing
problems

Area routing

channel routing

global routing

algorithms for global routing.
UNIT

IV
SIMULATION AND MODELING
(9)
Simulation

Gate

level modeling and simulation

Switch

level modeling and simulation

combinational Logic Synthesis

Binary Decision Diagrams

Two Le
vel Logic Synthesis.
UNIT

V
HIGH LEVEL MODELLING
(9)
High level Synthesis

Hardware models

Internal representation

Allocation
assignment and
scheduling

Simple scheduling algorithm

Assignment problem
–
High level transformations.
TO
TALHOURS= 45
REFERENCES
1.
S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons,2002.
2.
N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwar
Academic Publishers, 2002.
3.
Drechsler, R.,”
Evolutionary Algorithms
for
VLSI
CAD”
, K
luwer A
cad
emic
Publishers, Boston, 1998.
4.
Hill, D., D. Shugard, J. Fishburn and K. Keutzer,”
Algorithms and Techniques
for
VLSI
Layout Synthesis”
, Kluwer A
cad
emic Publishers, Boston, 1989.
294
11PEEX09
SELECTED TOPICS IN IC DESIGN
L
T
P
C
3
0
0
3
Course objectives:
To know about the current topics in IC design
UNIT

I
VOLTAGE AND CURRENT REFERENCES
(9)
PTAT current references, startup circuits and frequency compensation, CTAT current
references, Temperature

inde
pendent current references, PTAT current generators,
Voltage references, Zero

order references, first order references, Second

order references,
state

of

the

Art Curvature

correction techniques.
UNIT

II
PRECISION REFERENCE CIRCUITS
(9)
Error source, t
he output stage, designing for power supply rejection and line regulation,
Effect of resistors temperature coefficient on a reference.
UNIT

III
OSCILLATOR FUNDAMENTALS
(9)
General considerations, Ring oscillators, LC oscillators, monolithic inductors
, monolithic
varactors, Quadrature oscillators, distributed oscillators, voltage controlled oscillators,
mathematical model of VCOs.
UNIT

IV
PHASE LOCK LOOPS
(9)
Basic PLL topology, Charge

Pump PLLs, nonideal effects in PLLs, Delay locked
loops,
Frequency multiplication and synthesis, skew reduction, Jitter reduction.
UNIT

V
CLOCK AND DATA RECOVERY
(9)
General considerations, Phase detectors for random data, frequency detectors for random
data, Full rate referenceless architecture, Du
al

VCO Architecture, Dual

loop architecture
with external reference, jitter in CDR circuits.
TOTAL HOURS=45
REFERENCES
1.
Gabriel.A. Rincon

Mora, "Voltage references from diode to precision higher order
bandgap circuits”,John wiley & Sons, Inc 2002.
2.
Michiel Steyaert , Arthur H. M. van Roermund, Herman Casier “Analog Circuit
Design High

speed Clock and Data Recovery
, High

performance Amplifiers Power
Management “ springer, 2008.
295
11PEEX10
DESIGN AND ANALYSIS OF REAL TIME ALGORITHMS
L
T
P
C
3
0
0
3
Course objectives:
This course aims to introduce the classic algorithms in various domains, and techn
iques for
designing efficient algorithms.
UNIT

I
INTRODUCTION
(9)
Algorithm: Basic Concepts (properties, classification) Performance analysis, time and space
evaluat
ion,(Space complexity, Time complexity), Asymptotic notation (O,ө,Ω,0) and
performance measurements
–
I’ Hopital’s rule.
UNIT

II
DESIGN TECHNIQUES
(9)
Algorithm design techniques : Divide and conquer method
–
binary search, merge sort, quick
sort (
performance measurement and randomized algorithm) Greedy method
–
general method,
Knapsack problem, tree vertex splitting, job sequencing with deadlines, minimum cost
spanning trees (Kruskal and Prim’s algorithm)
–
single source shortest paths
–
Packet rou
ting.
UNIT

III
GRAPH THEORETIC ALGORITHMS
(9)
Dynamic programming: General method
–
multistage graph
–
All pair shortest path, the
traveling salesman problem
–
Backtracking
–
The general method, The 8 Queen problem,
Sum of sub sets, graph coloring an
d Hamiltonian cycles.
UNIT

IV
BRANCH AND BOUND ALGORITHMS
(9)
Branch and Bound method: general method
–
LC search, LC branch and bound
–
FIFO branch
and bound solution .0/1 Knapsack problem (LC and FIFO branch and bound solution)
Algebraic problems
–
the
general method, evaluation and interpretation
–
straightforward
evaluation
–
Homer’s rule, sparse evaluation
–
FFT algorithm.
UNIT

V
NP HARD AND NP COMPLETE PROBLEMS
(9)
Basic concepts
–
Non deterministic algorithms, classes NP and NP complete, COOK’s
theo
rem
–
NP hard graph problems (DHC and TSP), NP hard scheduling problems (job shop
scheduling)
–
Circuit realization.
TOTAL HOURS=45
REFERENCES:
1.
Mark Allen Weiss,” Data structures and algorithm analysis in C ”, II Edition, Addison
Wesley Longman pvt Ltd, Delh
i,2001.
2.
Ellis Horowiz,Saratj Sahni and Sanghuthevar Rajasekaran, “Fundamental of Computer
algorithms”, Galgotia Publication ,2000.
3.
Goodman S.E and Hedetencimi S.T, “Introduction to design and analysis of structures of
algorhims”, Mc.Graw Hill Book company
, 1998.
4.
Sara baasc Allen van golder.”Computer algorthims
–
Introduction to Design and
Analysis”, Addision Wesley,2000.
5.
Rajeev Motvani and Prabakar raghavan “Randomised algorithms”,Cambridge University
press, 1999.
6.
Tremblay and Sorensan “Introduction to Dat
a structures and applications”, Tata McGraw
hill, 1995.
296
11PEEX11
EMBEDDED PROCESSORS
L
T
P
C
3
0
0
3
Course objectives
To give sufficient background for undertaking embedded systems design.
To introduce students to the embedded systems, its ha
rdware and software.
To introduce devices and buses used for embedded networking.
To explain real time Characteristics and System design technique
UNIT

I
ARM EMBEDDED SYSTEMS
(9)
ARM Embedded Systems
–
Design philosophy
–
Systems hardware
–
Systems
Software
–
ARM Processor fundamentals
–
ARM Processor families.
UNIT

II
ARM PROGRAMMING
(9)
ARM Instruction set
–
The Thumb instruction set
–
Exception and Interrupt handling
–
Firmware
–
Example programs with Embedded Operating System for ARM.
UNIT

III
ARM DSP
(9)
ARM Digital Signal Processing
–
Introduction to DSP on the ARM
–
FIR
–
IIR
–
DFT Exception
and Interrupt handling ARM memory managements UNIT

.
UNIT

IV
BALACFIN PROCESSOR
(9)
Introduction to BALACFIN Processor
–
Embedded
Processor
–
Micro signal architecture
–
Real Time Embedded Signal processing
–
Architecture
–
Software tools
–
Number formats
–
Overview of Signal acquisition and transfer to memory
–
DMA operations
–
Using Cache
–
Scratch pad memory of BALACFIN Processor
–
Power management.
UNIT

V
PRACTICAL DSP APPLICATIONS
(9)
Overview of Real Time processing
–
Signal generator with BALACFIN Processor
–
implementation FIR & IIR Filters
–
Graphic equalizer
–
Audio coding and Audio effects
–
Digital Image Processing.
TOTAL HO
URS=45
REFERENCES :
1.
Bary B.Brey “ The INTEL Microprocessor architecture, Programming and Interfacing
”, Prentice hall of India Pvt Ltd
–
New Delhi
–
2006.
2.
Andrew Sloss, Dominic Symes, and Chris Wright “ ARM System developers guide:
Designing and optimizing
system”, The Morgan Kaufmann series,2004.
3.
Woon

Seng gan, sen M.Kuo “ Embedded Signal processing with the Micro signal
architecture”,John wiliey & sons inc, Hoboken,Newjersey, 2007.
4.
Jason Andrews “Co

verification of Hardware and software for ARM SoC design
”
Newnes

2004.
297
11PEEX12
FAULT TOLERANT COMPUTING
L
T
P
C
3
0
0
3
Course objectives
To give sufficient background for undertaking test generation for digital systems
To introduce fault simulation process
UNIT

I
TEST GENERATION FOR DIGITAL
SYSTEMS
(9)
Introduction
–
Physical failures and Fault models
–
Elementary testing concepts
–
Structural
level Test generation
–
Functional level Test Generation
–
Random Testing.
UNIT

II
DESIGN FOR TESTABILITY
(9)
Introduction
–
AdHoc technique
s
–
Testability measures

TEMAS, SEOAP, TEST SCREEN.
CAMLOT, VICTOR

Scan techniques
–
Easily testable networks and function independent
testing
–
Built in Self test.
UNIT

III
FAULT SIMULATION
(9)
Introduction
–
Circuit modeling
–
Logic v
alues
–
Delays and Timing
–
User defined
description
–
Circuit capture and expansion
–
Simulation models for elementary circuits
–
General simulation algorithm
–
Evaluation algorithm
–
Fault modeling
–
Fault Simulation
methods
–
Parallel, Detective & Concur
rent Fault simulation
–
Data structures at the
functional level
–
fault injection at the functional level
–
Special Fault simulation problems
–
comparison of Fault simulation methods
–
Open issues and directions.
UNIT

IV
CODING THEORY FOR FAULT TOLERANT
SYSTEMS
(9)
Introduction
–
Error models
–
basic structural properties of Parity check codes
–
Classes of
parity check codes and general decoding schemes
–
Unidirectional and asymmetric codes
–
Codes for computer memories
–
Arithmetic codes
–
On checking
Errors in Logical operations
–
Communication coding .
UNIT

V
CODING TECHNIQUES IN FAULT TOLERANT, SELF

CHECKING
AND FAIL

SAFE CIRCUITS
(9)
Introduction
–
Error detection codes and their applications
–
Self checking circuits
–
Fault
tolerance in Co
mbinational circuits
–
Fault tolerant Sequential circuits
–
Fault tolerant
asynchronous sequential circuits
–
Fail safe sequential circuits.
TOTAL HOURS=45
REFERENCES :
1.
Dhiraj K Pradhan “Fault Tolerant Computing
–
Theory and techniques”, Prentice Hall
of I
ndia Pvt. Ltd
–
New Delhi,1986.
2.
Mohammed Ismail and Terri Fiez, “Analog VLSI Signal and Information Processing”,
McGraw Hill, 1994.
3.
S.Y. Kung, H.J.Whilo House, T.Kailath, “VLSI and Modern Signal Processing”,
Prentice Hall, 1995.
298
11PEEX13
V
LSI SIGNAL PROCESSING
L
T
P
C
3
0
0
3
Course objectives
To give sufficient background DSP based system design
To introduce various architectures
UNIT

I
INTRODUCTION TO DSP
SYSTEMS, PIPELINING
AND PARALLEL
PROCESSING OF FIR FI
LTERS
(9)
Introduction to DSP systems
–
Typical DSP algorithms, Data flow and Dependence graphs

critical path, Loop bound, iteration bound, Longest path matrix algorithm, Pipelining and
Parallel processing of FIR filters, Pipelining and Paralle
l processing for low power.
UNIT

II
RETIMING, ALGORITHMIC STRENGTH REDUCTION (9)
Retiming
–
definitions and properties, Unfolding
–
an algorithm for unfolding, properties
of unfolding, sample period reduction and parallel processi
ng application, Algorithmic
strength reduction in filters and transforms
–
2

parallel FIR filter, 2

parallel fast FIR filter,
DCT architecture, rank

order filters, Odd

Even merge

sort architecture, parallel rank

order
filters.
UNIT

III
FAST CONVOLUTION,
PIPELINING AND PARALLEL
PROCESSING OF IIR FILTERS
(9)
Fast convolution
–
Cook

Toom algorithm, modified Cook

Toom algorithm, Pipelined and
parallel recursive filters
–
Look

Ahead pipelining in first

order IIR filters,
Look

Ahead
pipelining with power

of

2 decomposition, Clustered look

ahead pipelining, Parallel
processing of IIR filters, combined pipelining and parallel processing of IIR filters.
UNIT

IV
SCALING, ROUND

OFF NOISE, BIT

LEVEL ARITHMETIC
ARCHITECTURES
(9)
Scaling and round

off noise
–
scaling operation, round

off noise, state variable description
of digital filters, scaling and round

off noise computatio
n, round

off noise in pipelined IIR
filters, Bit

level arithmetic architectures
–
parallel multipliers with sign extension, parallel
carry

ripple and carry

save multipliers, Design of Lyon’s bit

serial multipliers using
Horner’s rule, bit

serial FIR filte
r, CSD representation, CSD multiplication using Horner’s
rule for precision improvement, Distributed Arithmetic fundamentals and FIR filters
UNIT

V
NUMERICAL STRENGTH REDUCTION, SYNCHRONOUS, WAVE
AND ASYNCHRONOUS PIPELINING
(9)
Numerical strength reduction
–
subexpression elimination, multiple constant
multiplication, iterative matching, synchronous pipelining and clocking styles, clock skew
in edge

triggered single phase clocki
ng, two

phase clocking, wave pipelining.
Asynchronous pipelining bundled data versus dual rail protocol.
TOTAL HOURS=45
REFERENCES
1.
Keshab K. Parhi, “VLSI Dig
ital Signal Processing Systems, Design and
implementation “, Wiley, Interscience, 2007.
2.
U. Meyer
–
Baese, “Digital Signal Processing with Field Programmable Gate
Arrays”, Springer, Second Edition, 2004
299
11PEEX14
RF SYSTEM DESIGN
L
T
P
C
3
0
0
3
Cou
rse objectives
To give sufficient background for CMOS based design
UNIT

I
CMOS PHYSICS, TRANSCEIVER SPECIFICATIONS AND
ARCHITECTURES (9)
CMOS: Int
roduction to MOSFET Physics
–
Noise: Thermal, shot, flicker, popcorn noise
Transceiver Specifications: Two port Noise theory, Noise Figure, THD, IP2, IP3, Sensitivity,
SFDR, Phase noise

Specification distribution over a communication link
Transceiver Ar
chitectures: Receiver: Homodyne, Heterodyne, Image reject, Low IF
Architectures
–
Transmitter: Direct upconversion, Two step upconversion
UNIT

II IMPEDANCE MATCHING AND AMPLIFIERS
(9)
S

parameters with Smith chart
–
Passive IC components

Impedance matching networks
Amplifiers: Common Gate, Common Source Amplifiers
–
OC Time constants in bandwidth
estimation and enhancement
–
High frequency amplifier design Low Noise Amplifiers: Power
match and Noise match
–
Single ended and Differential
LNAs
–
Terminated with Resistors
and Source Degeneration LNAs.
UNIT

III FEEDBACK SYSTEMS AND POWER AMPLIFIERS (9)
Feedback Systems: Stability of feedback systems: Gain and phase margin, Root

locus
techniques
–
Time and Frequ
ency domain considerations
–
Compensation Power Amplifiers:
General model
–
Class A, AB, B, C, D, E and F amplifiers
–
Linearisation Techniques
–
Efficiency boosting techniques
–
ACPR metric
–
Design considerations
UNIT

IV PLL AND FREQUENCY SYNTHESI
ZERS (9)
PLL: Linearised Model
–
Noise properties
–
Phase detectors
–
Loop filters and Charge pumps
Frequency Synthesizers: Integer

N frequency synthesizers
–
Direct Digital Frequency
synthesizers
UNIT

V
MIXERS AN
D OSCILLATORS (9)
Mixer: characteristics
–
Non

linear based mixers: Quadratic mixers
–
Multiplier based mixers:
Single balanced and double balanced mixers
–
subsampling mixers Oscillators: Des
cribing
Functions, Colpitts oscillators
–
Resonators
–
Tuned Oscillators
–
Negative resistance
oscillators
–
Phase noise
TOTAL HOURS=45
REFERENCES
1.
T.Lee, “Design
of CMOS RF Integrated Circuits”, Cambridge, 2004
2.
B.Razavi, “RF Microelectronics”, Pearson Education, 1997
3.
Jan Crols, Michiel Steyaert, “CMOS Wireless Transceiver Design”, Kluwer Academic
Publishers, 1997
4.
B.Razavi, “Design of Analog CMOS Integrated Circuits
”, McGraw Hill, 2001.
300
11PEEX15
SYNTHESIS AND OPTIMIZATION OF DIGITAL
CIRCUITS
L
T
P
C
3
0
0
3
Course objectives
To give sufficient background for circuits and hardware modeling
To introduce optimization procedures
UNIT

I
CIRC
UITS AND HARDWARE MODELING
(9)
Design of Microelectronic Circuits

Computer Aided Synthesis and optimization

Combinatorial optimization

Boolean Algebra and Application

Hardware Modeling
Languages
–
Compilation and Behavioral optimization.
UNIT

I
I
ARCHITECTURAL LEVEL SYNTHESIS AND OPTIMIZATION (9)
The Fundamental Architectural synthesis Problems

Area and performance Estimation

Control
UNIT

synthesis

synthesis of pipelined circuits.
UNIT

III
SCHEDULING ALGORITHMS AND RESOURCE SHARING (
9)
Unconstrained Scheduling

ASAP Algorithm

ALAP Scheduling Algorithm

Scheduling with
Resource Constraints

Scheduling pipelined circuits

Sharing and binding for Dominated
circuits

Area Binding

Concurrent Binding
–
Module selection problems

Structural testa
bility.
UNIT

IV
LOGIC

LEVEL SYNTHESIS AND OPTIMIZATION
(9)
Logic optimization Principles

Algorithms and logic Minimization
–
Encoding problems

Multiple

level optimization of logic networks

Algebraic and Boolean model

Algorithm for
delay Evaluation

Rule based logic optimization.
UNIT

V
SEQUENTIAL LOGIC OPTIMIZATION
(9)
Sequential circuit

State Encoding

Minimization methods

Retiming

Finite state machine

testability for synchronous circuits

Algorithm for library binding

Look

Up table

FPGA

Rule

based library binding.
TOTAL HOURS=45
REFERENCES
1.
Giovanni De Micheli, “Synthesis and optimization of Digital Circuits”, Tata McGraw

Hill, 2003.
2.
John Paul Shen, Mikko H. Lipasti, “Modern processor Design”, Tata McGraw Hill,
2003
301
11PEEX16
STATISTICAL SIGNAL PROCESSING
L
T
P
C
3
0
0
3
Course objectives:
The main
purpose
of this course is to introduce students the fundamentals of Discrete Random
Signal processing

Discrete random process and its types, various methods of spectra
l
estimation, Linear estimation and prediction methods, Adaptive filter types and multirate
digital signal processing and its appliations.
UNIT

I
DISCRETE RANDOM SIGNAL PROCESSING
9
Discrete Random Processes

Ensemble Averages, Stationary proces
ses, Bias and Estimation,
Autocovariance, Autocorrelation, Parseval’s theorem, Wiener

Khintchine relation, White
noise, Power Spectral Density, Spectral factorization, Filtering Random Processes, Special
types of Random Processes
–
ARMA, AR, MA
–
Yule

Walk
er equations.
UNIT

II
SPECTRAL ESTIMATION
(9)
Estimation of spectra from finite duration signals, Nonparametric methods
–
Periodogram,
Modified periodogram, Bartlett, Welch and Blackman

Tukey methods, Parametric methods
–
ARMA, AR and MA mode
l based spectral estimation, Solution using Levinson

Durbin
algorithm
UNIT

III
LINEAR ESTIMATION AND PREDICTION (9)
Linear prediction
–
Forward and Backward prediction, Solution of Prony’s normal equations,
Least mean

squared error criterion, Wiener filter for filtering and prediction, FIR and IIR
Wiener filters, Discrete Kalman filter
UNIT

IV
ADAPTIVE FILTERS
(9)
FIR adaptive filters
–
adapti
ve filter based on steepest descent method

Widrow

Hopf LMS
algorithm, Normalized LMS algorithm, Adaptive channel equalization, Adaptive echo
cancellation, Adaptive noise cancellation, RLS adaptive algorithm.
UNIT

V
MULTIRATE DIGITAL SIGNAL PROCESSING
(9)
Mathematical description of change of sampling rate
–
Interpolation and Decimation,
Decimation by an integer factor, Interpolation by an integer factor, Sampling rate conversion
by a rational factor, Polyphase filter structures, Multis
tage implementation of multirate
system, Application to subband coding
–
Wavelet transform
TOTAL HOURS=45
REFERENCES
1.
Monson H. Hayes, ‘Statistical Digital Signal Processing and Modeling”, John
Wiley and Sons, Inc, Singapore, 2002
2.
John J. Proakis, Dimitris
G. Manolakis, ‘Digital Signal Processing’, Pearson
Education, 2002
3.
Rafael C. Gonzalez, Richard E. Woods, ‘ Digital Image Processing’, Pearson
Education Inc.,Second Edition, 2004
302
11PEEX17
WAVELET TRANSFORMS AND APPLICATIONS
L
T
P
C
3
0
0
3
Cour
se objectives:
The purpose of introducing this course is to describe the fundamentals of Wavelets and
Wavelet transforms

Continuous and Discrete Wavelet transforms and the applications of
wavelets in signal and image processing. By undergoing this course,
the student will
understand the significance of wavelet transform.
UNIT

I
MATHEMATICAL PRELIMINARIES
(9)
Linear spaces
–
Vectors and vector spaces
–
Basis functions
–
Dimensions
–
Orthogonality and
biorthogonalilty
–
Local basis and Riesz basis
–
Di
screte linear normed space
–
Approximation by orthogonal projection
–
Matrix algebra and linear transformation.
UNIT

II
TIME FREQUENCY ANALYSIS
(9)
Window function
–
Short time Fourier transform
–
Discrete short time Fourier transform
–
Discrete Gab
or representation
–
Continuous wavelet transform
–
Discrete wavelet transform
–
Wigner

Ville distribution
–
Properties of Wigner

Ville distribution.
UNIT

III
MULTIRESOLUTION ANALYSIS
(9)
Multiresolution spaces
–
Orthogonal, biorthogonal and semiortho
gonal decomposition
–
Two
scale relations
–
Decomposition relation
–
Wavelets construction
–
Orthogonal wavelets
–
Orthonormal scaling functions
–
Construction of biorthogonal wavelets.
UNIT

IV
DISCRETE WAVELET TRANSFORM AND FILTER BANK
ALGORITHM
(9)
De
cimation and interpolation
–
Signal representation in the approximation subspace
–
Wavelet decomposition algorithm
–
Reconstruction algorithm
–
Change of bases
–
Two
channel perfect reconstruction filter bank
–
Polyphase representation for filter banks.
UNI
T

V
DIGITAL SIGNAL PROCESSING APPLICATIONS
(9)
Wavelet packets
–
Wavelet packet algorithms
–
Thresholding
–
Two dimensional wavelets
and wavelet packets
–
Wavelet and wavelet packet algorithms for two dimensional signals
–
image compression
–
image co
ding, wavelet tree coder, EZW code, EZW example.
TOTAL HOURS= 45
REFERENCES
1 Jaideva C. Goswami and Andrew K. Chan, “Fundamentals of Wavelet

Theory,Algorithms
and Applications”, A Wiley
–
Interscience Publication, 1999.
2 Rao RM and AS Bopardikar, “Wa
velet Transforms”, Addison Wesley, 1998.
3 Strang G Nguyen T, “Wavelet and filter banks”, Wellesley Cambridge Press1996.
4 Vetterli M. Kovacevic J, “Wavelets and Subband Coding”, Prentice Hall, 1995.
303
11PEEX18
MATHEMATICS FOR COMPUTING RESEARCH
L
T
P
C
3
0
0
3
Course Objectives:
Gives important insights into the mathematical ideas for research.
Discusses about linear and vector algebra , probability and queueing theory ideas for
research.
UNIT

I
PROOF TECHNIQUES
(9)
Constructive Proo
f
–
Equivalence
–
Negation
–
Contra positive
–
Converses
–
Contradiction
–
Uniqueness
–
Multiple Equivalences
–
Proving identity
–
Decomposition
–
Induction.
UNIT

I
I
VECTOR ALGEBRA
(9)
Vector quantities and their graphical representation
–
vector sp
aces
–
Linear Combinations
–
Spanning sets
–
Linear Independence and dependence
–
Standard Bases
–
Dimension
–
subspaces
–
scalar and vector products.
UNIT

III
LINEAR ALGEBRA
(9)
Eigen Values and Eigen Vectors
–
Linear Transformation Orthogonal D
iagonalization
–
Jordan Canonical Form.
UNIT

IV
PROBABILITY
(9)
Distributions and Densities
–
Expected Value and Variance
–
Central Limit Theorem
–
Generating Functions
–
Markov Chains

Random Walks.
UNIT

V
QUEUEING THEORY
(9)
Queueing Mode
ls and fundamental relations
–
M/M/1
–
M/M/C
–
M/G/1
–
G/M/1.
TOTAL HOURS=45
REFERENCES:
1. I Adan and J. Resing, “Queueing Theory”
–
Open Souce.
2. Robert A. Beezer, “A first course in Linear Algebra”, Open Source.
3. Charles M. Grinsted and J. Laurie Snel
l,” Introduction to Probability”, Open Source.
304
11PEEX19
GENETIC ALGORITHMS AND APPLICATIONS
L
T
P
C
3
0
0
3
Course Objectives:
This course teaches the fundamentals of Genetic algorithm, Genetic technology, genetic
programming, Advanced
operators and techniques in genetic research, Computer
implementation of genetic algorithm and various applications of genetic algorithm.
UNIT

I
FUNDAMENTALS OF GENETIC ALGORITHM
(9)
A brief history of evolutionary computation

biological terminology

se
arch space

encoding,
reproduction

elements of genetic algorithm

genetic modeling

Traditional optimization

comparison of GA and traditional search methods.
UNIT

II
GENETIC TECHNOLOGY
(9)
Steady state algorithm

fitness scaling
–
coding

a multipara
meter, mapped, fixedpoint coding

Discretization

constraints

inversion. Genetic programming

Genetic Algorithm in problem
Solving
UNIT

III
ADVANCED OPERATORS AND TECHNIQUES IN GENETIC
RESEARCH
(9)
Dominance, diploidy and abeyance

other micro
operators

Genetic Algorithm in engineering
and
optimization

natural evolution
–
simulated annealing, Genetic Algorithm in scientific models
and
theoretical foundations.
UNIT

IV
COMPUTER IMPLEMENTATION OF GENETIC ALGORITHM (9)
Implementing a Genetic Alg
orithm
–
computer implementation

low level operator and
knowledge based techniques in Genetic Algorithm

Improvement in basic techniques

current
applications of genetic algorithms
UNIT

V
CURRENT APPLICATIONS OF GA
(9)
Applications of Genetic based m
achine learning

Genetic Algorithm and parallel processors,
composite laminates, constraint optimization, multilevel optimization, real life problem.
TOTAL HOURS=45
REFERENCES
1. Melanie Mitchell, “An introduction to Genetic Algorithm”, Prentice

Hall of Ind
ia,
NewDelhi, 2004.
2. David.E.Golberg,” Genetic algorithms in search, optimization and machine learning”,
Addition, Wesley, 1999
3. S.Rajasekaran and G.A Vijayalakshmi Pai,” Neural Networks, Fuzzy logic and Genetic
Algorithms, Synthesis and Applications”,
Prentice Hall of India, New Delhi, 2003.
4. Nils.J.Nilsson, “Artificial Intelligence

A new synthesis”, Original Edition, 1999.
305
11PEEX20
POWER ELECTRONICS
L
T
P
C
3
0
0
3
Course Objectives:
This course teaches the fundamentals of converters,
converter dynamics, magnetic principles ,
power system harmonics, and various types of rectifiers.
UNIT

I
CONVERTERS IN EQUILI
BRIUM
(9)
Principles of Steady State Converter Analysis
–
Boost and Buck Conve
rter Examples Steady

State Equivalent Circuit Modeling, Losses, and Efficiency
–
Equivalent circuit model
–
complete circuit model


Switch Realization

Switching loss

Converter Circuits
–
Circuit
manipulation
–
Transformer isolation
–
Converter evalu
ation and design
UNIT

II
CONVERTER DYNAMICS A
ND CONTROL
(9)
The Basic AC Modeling Approach

Averaging the Inductor and capacitor Waveforms

A
Nonideal Flyback Converter

State

Space Averaging

Circuit Averaging
and Averaged
Switch Modeling

The Canonical Circuit Model

Converter Transfer Functions

Analysis of
Converter Transfer Functions

Graphical Construction of Impedances and Transfer Functions

Controller Design

Input Filter Design

Current Programme
d Control
UNIT

III
MAGNETICS
(9)
Basic Magnetics Theory

Transformer Modeling

Loss Mechanisms in Magnetic Devices

Eddy Currents in Winding Conductors

Inductor Design

Filter Inductor Design Constraints

A Step

by

Step Procedure

Transformer Desi
gn

A Step

by

Step Transformer Design
Procedure
UNIT

IV
MODERN RECTIFIERS AND POWER SYSTEM HARMONICS (9)
Power Phasors in Sinusoidal Systems

Harmonic Currents in Three

Phase Systems

AC Line
Current Harmonic Standards

Line

Commutated Rectifiers

The Single

Phase Full

Wave
Rectifier

The Three

Phase Bridge Rectifier

Phase Control

Pulse

Width Modulated
Rectifiers

Realization of a Near

Ideal Rectifier

Control of the Current Waveform

Ideal
Three

Phase Rectifiers
UNIT

IV
RESONANT CONVERTERS
(9)
Resonant Conversion

Sinusoidal Analysis of Resonant Converters
–
Examples

Soft
Switching

Soft

Switching Mechanisms of Semiconductor Devices

The Zero

Current

Switching Quasi

Resonant Switch Cell

Resonan
t Switch Topologies

Soft Switching in
PWM Converters
TOTAL HOURS=45
REFERENCES
1. Robert W. Erickson, Dragan Maksimovic,” Fundamentals of Power Electronics”, Kluwer
Academic Publishers, Second Edition, New York, Boston, Dordrecht, London, Moscow.
2.
Muhammad H Rashid, “ Power Electronics
–
Circuits, Devices and Applications”, Third
Edition, Prentice Hall of India, 2004.
3. M.D. Singh, K.B.Khanchandani, “ Power Electronics”, Tata McGraw Hill, 1998.
4. Ned Mohan, Tore M Undeland, William P. Robbins,” Po
wer Electronics, Converters,
Applications and Design”, John Wiley & Sons, 1994.
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