Image Processing Units - HAW Hamburg

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6 Νοε 2013 (πριν από 3 χρόνια και 9 μήνες)

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haw hamburg

Prof. Dr.
-
Ing.
B. Schwarz



FACHBEREICH ELEKTROTECHNIK/ INFORMATIK



DIGITAL SYSTEM DESIGN


Feb. 12, 2001


I
MAGE
P
ROCESSING
U
NITS



FPGA

C
OPROCESSOR
B
OARDS


Name

IPU
-
1

IPU
-
2/microEnable

PC
-
System/OS/Bus

Pentium I/WIN95;DOS/ISA 8 Bit

Pentium II/WIN NT 4.0/PCI 32 Bit

HW
-
SW Manufacturer

Student thesis projects

Silicon Software GmbH; www.silicon
-
software.com

XI
LINX FPGA

4013E
-
3 PQ160/4006E
-
4 PG159

4044XLA
-
09 PQ240/4036XLA
-
09 PQ240

Image Memory

0.5 MB SRAM 70ns

2MB/0.5MB SRAM 12ns

User Interface/Connector

8 Bit bidirectional/25 pin connector SUB
-
D

RS
-
422 transceiver module/CMC IEEE P 1396

Clock System

External

oscillator socket

5 Clock
-
channels programmable up to 120 MHz

PC Control Software

C
-
Code

Imagetransfer; configuration; reset and operation
handshake; interrupt service

C
-
functions support datatransfer: Single
-
/burst
-
transfer; DMA and DMA on demand; int
errupt
service

Presynthesized Interface
Module

---

Top
-
Entity module: Links to local bus and to SRAM;
XNF
-
file

VHDL Modules
developed by student
project teams



Structural model: Bus interface and memory
addressing platform



Gray level enhancement: Histogr
am equalization



Noise reduction: Median filter



Edge detection: Laplacian and Sobel operator



Segmentation: Opening and closing of binary
images



Structural model: Bus and memory links;
memory addressing module; CCD
-
camera
interface



Histogram equalization; FP
GA
-
RAM used for
histogram and LUT storage



Median/Laplcian filter data path with enhanced
number of pipelining stages (54.7 MHz)



Filter sequences: Median
-
Laplacian/Sobel

Status of test results

Operation up to 40 MHz

Operation up to 45 MHz