A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

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A new symmetrical double gate nanoscale MOSFET with
asymmetrical side gates for electrically induced source/drain
Ali A.Orouji
a
,M.Jagadesh Kumar
b,
*
a
Department of Electrical Engineering,Semnan University,Semnan,Iran
b
Department of Electrical Engineering,Indian Institute of Technology,Delhi,Hauz Khas,New Delhi 110016,India
Received 27 June 2005;received in revised form 1 October 2005;accepted 2 November 2005
Available online 28 November 2005
Abstract
In this paper,we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side
gates as an extension of the source/drain.The asymmetrical side gates are used to induce extremely shallow source/drain regions on
either side of the main gate.Using two-dimensional and two-carrier device simulation,we have investigated the improvement in device
performance focusing on the threshold voltage roll-off,the drain induced barrier lowering,the subthreshold swing and the hot carrier
effect.Based on our simulation results,we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical
side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional
symmetrical double gate SOI MOSFET.We show that when the side gate length is equal to the main gate length,the device can be oper-
ated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect.We further show that in the proposed structure
the threshold voltage of the device is nearly independent of the side gate bias variation.
 2005 Elsevier B.V.All rights reserved.
Keywords:Short-channel effects;MOSFET;Threshold voltage;Two-dimensional simulation;Induced source/drain
1.Introduction
The CMOS transistor gate length scaling is projected to
continue through 2016 down to the incredible 9 nm [1].
Even if these dimensions can be realized using technologi-
cal innovations,CMOS devices will suffer from a number
of short channel effects,such as the threshold voltage
roll-off,the drain induced barrier lowering (DIBL) and
the subthreshold swing all of which degrade the MOSFET
performance.A number of solutions have been proposed
to overcome these problems [2].Employing a double gate
field effect transistor (DG MOSFET) structure instead of
using bulk-Si transistors is one of these solutions.In addi-
tion to the inherent suppression of SCEs,DG MOSFETs
offer high drive current and transconductance [3].More
importantly,the electrical coupling between the two gates
results in high I
on
/I
off
ratios when the threshold voltage is
properly controlled [4,5].
An ultra shallow extended source/drain is another effec-
tive method to suppress SCEs.But,it is very difficult to
form shallow junctions by conventional fabrication tech-
niques.However,it has been reported that SCEs can be
suppressed by using an inversion layer as an ultra shallow
extended S/D [6–12].These devices are known as electri-
cally variable shallow junction MOSFETs (EJ MOSFETs).
In spite of the area penalty associated with these devices
due to the additional side gates required for the inversion
layer formation,EJ MOSFETs are expected to play a
major role in the reduction of SCEs and hot carrier effects
as discussed in our paper.To combine the advantages of
both DG and EJ structures,in this paper we propose a
novel symmetrical double gate nanoscale MOSFET with
asymmetrical side gates for electrically induced source/
drain regions.This structure is similar to that of a symmet-
rical DG MOSFET with the exception that the front gate
0167-9317/$ - see front matter  2005 Elsevier B.V.All rights reserved.
doi:10.1016/j.mee.2005.11.002
*
Corresponding author.Tel.:+91 11 2659 1085;fax:+91 11 2658 1264.
E-mail address:mamidala@ieee.org (M.J.Kumar).
www.elsevier.com/locate/mee
Microelectronic Engineering 83 (2006) 409–414
consists of two asymmetrical side gates on both sides of the
main gate.The aim of this paper is,therefore,to present
the design and performance considerations of the proposed
structure using two-dimensional simulation [13].First,we
have compared the performance of the EJ-DG structure
with the symmetrical double gate (S-DG) structure in terms
of threshold voltage,subthreshold swing,and electric field.
Second,we have investigated the side gate design consider-
ations in terms of threshold voltage,electric field,and hot
carriers effects.Based on our simulation results,we demon-
strate that the proposed EJ-DG structure is superior to the
symmetrical double gate (S-DG) structure in controlling
the SCEs.
2.EJ-DG structure
A schematic cross-sectional view of EJ-DG MOSFET
implemented using the 2-D device simulator MEDICI is
shown in Fig.1.The front gate consists of two side gates
using n
+
-poly and a main gate using p
+
-poly while the back
gate is a p
+
-poly gate.The doping in the silicon thin film is
kept at 10
15
cm
3
(i.e.,lightly doped with N
A
< 10
16
cm
3
[14]) to avoid adverse effects associated with heavy doping,
such as the mobility degradation [15] and the random
microscopic fluctuations of dopant atoms [16].The doping
in the n
+
source/drain regions is kept at 5 · 10
19
cm
3
.The
typical values of the main-gate and the side gate lengths are
identical and equal to 50 nm.The thicknesses of main gate
oxide and side gate oxide are identical and equal to 3 nm.
The thickness of diffusion barrier between the main and
the side gate is 4 nm.The work functions of p
+
-poly and
n
+
-poly are chosen as 5.25 and 4.17 eV,respectively.The
silicon thin filmthickness is chosen as 10 nm.All the device
parameters of EJ-DG are equivalent to those of the sym-
metrical DG (S-DG) unless otherwise stated.
Conventional 2-D simulation of semiconductor devices
is based on the thermal equilibrium approximation
(TEA),which implies that carrier temperatures are equal
to the (constant) lattice temperature.For EJ-DGstructure,
this assumption is invalid since the electric fields in the
direction of current flow can be very large.Therefore,we
must consider the velocity saturation effects and the local
carrier heating in the channel region for accurately predict-
ing the device behavior.Due to local carrier heating,carrier
temperatures significantly differ from the lattice tempera-
ture resulting in inhomogeneous carrier temperature distri-
butions in the channel region of the device.As a result,the
carrier temperature gradients can make the thermal diffu-
sion currents to be significant and together with the local
carrier heating may influence the spatial carrier distribu-
tions and hence the thermal currents [17–19].
To account for the above,we have selected the full
energy balance model for mobility model in our simula-
tions in which the electron temperature is fed back into
the continuity equation.Impact ionization is again com-
puted as a post processing step.However,if we choose
other mobility models such as the approximate energy bal-
ance model,the carrier temperature is never fed back to the
drift-diffusion equation [13] and this can result in substan-
tial errors in the prediction of carrier transport.
3.Results and discussion
Fig.2 shows a typical MEDICI simulated 2-D electron
density distribution from source to drain of the EJ-DG
structure for the main gate voltage V
MGS
=0 V,the side
Fig.1.Cross-sectional view of the EJ-DG SOI MOSFET structure.
Fig.2.Electron distribution in the silicon thin filmof the EJ-DGstructure
for V
MGS
=0 V,V
SGS
=1.5 V and V
DS
=0 V.
410 A.A.Orouji,M.J.Kumar/Microelectronic Engineering 83 (2006) 409–414
gate voltage V
SGS
=1.5 V and the drain to source voltage
V
DS
=0 V.As can be seen fromthe figure,the electron dis-
tribution in the channel region under the side gates
decreases exponentially (linearly in the log scale) from the
top of the silicon film to its bottom.Due to the difference
between the work functions of the side gates and the back
gate,the inversion layer is formed at the top surface of the
silicon filmunder the side gate [20].But,the electron distri-
bution in the channel region under the main gate is almost
fixed and the change is very limited [21].In other words,the
proposed EJ-DG structure is an asymmetrical double gate
(A-DG) in the side gate regions,and symmetrical double
gate (S-DG) in the main gate region.Therefore,the good
features of both the S-DG and the A-DG are combined
in the proposed EJ-DG structure.
3.1.Performance comparison with S-DG
In Fig.3,the surface potential is plotted against the hor-
izontal distance in the channel for the EJ-DG structure.It
can be seen from the figure that due to the presence of the
electrically induced source/drain,there is no significant
change in the potential under the main gate as the drain
bias is increased even up to 1.5 V.Hence,in the EJ-DG
structure,the channel region under the main gate is
‘‘screened’’ from the changes in the drain potential.As a
consequence,V
DS
has only a very small effect on the drain
current after saturation.Therefore,the side gates (i.e.vir-
tual source/drain) are expected to effectively suppress the
short channel effects.
The output characteristics of the EJ-DG MOSFET are
compared with that of the S-DG MOSFET in Fig.4.
The drive capability of the EJ-DG MOSFET is lower than
that of the S-DGMOSFET.This is expected because of the
increased source/drain resistance in the EJ-DG MOSFET
due to the extremely shallow depth of the inversion layers
under the side gates.However,the output characteristics
of the EJ-DG MOSFET are nearly ideal with significantly
improved output conductance and improved breakdown
voltage.These two advantages clearly overweigh a small
reduction in the drive capability.It is worth noting that
adopting the inversion layer as an extended source/drain
is very effective in not only controlling SCEs but also
reducing source/drain parasitic resistance when a sub-
15 nm source/drain is needed for future scaled CMOS [6].
In Figs.5 and 6,the threshold voltage and the sub-
threshold swing of the EJ-DG and the S-DG MOSFETs
are compared as a function of the main channel length.
The threshold voltage values in our simulation are
obtained from the commonly used maximum transconduc-
tance method.It can be observed clearly that the EJ-DG
structure exhibits a lower threshold voltage roll-off.In
the case of EJ-DG,when the main channel length is
0 20 40 60 80 100 120 140 160
-0.5
0.0
0.5
1.0
1.5
2.0
1.5V
0.9V
V
DS
=0.5V
L
S
=50nm
L
M
=50nm
V
SGS
=1V
V
MGS
=0.2V
Surface Potential (Volts)
Position in Channel (nm)
Fig.3.Surface potential profiles in the channel of the EJ-DGMOSFETs.
0.0 0.5 1.0 1.5 2.0
0.0
0.5
1.0
1.5
2.0
L
S
=L
M
=50nm
V
SGS
=1.5V
V
MGS
=1.4V
V
MGS
=1.2V
V
MGS
=1V
Drain Current, ID(mA)
Drain Voltage, V
DS
(V)
EJ-DG
S-DG
Fig.4.Output characteristics of the EJ-DG and S-DG MOSFETs
20 30 40 50 60
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
EJ-DG
V
DS
=50mV
V
SGS
=1V
L
S
=50nm
S-DG
V
DS
=50mV
Threshold Voltage (Volts)
Main Channel Length (nm)
S-DG
EJ-DG
Fig.5.Threshold voltage versus main channel length for channel lengths
up to 20 nm with the side gate length fixed at 50 nm.
A.A.Orouji,M.J.Kumar/Microelectronic Engineering 83 (2006) 409–414 411
reduced from 60 to 20 nm,the variation in threshold volt-
age is only approximately 7%.In addition,even for a main
channel length of L
M
=20 nm the subthreshold swing of
the EJ-DG structure is near ideal while it is significantly
larger for the S-DG structure.
The threshold voltage as a function of silicon thin-film
thickness of the EJ-DG MOSFET is compared with the
S-DG MOSFETs in Fig.7.As can be seen from the figure,
when the silicon thin film thickness is reduced from 40 to
8 nm,the threshold voltage roll up of the EJ-DG structure
is 51 mV while for the S-DG structure,the roll up is
112 mV.Therefore,in the EJ-DG MOSFETs,the depen-
dence of threshold voltage on the silicon thin-filmthickness
can be more effectively controlled as compared to the S-
DGMOSFETs.This is due to the existence of a workfunc-
tion difference in the front gates in the case of EJ-DG
MOSFETs.
In Fig.8,the electric field distribution along the channel
near the drain is shown for S-DG and EJ-DG MOSFETs
with a channel length L = 50 nm.It is evident from the
figure that the presence of the induced drain under the side
gate reduces the peak electric field considerably.Fig.9
shows the dependence of surface potential on the side gate
bias.The main gate voltage is set at 1 V.When the side gate
bias is less than 0 V,the surface-potential in the virtual
drain is low,and there are not enough carriers in the virtual
drain.However,when the side gate bias is more than 0 V,
the potential in the virtual drain will increase and the car-
rier concentration in the virtual source and drain is suffi-
cient for the inversion layers to function as the virtual
source and drain.As the side gate voltage increases,resis-
tance of the virtual source and drain (due to dependency
of carrier￿s concentration to voltage bias) will reduce and
the current of the device will increase.It should be noted
that the potential edge in the virtual drain moves slightly
20 30 40 50 60
60
70
80
90
100
110
120
EJ-DG
V
DS
=50mV
V
SGS
=1V
L
S
=50nm
S-DG
V
DS
=50mV
S-DG
EJ-DG
Subthreshold Swing (mV/dec)
Main Channel Len
g
th (nm)
Fig.6.Subthreshold swing versus main channel length for channel lengths
up to 20 nm with the side gate length fixed at 50 nm.
5 10 15 20 25 30 35 40 45
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
EJ-DG
V
DS
=50mV
V
SGS
=1V
L
S
=50nm
L
M
=50nm
S-DG
V
DS
=50mV
L=50nm
S-DG
EJ-DG
Threshold Voltage (Volts)
Thickness of Thin Layer (nm)
Fig.7.Threshold voltage versus silicon thin-film thickness for the S-DG
and the EJ-DG MOSFETs.
25 30 35 40 45 50
0.0
0.5
1.0
1.5
2.0
2.5
EJ-DG
V
DS
=1.5V
V
MGS
=0.2V
V
SGS
=1V
L
S
=50nm
L
M
=50nm
S-DG
V
DS
=1.5V
V
GS
=0.2V
L=50nm
Electric Field (MV/cm)
Position in the Main Channel (nm)
S-DG
EJ-DG
Fig.8.Longitudinal electric field along the channel toward the drain end
for the S-DG and the EJ-DG MOSFETs.
-20 0 20 40 60 80 100 120 140 160
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.5V
1V
0.5V
V
SGS
=-0.2V
V
DS
=1.5V
V
MGS
=1V
L
S
=50nm
L
M
=50nm
Surface Potential (Volts)
Position in Channel (nm)
Fig.9.Surface potential profiles in the channel of the EJ-DG MOSFET
for different side gate biases.
412 A.A.Orouji,M.J.Kumar/Microelectronic Engineering 83 (2006) 409–414
into the channel as the side gate bias increases above 0 V.
In other words,the threshold voltage of the device is only
marginally dependent on the side gate bias as shown in
Fig.10.Hence,we can consider that the threshold voltage
practically remains invariant with the applied side gate bias
as well as the main channel length L
M
.This is an additional
advantage of the EJ-DG structure over that of the conven-
tional EJ MOSFET in which for a main channel length of
L
M
=80 nm,the threshold voltage decreases by approxi-
mately 300% when the side gate voltage is varied from 6
to 10 V [7].
3.2.Side gate design considerations
In this section,the main gate length is fixed at 50 nm
while the side gate length is varied for investigating the
design optimization in terms of threshold voltage roll-off
and hot carrier effect.
Fig.11 shows the dependence of the threshold voltage
roll-off on the variation of side gate conditions (length
and bias).It can be observed clearly that the EJ-DG struc-
ture exhibits a reverse short channel effect (RSCE),i.e.the
threshold voltage ‘‘rolls-up’’ when the side gate length is
decreased for a fixed main gate length L
M
.The threshold
voltage roll-up occurs because as the side gate length
decreases,the influence of asymmetrical double gate region
(side gate region) on the symmetrical double gate region
(main gate region) reduces leading to an increase in the
threshold voltage.This unique feature of the EJ-DG struc-
ture is an added advantage when the device dimensions are
continuously shrinking.It is worth noting that the side gate
bias affects the threshold voltage only marginally as already
shown in Fig.10.
For investigating the hot carrier effects in the EJ-DG
structure,a comparison in terms of the vertical electric field
and the electron temperature is performed.Fig.12 shows
the vertical field in the side gate region along A–A
0
cut line
located at 5 nmfrom the side gate region on the drain side.
It can be seen that the peak electric field at the front gate
side is larger as compared to the back gate and the electric
field at the back gate side increases with decreasing the side
gate length.Fig.13 shows the electron temperature at the
silicon thin film surface for the S-DG and EJ-DG struc-
tures.Due to the high electric field under the side gate
region near the drain end,the electron temperature is dif-
ferent from the lattice temperature and this effect increases
with decreasing side gate length.Thus,the choice of side
gate length determines the extent of hot carrier effects in
the device.However,it can be seen from Fig.13 that the
electron temperature for the S-DGstructure is greater than
that of EJ-DG structure.Since the hot electron effect is
dependent on the electron temperature,it is expected that
the EJ-DG structure will be less prone to the hot electron
effect.
20 30 40 50 60
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
V
DS
=50mV
L
S
=50nm
Threshold Voltage (Volts)
Main Channel Length (nm)
V
SGS
=1V
V
SGS
=1.2V
V
SGS
=1.5V
Fig.10.Threshold voltage versus main channel length of the EJ-DG
MOSFET for channel lengths up to 20 nm with V
DS
=50 mV.
20 25 30 35 40 45 50 55 60
0.920
0.922
0.924
0.926
0.928
0.930
0.932
0.934
0.936
0.938
0.940
V
DS
=50mV
L
M
=50nm
V
SGS
=1V
V
SGS
=1.2V
V
SGS
=1.5V
Threshold Voltage (Volts)
Side gate Length (nm)
Fig.11.Threshold voltage versus side gate length of the EJ-DGMOSFET
at different side gate biases.
Fig.12.Vertical electric field profiles along the cut line A–A
0
located at
5 nm from the edge of the side gate on the drain side of the EJ-DG
MOSFET.
A.A.Orouji,M.J.Kumar/Microelectronic Engineering 83 (2006) 409–414 413
4.Conclusions
In this paper,we have proposed a novel configuration
for the symmetrical double gate SOI MOSFET using two
side gates in order to investigate the influence of extremely
shallow source and drain junctions on the short-channel
effects.A constant voltage,independent of the main gate
voltage,is applied to the side gates to forminversion layers
acting as the extremely shallow virtual source and drain.
Based on our simulation results we demonstrate that the
combination of extremely shallow junctions and double
gate structure effectively reduce the SCEs due to the sup-
pression of the charge sharing by the inversion layer under
the side gates.Our results suggest that the optimized side
gate length condition,in terms of SCEs and the hot carrier
effect,is achieved when the side gate length is equal to the
main gate length.
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0 20 40 60 80 100 120
0
500
1000
1500
2000
2500
3000
3500
4000
4500
EJ-DG (L
S
=50nm)
EJ-DG (L
S
=40nm)
EJ-DG (L
S
=30nm)
EJ-DG (L
S
=20nm)
S-DG
EJ-DG
V
DS
=1.5V
V
MGS
=0.2V
V
SGS
=1.5V
L
M
=50nm
S-DG
V
DS
=1.5
V
GS
=0.2V
L=50nm
L
M
Electron Temperature (Kelvin)
Distance from start of the Main Channel (nm)
Fig.13.Electron temperature near the front oxide and silicon interface of
the S-DG and EJ-DG MOSFETs.
414 A.A.Orouji,M.J.Kumar/Microelectronic Engineering 83 (2006) 409–414