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1

Module 4: Memory
M
anagement




Course outline:

MEMORY MANAGEMENT IN PC :

Parity


ECC


Static & Dynamic RAM


Memory Addressing


Segmented addressing
-

64 KB Limits


640 KB barrier


Logical, segmented, virtual, linear and physical memory addresses


E
xtended and
Expanded memory


Cache memory


Video memory


HMA
-

Flat memory model


Advanced
memory technologies.


Memory organization:


Figure 6
-
1.

C1assif
ication system of memory.


Computer storage
,
computer memory
, and often casually
memory

refer to
computer

components,
devices and
recording media

that retain digital
data

used for computing for some interval of time.
Computer storage provides one of the core functions of
the modern computer, that of information
retention. It is one of the fundamental components of all modern computers, and coupled with a
central
processing unit

(CPU), implements the basic
Von Neumann

computer model used since the 1940s.

In contemporary usage,
memory

usually refers to a form of
solid state

storage known as
random access
memory

(RAM) and sometimes other f
orms of fast but temporary storage. Similarly,
storage

more
commonly refers to
mass storage

-

optical dis
cs
, forms of
magnetic storage

like
hard disks
, and other
types of storage which are slower than RAM,
but of a more permanent nature. These contemporary
distinctions are helpful, because they are also fundamental to the architecture of computers in general.



2

As well, they reflect an important and significant technical difference between memory and mass
stor
age devices, which has been blurred by the historical usage of the terms "main storage" (and
sometimes "primary storage") for random access memory, and "secondary storage" for mass storage
devices. This is explained in the following sections, in which the
traditional "storage" terms are used as
sub
-
headings for convenience.


The fundamental components of a general
-
purpose computer are
arithmetic and logic un
it
,
control
circuitry
, storage space, and input/output devices. If storage is removed, a computer can only function as
a
digital signal processing

device (e.g.
calculator
,
media player
)
. The ability to store
instructions

that
form a computer program, and the information that the instructions manipulate, is what makes
stored
program architecture

computers versatile enough for general purposes.

A
digital computer

represents information using the
binary numeral system
. Text, numbers, pictures,
audio, and nearly any other form of information can be converte
d into a string of
bits
, or binary digits,
each of which has a value of 1 or 0. The most common unit of storage is the
byte
, equal to 8 bi
ts. A
piece of information can be manipulated by any computer whose storage space is large enough to
accommodate the corresponding
data
, or
the binary representation of

the piece of information
. For
example, a computer with a storage space of eight million bits, or one
megabyte
, could be used to edit a
small
novel
.

Various forms of storage, divided according to their distance from the
central processing unit
.
Additionally, common technology and cap
acity found in
home computers

of
2005

is indicated next to
some items.

Various forms of storage, based on various na
tural phenomena, have been invented. So far, no practical
universal storage medium exists, and all forms of storage have some drawbacks. Therefore a computer
system usually contains several kinds of storage, each with an individual purpose, as shown in the

diagram.





3






Parity:

A
parity bit

is a
binary digit

that indicates whether the number of bits with value of
one

in a given set of
bits is
even

or
odd
. Parity bits are used as the simplest
error detecting code
.

There are two types of parity bits:
even parity bit

and
odd parity bit
. An even parity bit is set to 1 if the
number of ones in a given set of bits is odd (making the total number of ones even). An odd parity bit is

set to 1 if the number of ones in a given set of bits is even (making the total number of ones odd). Even



4

parity is actually a special case of a
cyclic redund
ancy check

(CRC), where the 1
-
bit CRC is generated
by the
polynomial

x
+1.

Error detection:

If an odd number of bits (including the parity bit) are changed in
transmission

of a set of bits then parity
bit will be incorrect and will thus indicate that an error in transition has occurred. Therefore, parity bit is
an er
ror detecting code, but is not an error correcting code as there is no way to determine which
particular bit is corrupted. The data must be discarded entirely, and re
-
transmitted from scratch. On a
noisy transmission medium a successful transmission could
take a long time, or even never occur. Parity
does have the advantage, however, that it is about the best possible code that uses only a single bit of
space and it requires only a number of
XOR gates

to generate. See
Hamming code

for an example of an
error
-
correcting code.


Error correction Code (ECC):

An
error
-
correcting code

(
ECC
) is a
code

in which each data signal conforms to specific rules of
construction so that departures from this construction in the received signal can generally be
automatically detected and corrected. It is used in computer data
storage
, for example in
dynamic RAM
,
and in
data transmission
.

Some codes can correct a certain number of bit errors and only detect further numbers of bit errors.
Codes which can correct one error are termed single error correcting (SEC), and those which detect two
are termed double err
or detecting (DED). The simplest error correcting codes can correct single
-
bit
errors and detect double
-
bit errors. There are codes which can correct and detect more errors than these.

An error
-
correcting code which corrects all errors of up to
n

bits corr
ectly is also an error
-
detecting code
which can detect at least all errors of up to 2
n

bits.

Two main categories are
convolutional codes

and
block codes
. Examples of the latter are
Hamming
code
,
BCH code
,
Reed
-
Solomon code
,
Reed
-
Muller code
,
Binary Golay code
, and
turbo code
.

Shannon's theorem

is an imp
ortant theorem in error correction which describes the maximum attainable
efficiency of an error
-
correcting scheme versus the levels of noise interference expected. In general,
these methods put redundant information into the data stream following certain
algebraic or geometric
relations so that the decoded stream, if damaged in transmission, can be corrected. The effectiveness of
the coding scheme is measured in terms of
code rate
, which

is the code length divided by the useful



5

information, and the
Coding gain
, which is the difference of the
SNR

levels of the uncoded and coded
systems required to reach the same
BER

levels.


Static RAM

Static random access memory

(SRAM) is a type of
semiconductor

memory. The word "static"
indicates that the memory retains its contents as long as power remains applied, unlike dynamic RAM
(
DRAM
) that needs to be periodically
refreshed

(nevertheless, SRAM should not be confused with
read
-
only memory

and
flash memory
, since it is
volatile memory

and preserves data only while power is
continuously applied). SRAM should not be confused with
SDRAM
, which stands for
synchronous
DRAM

and is entirely different from SRA
M, or with pseudostatic RAM (
PSRAM
), which is DRAM
disguised as SRAM.


Dynamic RAM

Dynamic random access memory

(
DRAM
) is a type of
random access memory

that stores each
bit

of
data in a separate
capacitor

within an
integrated circuit
. Since real capacitors leak charge, the
information eventually fades unless the capacitor charge is refreshed periodically. Because of this
refresh requirement, it

is a
dynamic

memory as opposed to
SRAM

and other
static

memory. Its
advantage over SRAM is its structural simplicity: only one transistor and a capac
itor are required per bit,
compared to six transistors in SRAM. This allows DRAM to reach very high
density
. Since DRAM
loses its data when the power supply

is removed, it is in the class of
volatile

memory devices.

PC memory organization:





6

Conventional memory


DOS:




Addressing:

8088


1mb (2
20

address lines)

80286


real mode


1m

-

protected mode


16m

80386


real mode
-

1m

-

above protected mode


up to

4GB


640kb


used for OS

384kb


reserved for addressing bios, video RAM, I/O etc…





7

Conventional memory is reserved for operating system and user data and upper memory area is reserved
for BIOS and I/O addressing. Initially the capacity was 1mb. In real m
ode only 1mb is used and later it
was extended to 16mb.


High memory area



Size 1m+64



There are 21 pins in 8088. using these 21 pins this area can be accessed.


Conventional memory:



Interrupt vector: contains the address of all interrupts. (part of hard
ware)



IO.SYS: bios interface between the bios and the OS



MSDOS.SYS: kernel of the dos operating system



Buffer cache: stores the file in it in the form of file allocation table



Device management: software to operate different devices



Command.com is like the

shell of the operating system



Resident portion cannot be over written.



TSR programs: Terminate, Stay, Resident programs converts user defined language inputs to
machine language.



User programs: user programs are stored here



Transient: it can be over wri
tten and is not fixed


Extended memory:



All memory above 1mb is known as extended memory



Windows xp onwards dos based os can directly accesses extended memory



Windows 3.1, 95, 98, ME must co
-
ordinate their accesses to extended memory through the use
of an

external memory manager



It uses xms protocol [used for only dos utilities]



Most commonly used manager is himem.sys [ up to windows 98 first dos is booted and then
windows]



High memory area can be accessed by segmented address/offset addressing by working
80286 in
real mode.


Memory:




8

1.

Static

Refresh circuit is not required.

Advantages


high speed (no capacitor)

Disadvantages


high cost (made up of transistor)

2.

Dynamic

Refresh needed (so need special circuit known as refresh circuit)

All pc use DRAM for t
heir main memory


Memory Errors:

Repeatable/hard errors: physical damage of memory module

Transient/soft errors:
due to some charge changes (these errors are not repeated)


Memory error detection and correction:

Parity memory and ECC memory are to over com
e soft errors


Different addressing:

Logical:


In computer networks, a
logical address

refers to a
network layer

address such as an
IP address
, an
X.25
/
X.121

or
IPX

address.

In
computer architectures
, a
logical address

or
virtual address

is a memory location accessed by an
application program

in a system with
virtual memory

such that intervening
computer hardware

and/or
software maps the virtual address to
real (physical) memory
. During the course of
execution

of an
application, the same virtual address may be mapped to many different physical addresses as
data

and
programs are
paged

out and paged in to other locations.

Segmented:

An
address space

logically

divided into s
ections, called
segments.

To access a particular memory
location, a program must specify both the segment number and the
offset

within that segment. In
contrast, a
flat address space

consists of s
imple memory addresses that start at 0 and increment to the
maximum address.




9

Segmentation

is one of the most common ways to achieve
memory protection
; another common one
is
paging
. Segmentation means that a part or parts of the memory will be sealed off from the currently
running
process
, through the use of
hardware registers
. If the data that is about to be read or written to is
outside the permitted
address space

of that process, a
segmentation fault

will result.

This usage should not be confused with that of the
memory segments

used by early
x86

processor
architectures.

For details of
x86
's implementation of segmentation in both 16
-
bit and 32
-
bit mode, please see the
article on
memory segments
.

Segmentation is a memory
-
management scheme that supports
this user view of memory. A logical
address space is a collection of segments. Each segment has a name and a length. The address specifies
both the segment name and the offset within the segment. The user therefore specifies each address by 2
parameters
: a segment name and an offset.


Linear address:

A memory addressing scheme used in processors where the whole memory can be accessed using a
single address that fits in a single register o
r instruction. This contrasts with a
segmented memory

architecture, such as that used on the
Intel 8086
, where an address is given by an offset from a base
address held in one of the "segment registers". Linear addressing greatly simplifies programming at the
assembly language

level but requires more instruction word bits to be allocated for an address.


Physical address:

In computers, a
physical address

or
binary address

is the value of the
finite

monotonically or
dered
binary

number

presented on the
computer
's
main memory

control structure called a
computer
address
bus

which is used electronically by the circuitry to directly enable a
particular memory storage cell

(itself part of the circuitry) using other boolean logic circuitry, the Memory Management Unit (MMU).
It is distinct from a
memory address

only in that the term "Memory address" in practice include both
virtual

and physical addresses.


Vir
tual address:




10

In
computer

terminology a
virtual address

is an address identifying a virtual (non
-
physical) entity. The
term virtual address is most commonly used for
virtual memory

or
virtual network address
.
Virtual
memory

is an addressing
scheme implemented in hardware and software that allows non
-
contiguous
memory to be addressed as if it were contiguous. The technique used by all current implementations
provides two major capabilities to the system:

1.

Memory can be addressed that does not c
urrently reside in main memory and the hardware and
operating system will load the required memory from auxiliary storage automatically, without
any knowledge of the program addressing the memory, thus allowing a program to reference
more (RAM) memory than

actually exists in the computer.

2.

In multi tasking systems, total memory isolation, otherwise referred to as a discrete address
space, can be provided to every task except the lowest level operating system. This greatly
increases reliability by isolating p
rogram problems within a specific task and allowing unrelated
tasks to continue to process.


In short:
-

There are 5 types of addressing schemes. They are :
-

1.

Logical memory address
-

Used by programs

2.

Segmented memory address


used in real mode

3.

Virtual me
mory address


used in protected mode by using selector descriptor table

4.

Linear memory address


address computer by CPU

5.

Physical memory address


address that is used to address physically. MMU converts
into physical address. In 80386 paging is used to ma
p physical to linear address.


More about Virtual memory:

Virtual memory

is an addressing scheme implemented in hardware and software that allows non
-
contiguous memory to be addressed as if it were contiguous. The technique used by all current
implementati
ons provides two major capabilities to the system:

1.

Memory can be addressed that does not currently reside in main memory and the hardware and
operating system will load the required memory from auxiliary storage automatically, without
any knowledge of the
program addressing the memory, thus allowing a program to reference
more (RAM) memory than actually exists in the computer.




11

2.

In multi tasking systems, total memory isolation, otherwise referred to as a discrete address
space, can be provided to every task e
xcept the lowest level operating system. This greatly
increases reliability by isolating program problems within a specific task and allowing unrelated
tasks to continue to process.

Overview

Hardware must have two methods of addressing RAM, real and virtua
l. In real mode, the memory
address register will contain the integer that addresses a word or byte of RAM. The memory is addressed
sequentially and by adding to the address register, the location of the memory being addressed moves
forward by the number b
eing added to the address register. In virtual mode, memory is divided into
pages usually 4096 bytes long (see
page size
). These pages may reside in any available RAM location
that can b
e addressed in virtual mode. The high order bits in the memory address register are an index
into page
-
mapping tables at specific starting locations in memory and the table entries contain the
starting real addresses of the corresponding pages. The low ord
er bits in the address register are an offset
of 0 up to 4,095 (0 to the page size
-

1) into the page ultimately referenced by resolving all the table
references of page locations.

The size of the tables is governed by the computer design and the size of R
AM. All virtual addressing
schemes require the page tables to start at a either a fixed location or one identified by a register. In a
typical computer, the first table will be an array of addresses of the start of the next array; certain high
-
order bits o
f the memory address register will be the index into the first array. Depending on the design
goal of the computer, each array entry can be any size the computer can address. The next bits will be an
index into the array resolved by the first index. This s
et of arrays of arrays can be repeated for as many
bits that can be contained in the memory address register. The number of tables and the size of the tables
will vary by architecture, but the end goal is to take the high order bits of the virtual address
in the
memory address register and resolve them to an entry in the page table that points to either the location
of the page in real memory or a flag to say the page is not available.

Paging

If a program references a memory location that resolves within a
virtual page

not available, the
computer will generate a
page fault
. The hardware w
ill pass control to the operating system at a place
that can load the required page from auxiliary storage (
e.g.
, a paging file on disk) and turn on the flag to



12

say the page is available. The hardware will then take the start location of the page, add in t
he offset of
the low order bits in the address register and access the memory location desired.

All the work required to access the correct memory address is invisible to the application addressing the
memory. If the page is in memory, the hardware resolve
s the address. If a page fault is generated,
software in the operating system resolves the problem and passes control back to the application trying
to access the memory location. This scheme is called
paging
.

Translating the memory addresses

To minimize the performance penalty of address translation, most modern CPUs include an on
-
chip
Memory Managem
ent Unit
, or MMU, and maintain a table of recently used virtual
-
to
-
physical
translations, called a
Translation Lookaside Buffer
, or TLB. Addresses
with entries in the TLB require
no additional memory references (and therefore time) to translate. However, the TLB can only maintain
a fixed number of mappings between virtual and physical addresses; when the needed translation is not
resident in the TLB,

action will have to be taken to load it in.

On some processors, this is performed entirely in hardware; the MMU has to do additional memory
references to load the required translations from the translation tables, but no other action is needed. In
other p
rocessors, assistance from the operating system is needed; an exception is raised, and the
operating system handles this exception by replacing one of the entries in the TLB with an entry from
the primary translation table, and the instruction which made t
he original memory reference is restarted.

Protected memory

Hardware that supports virtual memory almost always supports
memory protection

mechanisms as well.
The MMU may

have the ability to vary its operation according to the type of memory reference (for
read, write or execution), as well as the
privilege mode

of the CPU at the time the mem
ory reference
was made. This allows the operating system to protect its own code and data (such as the translation
tables used for virtual memory) from corruption by an erroneous application program and to protect
application programs from each other and (
to some extent) from themselves (e.g. by preventing writes to
areas of memory that contain code).




13

Difference between extended and expanded memory

Extended memory

Memory addresses greater than or equal to one
m
egabyte

are called extended memory. The 8088 and
8086 PCs can't have extended memory because these chips can access only addresses of less than one
megabyte (1MB) in size.

With the minor exception of the High Memory Area (HMA), extended memory can be addr
essed only
by applications run in real mode. It is possible, however, for DOS applications to make use of this
memory to store data (but not to execute code directly from there). XMS (eXtended Memory Standard,
promulgated by Microsoft) permits applications

to allocate extended memory and takes care of copying
data to and from extended memory and conventional memory so that the application does not have to
worry about switching between modes. Like EMS, XMS usually requires loading a device driver of
some sor
t. Extended memory is limited to 15Mb on 286es and 386SXes (15Mb extended plus 1Mb
conventional and upper memory equals 16Mb, or 2
24
, 24 being the number of address lines coming out
of the CPU), limited to 4 gigabytes (2
32
) for 386DX chips and up, although

very few motherboards have
been designed to hold that much memory.

Expanded memory

Expanded memory is addressed from within the lower 1MB space, usually above 640K. It is sometimes
up to 64K of real addresses but this is just a small portion of the whole
expanded memory, which can be
very large. The expanded memory requires hardware and/or software that maps the expanded memory to
a piece of address space, in what is called a "page frame". Extended memory can be used as expanded
memory by using software an
d the 80286 or 80386 chips to "remap" it to the lower 1MB. It should be
noted that the 80386 chip has hardware built in that supports expanded memory while the 80286 chip
does not. Software that will convert extended memory on an 80286 machine to expanded
memory may
result in a significant performance penalty, if the machine does not have special hardware support for
expanded memory. Software that will convert extended memory to expanded memory on an 80286
machine is not written to use the special hardware
built into the 80386 chip, so the same type of
performance penalty may apply.

Hardware supported expanded memory is the fastest form of expanded memory and is available directly
on all 80386SX or better IBM compatibles running the proper software. It is al
so available on some



14

80286 machines with special chip sets or 80286 machines equipped with a hardware memory manager
add
-
on. Lastly, it is available in a large number of memory expansion boards for all IBM compatible
machines, including the 8088/8086 machi
nes.

Expanded memory standards

When looking at expanded memory, one must also take into account such factors as the type of
expanded memory being made available. The first widely accepted standard was the Lotus
-
Intel
-
Microsoft Expanded Memory Specification

(LIM EMS) version 3.2. This provided a way for programs
to store information in expanded memory, but did not allow for efficient movement of information or
the storing of the actual program. Lotus 1
-
2
-
3, for example, could store only cell labels and not v
alues in
expanded memory, restricting the real value of this type of expanded memory. Other standards that were
developed later included AST's Enhanced Expanded Memory Specification (EEMS) and IBM's
Expanded Memory Adapter (XMA). Once combined under LIM EM
S version 4.0, these allowed better
use of expanded memory. The features in LIM EMS 4.0 include increased page size and the ability to
position the page windows anywhere in memory. Version 4.0 allowed programs to load executable code
into expanded memory,
since the page could be made to appear to be from memory in the 0
-
640K DOS
memory range.

Most memory boards currently offer some sort of LIM EMS 4.0 support but you will still pay a
performance penalty unless the board offers full hardware support for LIM
EMS 4.0. (Some boards offer
software drivers to give the board LIM EMS 4.0 compatibility.)

Under DOS, applications must explicitly use either expanded or extended memory. Lotus 1
-
2
-
3 release
3.1 and Microsoft Windows require that extended memory be availab
le in order to operate. Most other
DOS programs will use expanded memory only to get around the DOS 640K barrier. Some of the
commercial memory management software for the 80386 chip will actually switch memory from
expanded to extended memory if a program

asks for it.

Under OS/2 or Unix, there is no need for expanded memory because you do not run them on 8088s. The
term "extended" memory loses meaning because
all

the physical memory is available and is allocated to
the programs as needed.

Cache memory:




15

In
computer science
, a
cache

(
pronounced

"cash"
/kæ
ʃ
/
[1]
) is a collection of data duplicating original
values stored elsewhere or computed earlier, where the original data is expensive to fetch (due to slow
access time
) or to compute, relative to the cost of reading the cache. In other words, a cache is a
temporary storage area where frequently accessed data can be stored for rapid access. Once the data is
stored in

the cache, future use can be made by accessing the cached copy rather than re
-
fetching or
recomputing the original data, so that the average access time is lower.

Caches have proven to be extremely effective in many areas of computing because access patte
rns in
typical
computer applications

have
locality of reference
. There

are several kinds of locality, but this
article primarily deals with data that are accessed close together in time (
temporal locality
). The data
might or might not be locate
d physically close to each other (spatial locality).

Video Memory:

Video memory

is a term generally used in
computers

to describe some form of writable memory,
usually
RAM
, dedicated to the purpose of holding the information necessary for a
graphics card

to drive
a
display device
. In modern 3D graphics cards, the video memory may also hold 3D vector data,
textures
, backbuffers,
overlays

and
GPU

programs.

This memory sometimes takes the form of dedicated memo
ry chips integrated in the
framebuffer
, and
sometimes takes the form of a
Share
d Memory Architecture

(SMA).

HMA:

Short for
High Memory Area
,
HMA

is the first 64KB (65,520 bytes) of extended memory above the
first 1MB of memory found on IBM compatible computers. The HMA can be used to swap programs
from conventional memory into HMA c
ausing the computer to think more conventional memory is
available on the computer.

In MS
-
DOS, the HMA can be accessed using Microsoft's HIMEM.SYS file and specifying the
DOS=HIGH command in the config.sys. Additional information about the Autoexec.bat an
d Config.sys
can be found on our
Autoexec.bat / Config.sys page
.

Flat memory model:




16

In computer systems design, a flat memory model refers to a linear addressing
paradigm
, such that the
CPU

can directly (and sequentially) address all of the available memory locations, without having to
resort to any sort of memory segmentation or pag
ing schemes.

Memory management and logical to physical address translation can still be implemented
on top of

a flat
memory model in order to facilitate the
operating system
's functionality, resource protection,
multi
-
tasking

or to increase the memory capacity beyond the limits imposed by the processor's physical
address space, but the key feature
of a flat memory model, is that the entire memory space is linear,
sequential and contiguous from address zero to MaxBytes
-
1.

Memory management is therefore
possible
,
optional
, but
not necessary

nor dictated by the CPU
architecture:



In a simple controller,

or in a
single tasking

embedded application, where memory management
is not needed nor desirable, the flat memory model is the most appropriate, because it provides
the simplest interface from the programmer's point of view, with direct access to all memo
ry
locations and minimum design complexity.



It a general purpose computer system, which requires multi
-
tasking, resource allocation and
protection, the flat memory system must be augmented by some memory management scheme,
which is typically implemented th
rough a combination of dedicated hardware (inside or outside
the CPU) and software built into the operating system. The flat memory model (at the physical
addressing level) still provides the greatest flexibility for implementing this type of memory
manage
ment.

The vast majority of processor architectures do implement a flat memory design, including all early 8
-
bit
processors, the Motorola 68K series ... etc. The original Intel 8086 was an exception to this rule which
implemented a
segmented

memory model, b
ecause it provided an easy form of memory management
with flexible page boundaries for early operating systems such as DOS.

Most modern memory models fall into one of three categories:



Flat memory model:

o

Simple interface for programmers, clean design.

o

Gre
atest flexibility

o

Minimum hardware and CPU real estate for simple controller applications




17

o

Maximum execution speed

o

Not suitable for general computing or multi
-
tasking operating systems, unless enhanced
with additional memory management hardware/software, bu
t this is almost always the
case in modern
CISC

processors, which implement advanced memory management and
protection technology over a flat memory model.



Paged memory model:

o

Suitable for multita
sking, general operating system design, resource protection and
allocation.

o

Suitable for virtual memory implementation.

o

More CPU real estate, somewhat lower speed

o

More complex to program

o

Rigid page boundaries, not always the most memory efficient.



Segmente
d memory model:

o

Similar to paged memory, but paging is achieved by the implicit addition of two
relatively shifted registers:
segment:offset

o

Variable page boundaries, more efficient and flexible than the paged memory model

o

Quite complex and awkward from a

programmer's point of view

o

More difficult for compilers.

o

Pages can overlap / poor resource protection and isolation

o

Many to one address translation correspondence: Many
segment:offset

combinations
resolve to the same physical address

o

Greater chance of pro
gramming errors

o

Implemented in original Intel 8086, 8088, 80186, 80286 and supported by 80386 and all
subsequent x86 machines through to present day Pentium and Core 2 processors. This
memory model has remained ever since in the x86 machines, which now pro
vide multi
-
mode operation and rarely operate in the compatible segmented mode anyway.