Metal-catalyzed silicon nanowires: Growth and devices

internalchildlikeInternet και Εφαρμογές Web

12 Νοε 2013 (πριν από 3 χρόνια και 7 μήνες)

116 εμφανίσεις

Ted Kamins

Principal Scientist

Quantum Science Research

Hewlett
-
Packard Laboratories

Palo Alto, California


with Nate Quitoriano


www.hpl.hp.com/research/qsr


Presented to

French Delegation Visiting HPL

December 6, 2007

Metal
-
catalyzed silicon nanowires:


Growth and devices

Image processed with the assistance of Gio Medeiros
-
Ribeiro
-

HPL and LNLS

M. Saif Islam, S. Sharma, T. I. Kamins, and R. Stanley

Williams, Nanotechnology
15
, L5
-
L8 (May 2004)

Transistors per Chip

CMOS scaling

10
100
1000
10000
1970
1975
1980
1985
1990
1995
2000
2005
2010
Year
Feature Size (nm)
Minimum Feature Size

Feature size (nm)

Year

1972

1980

1988

1996

10
3

10
4

10
5

10
6

10
7

10
8

10
9

Year

Transistors per Chip

4004

8080

8086

80286

80386

80486

Pentium

Pentium Pro

Pentium 3

2004

Pentium 4

CMOS scaling: Cost and functionality



Cost of fabrication facility


Limits number of companies building ICs

Lithography is main cost


193 nm immersion stepper: US $45M



Use self
-

and directed
-
assembly to
extend Moore's law
(“more Moore”)


and

add functionality
(“more than Moore”).


Determine critical dimensions by choice of materials and


deposition kinetics ("self assembly"), not lithography


Use lithography to position devices or arrays of devices


("directed assembly")

Self
-

and directed
-

assembly


Nanowire growth on catalytic nanoparticles


Growth, devices, and integration

Moore's “Second Law”

Year

IC Fabrication

Facility Cost ($B)

1995

2005

2010

1

10

100

2000

CMOS scaling: Cost and functionality



Cost of fabrication facility


Limits number of companies building ICs

Lithography is main cost


193 nm immersion stepper: US $45M



Use self
-

and directed
-
assembly to
extend Moore's law
(“more Moore”)


and

add functionality
(“more than Moore”).


Determine critical dimensions by choice of materials and


deposition kinetics ("self assembly"), not lithography


Use lithography to position devices or arrays of devices


("directed assembly")

Self
-

and directed
-

assembly


Nanowire growth on catalytic nanoparticles


Growth, devices, and integration

Moore's “Second Law”

Year

IC Fabrication

Facility Cost ($B)

1995

2005

2010

1

10

100

2000

Topics (not in sequence)

Metal
-
catalyzed (mostly) Si nanowires:


Growth and devices

Basic idea of nanowire growth

Growth: Si and Ge


Catalyst nanoparticles: Material, position, size control

Nanowires in 2007 edition of ITRS

Field
-
effect devices


Transistors and sensors


Doping and surface states

Connecting nanowires: Integration


Sensors


Field
-
effect sensors (possibly integrated with CMOS)


Resonant nanowire sensors

Optoelectronic / photonic devices


Integrating compound semiconductors on an IC (InP/Si)

Sequential steps in nanowire growth

Si substrate

Metal catalyst

particle (eg, TiSi )

2

SiH

4

Si

H

H

2

Si

Gas transport

Catalyzed surface reaction

Diffusion (bulk or surface)

Precipitation

SiH

4

Si nanowire

Metal nanoparticle

Catalyst nanoparticle can be in liquid

or solid state during nanowire growth

Si wire

TiSi
x

Ti

Cu

Si

At tip

~2 diameters


below tip

Ti

Cu

Si

TiSi

x

Si

Analysis by

Thorsten Hesjedal (Stanford University / Univ. of Waterloo)

David Basile (Hewlett
-
Packard)

Energy
-
Dispersive

X
-
Ray Spectroscopy

Single
-
crystal Si nanowire with metal


(TiSi
x
) catalyst nanoparticle at tip

Cu from TEM grid

Single
-
Crystal Wire

Amorphous Coating

(~ 23 nm)

(~ 2.4 nm)

<111>

T. I. Kamins, et al, J. Appl. Phys.
89
, 1008 (15 Jan. 2001)

Metal
-
catalyzed Si and Ge nanowires

Diameter: 5 nm


300 nm (at least)

Random or epitaxial alignment

Aspect ratio for straight nanowires > 1000:1

Nanowire diameter depends on


Catalyst nanoparticle size


Nanowire growth conditions

1

m

500 nm

1.5
µ
m

5
µm

Au NanoP+Bake

+ NW (363
-
3)

2
µ
m

Metal
-
catalyzed Si and Ge nanowires

Diameter: 5 nm


300 nm (at least)

Random or epitaxial alignment

Aspect ratio for straight nanowires > 1000:1

Nanowire diameter depends on


Catalyst nanoparticle size


Nanowire growth conditions

1

m

500 nm

1.5
µ
m

5
µm

Au NanoP+Bake

+ NW (363
-
3)

2
µ
m

Quantum regime

22 nm node and beyond

Low
-
dimensional materials section
includes nanowires and nanotubes

Application

Potential Material Value

Key Challenges

Devices: 1D Memory
and Logic Devices

Nanotubes

exhibit ballistic
transport and potential high
performance

-
Control of bandgap and metallic vs.
semiconducting

-
Control of carrier type and concentration

-
Electrical properties must not degrade when
embedded in a dielectric

-
Control of location and orientation

-
Control of contact resistance

Nanowires

could enable
surround gate structures & novel
heterostructures

-
Control of location and orientation

-
Performance exceeding patterned materials

-
Catalyst and processing temperatures compatible
with CMOS

Interconnects and
Vias: Nanotube


Nanotubes

have ballistic
transport, high current carrying
ability, and resistance to
electromigration (EM)

-
Ability to place CNTs in precise locations and with
controlled direction

-
Ability to grow with high density*

-
Conductivity must not degrade when embedded in
a dielectric*

-
Low contact resistance*

Interconnects:
Nanowire

Single crystal smooth

metal
nanowires

could reduce grain
-
boundary and sidewall scattering

-
Ability to grow long single
-
crystal high
-
conductivity
nanowires

-
Ability to place the nanowires in precise locations
and with controlled direction

New Chapter in 2007 ITRS:


Emerging Research Materials

Preliminary draft


not for wide distribution

Field
-
effect devices:


Transistors and sensors

MOS Transistor

Sensor

NW

Dielectric

Gate

NW

Dielectric

+

+

+

+

+

+

+

Depletion mode


Normally ON transistor


Modulate conducting area:
I


D
2


Nanowire moderately doped


~10
18

cm
-
3

Accumulation or inversion mode


Normally OFF transistor


Induce surface channel:
I


D



Nanowire lightly doped


Overlap increases capacitance

Surface / interface charge

r
r
o
L
Surface (+) charges ( N
s
[cm
-
2
] )
Depleted (
-
) charges
( N
a
[cm
-
3
] )
Φ
Effective
conducting
area (
A
eff
)
Depleted region
by surface charge
r
r
o
L
Surface (+) charges ( N
s
[cm
-
2
] )
Depleted (
-
) charges
( N
a
[cm
-
3
] )
Φ
Effective
conducting
area (
A
eff
)
Depleted region
by surface charge
K.
-
I Seo, S. Sharma, A. Yasseri, D. Stewart, T. I. Kamins

Electrochemical and Solid
-
State Letters
9
, G69 (2006)

Determine N
s

from dependence of


resistance on nanowire diameter

N
a

= 1.9


10
18

cm
-
3

N
s

= 2.3


10
12

cm
-
2


N
s

= 5


10


10
11

cm
-
2


Dopant concentration

Surface/interface charge density

with native oxide on surface

after thermal oxide grown

N
s

probably can be markedly reduced

0
2x10
-10
4x10
-10
6x10
-10
0
1x10
-8
2x10
-8
3x10
-8
with native
SiO
x
with thermal
SiO
2
(b)




A
eff

(
cm
2
)
Conductance-L
(
S-cm
)
Integrating nanowires

Grow nanowires in location where they will be used










Grow nanowires and then reposition them

Nanowires

Si

electrode

Si

electrode

SiO
2

5
µm

Integrating nanowires

Best integration approach depends on application


Grow nanowires in location where they will be used


Field emitters: Vertical nanowires


Integration with conventional electronics (CMOS)


Sensors: Resonant or field
-
effect


Optoelectronics: Heterogeneous integration


Grow nanowires and then reposition them


Large
-
area electronics


Metal interconnections on an integrated circuit(?)

Integrating nanowires

Best integration approach depends on application


Grow nanowires in location where they will be used


Field emitters: Vertical nanowires


Integration with conventional electronics (CMOS)


Sensors: Resonant or field
-
effect


Optoelectronics: Heterogeneous integration

Integrating nanowires

Best integration approach depends on application


Grow nanowires in location where they will be used


Field emitters


Integrate with conventional electronics
-

CMOS


Sensors: Resonant or field
-
effect


Optoelectronics: Heterogeneous integration


Critical criteria for integrating metal
-
catalyzed nanowires grown in place


Catalyst


Formation method


Size and size distribution


Materials compatibility


Nanowire growth


Temperature

OMIT: 60% vertical

OMIT: 60% vertical

Nanoimprint lithography


+ electroless deposition

Si(111) + NIL + electroless Au

Si nanowires (~top view)

Grow nanowire on substrate


Nanowires often grow in <111> directions;


ie, perpendicular to {111} surfaces


Crystal structure continuous


Good electrical connection between


grown nanowire and substrate

V

I

Si substrate

OMIT: 60% vertical

OMIT: 60% vertical

Nanoimprint lithography


+ electroless deposition

Si(111) + NIL + electroless Au

Si nanowires (~top view)

Electron emitters:

Field emission

Vertical nanowire transistors

Devices within nanowires

Q. Tang, T. I. Kamins, X. Liu, D. E. Grupp, and J. S. Harris,

Electrochem. and Solid
-
State Lett.
8
, G204
-
208 (August 2005).

-2.0E-08
0.0E+00
2.0E-08
4.0E-08
6.0E-08
8.0E-08
1.0E-07
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Voltage (V)
Current (nA)
n

p

Voltage (V)

1.5

-
1.5

0

Current

Voltage (V)

-8.0E-03
-7.0E-03
-6.0E-03
-5.0E-03
-4.0E-03
-3.0E-03
-2.0E-03
-1.0E-03
0.0E+00
1.0E-03
-1.5
-1
-0.5
0
0.5
1
1.5
Voltage (V)
Current (mA)
p

n

1.5

-
1.5

0

Current

Voltage (V)

1.5

-
1.5

0

Current

n

p

n

Within nanowire

p
-
n junction in vertical nanowire

At nanowire/substrate interface

V
g

= 1V

0.5 V

0 V

-
0.5 V

0.2

-
0.2

0

Drain voltage (V)

-
1

0

1

Drain current (
µ
A)

Si substrate

G

S

D

SiO
2

SiO
2

W

Surrounding gate to control current

Connecting both ends of nanowires:


Bridging nanowires

M. Saif Islam, S. Sharma, T. I. Kamins, and R. Stanley

Williams, Nanotechnology
15
, L5
-
L8 (May 2004)

Au catalyst

Ti catalyst

Growth direction

Non
-
planar surface:


Pre
-
formed nanocrystals in colloid

Advantages

Nanowire diameter and length uniformity

Useful for wide range of diameters

Independent control of size and density

Negatively charged

Top View

Trench

1.5
µ
m

N. J. Quitoriano and T. I. Kamins, J. Appl. Phys.
102
, 044331 (2007);


Fall 2007 MRS Meeting, paper JJ1.2

Positioning nanoparticles using


electric field at p
-
n junction

n+

p
-

++++

-

-

-

-

-

Cross sectional SEMs


~along trench

~trench face

Nanowires

5
µm

5
µm

Positioning nanoparticles using


electric field at p
-
n junction

5
µm

5
µm

SOI platform for bridging nanowires

Nanowire

(110)
-
SOI

Electrodes

Insulator

S

D

Gate insulator

+

-

E

Si NW

Selective coating

Barrier layer

Si nanowires

Can control diameter (10


200 nm)


Properties of Si well known. Can dope controllably


Surface passivation techniques well known


Low interface
-
state density

Use bridging nanowires for transistors or sensors


Grow nanowires between two electrodes on SOI substrate

Possibly integrate nanowires with CMOS


Nanowires: Sensors


CMOS: Amplification and computation

Bridging nanowire vapor sensor

Si
-
nanowire
SiO
2
p
-
Si
p
-
Si
Si
sub.
I
V
Al
Al
Si
-
nanowire
SiO
2
p
-
Si
p
-
Si
Si
sub.
I
V
Al
Al
Suspended nanowire to reduce boundary
-
layer effects

Mechanical strength to withstand fluid flow

Bridging nanowire vapor sensor

Si
-
nanowire
SiO
2
p
-
Si
p
-
Si
Si
sub.
I
V
Al
Al
Si
-
nanowire
SiO
2
p
-
Si
p
-
Si
Si
sub.
I
V
Al
Al
Vacuum
HCl
HCl
HCl
HCl
HCl
NH
3
NH
3
NH
3
NH
3
NH
3
NH
3
HCl
H
2
O
Vacuum
HCl
HCl
HCl
HCl
HCl
NH
3
NH
3
NH
3
NH
3
NH
3
NH
3
HCl
H
2
O
Time (s)

Current

Pump

Successive exposures to


saturated HCl and NH
3

vapors

50 Torr total pressure

Pumped to < 2 mTorr between


vapor exposures

Need barrier layer and selective coatings

T. I. Kamins, S. Sharma, A. A. Yasseri, Z. Li, and J. Straznicky,

Nanotechnology
17
, S291
-
S297 (14 June 2006).

Assume sensor mimicking human nose requires 1000 sensors


Too many to connect discrete wires to individual sensors: Integrate


1000 sensors + electronics (op
-
amp, ADC, Mux) fit on a 1 cm
2

chip

How to integrate?


Fabricate electrodes on SOI


Fabricate transistors in substrate between electrodes or in SOI


Grow nanowires (<400

C); possible with Ge, possibly with Si


Sensor system concept

Sensors

Initial

processing

Additional

processing

Off
-
chip

connections

Sensor

Reference

4
-
6 bit

A/D

Op
-
Amp

Mux

20
-
30

100
-
500

Transistors

Nanowire sensor structure
:

Mechanical resonance of cantilever

f
0

f

Response


f

f
0

f
1

Response

Si substrate

Si substrate

Nanowire

High surface area

Low mass: Sensitive to added mass


Nanowires grow perpendicular


to (111)
-
oriented sidewall

Cantilevered (single
-
clamped) or


bridging (double
-
clamped) nanowires

with Stephane Evoy, Miro Belov, Wayne Hiebert

Canadian National Institute of Technology

Resonant response

Nanomechanical resonance

0

20

40

60

80

1.6075

1.6076

1.6077

1.6078

Frequency (MHz)

Amplitude (
µ
V)


f

Mass sensitivity

=

m = M
0

f

/
f
0

= M
0
/Q


M
0
=




D
2

L/4 ~ 7x10
-
14

g for D = 100 nm, L = 4
µm



m = M
0
/Q = 3x10
-
18

g

High Q

related to


Narrow diameter cantilever (less damping from air and squeezing)


Good connection to supporting post (avoids clamping loss)




E
L
D
f
2
2
0
8

Q = f
0
/

f


~ 1.60764 MHz / 60 Hz


~ 25,000

E

~ bulk value

Quality factor

0

5000

10000

15000

20000

25000

Pressure (Torr)

Quality factor Q

10
-
4

0.001

0.01

0.1

1

10

100

1000

Nanomechanical resonance

and pressure

Weak dependence of quality factor Q on pressure



Q ~
10
-
15% up to 100 Torr



Q
<3X at atmospheric pressure

Unlike micro
-
scale resonators: Damping from air and squeezing

Similar weak pressure dependence at nanoscale recently reported:


Li, Tang, and Roukes, Nature Nanotechnology
2
, 114 (2007)


Karabacak, Yakhot, and Ekinci, Phys. Rev. Lett.
98
, 254505 (2007)

As computing becomes distributed, sensors should be


integrated adjacent to the computing elements

Semiconductor nanowires for sensors


Lateral growth between pre
-
formed electrodes

Good electrical and mechanical connection

Field
-
effect sensors:


Controllable doping in nanowire


Low surface/interface state density

Resonant sensors:


High quality factor Q


Weak pressure sensitivity of Q

Self
-
assembled silicon nanowires


as an enabler for nanoscale sensors

Si nanowires: Precursors: Si
2
H
6
, SiH
4
, SiH
2
Cl
2
, SiCl
4


Typically grow in ~600

C temperature range


Compatible with partially processed CMOS


For compatibility with fully processed CMOS need T<400

C


Consider Ge instead of Si

1

m

1

m

500 nm

337C (416
-
1)

500 nm

(100) substrate

(111)
-
4


獵扳瑲s瑥

Ge nanowires: Precursor: GeH
4


Growth temperature ~330

C (Can be grown below 300

C)

Heterogeneous Integration

10s nm

III
-
V material

Si (111) substrate

~
µ
m

Heterogeneous Integration

Small cross section


Accommodates


Lattice mismatch strain (8% for InP/Si)


Thermal expansion mismatch


Allows single domain


Growth of high
-
quality III
-
V materials on Si


could lead to new optoelectronic nanodevices;




especially integrated electronics


Materials grown on Si substrate (partial list)


GaP, GaAs, InP, InN

Agilent Laboratories

Molecular Technology Laboratory


S. S. Yi, G. Girolami, J. Amano, M. Saif Islam,
S. Sharma,I. Kimukin, and T. I. Kamins, Appl.
Phys. Lett
89
, 133121 (2006).

Epitaxial growth of III
-
V nanowires on Si substrate

6
µ
m

1
µ
m

Si (111)

[111]

Epitaxial growth of InP

nanowires on Si(111) substrates

Agilent Laboratories

Molecular Technology Laboratory


<111>

0.338 nm

High
-
resolution transmission

electron micrograph

S. S. Yi, G. Girolami, J. Amano, M. Saif Islam,
S. Sharma,I. Kimukin, and T. I. Kamins, Appl.
Phys. Lett.
89
, 133121 (2006).

Si electrodes

SiO
2

Si

Si

Si

10
µ
m

Si

Si

SiO
2

Top View

InP nanobridge between isolated

Si electrodes

Physical connection: Good

Electrical connection: ?

Agilent Laboratories

Molecular Technology Laboratory


S. S. Yi, G. Girolami, J. Amano, M. Saif Islam,
S. Sharma,I. Kimukin, and T. I. Kamins, Appl.
Phys. Lett.
89
, 133121 (2006).

Physical connection: Good

Electrical connection: ?


Consider band structure

Topics (not in sequence)

Metal
-
catalyzed (mostly) Si nanowires:


Growth and devices

Basic idea of nanowire growth

Growth: Si and Ge


Catalyst nanoparticles: Material, position, size control

Nanowires in 2007 edition of ITRS

Field
-
effect devices


Transistors and sensors


Doping and surface states

Connecting nanowires: Integration


Sensors


Field
-
effect sensors (possibly integrated with CMOS)


Resonant nanowire sensors

Optoelectronic / photonic devices


Integrating compound semiconductors on an IC (InP/Si)

Metal
-
catalyzed Si (and Ge) nanowires:

Control and connection

HP Labs contributors to nanowire growth and applications:


Nate Quitoriano


Post
-
doctoral research associate


Shashank Sharma (Now at Spansion)


Amir Yasseri (Now at Lam Research)


Saif Islam (Now at UC Davis)


Xuema Li


Process engineer


Tan Ha


Equipment engineer


Cuong Le


Equipment engineer


Work primarily supported by


Hewlett
-
Packard Laboratories

with additional support from


Defense Advanced Research Projects Agency (DARPA)


Province of Alberta through National Institute of Nanotechnology

Acknowledgments