Nanoscale silicon Transistors

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2 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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Nanoscale silicon Transistors


By

Nabil Hassani

Tai Vo

The point
-
contact transistor


-

Created in 1947 by Walter
Brattain and John Bardeen.


-

Extremely simple: two foil
contacts sitting on a germanium
crystal


-

Started a new electrical
revolution.


The sandwich transistor

-
Created by William Shockley in
January, 1948 .

-
Consisted of 3 layers, n
-
type
semiconductors on the outside and
p
-
type inside

-
Current flows thru the
semiconductors controlled by the
voltage in the middle.



First Integrated Circuit


1957 Creation of Fairchild semiconductors by the
"traitorous eight,"


Created transistors without suturing or wires. And put
together several transistors in the same block of silicon
creating the integrated circuit (IC).

From Micro to Nano

Nanotechnology



Transistor creation scaled to increasingly
smaller dimensions, which results in higher
performance.


Continuing to improve performance while
decreasing power consumption of CMOS
results in a doubling of microprocessor
performance every two years.


Gordon Moore’s Predictions (1965)


The semiconductor industry continues to move
down the two
-

or three
-
year cycle in terms of
process technology, then traditional IC scaling will
last "ten years, plus or minus two years,"


Chip makers will be able to "make conventional
transistors down to the 30
-
nm range,"


Leakage and resistance problems occur past
certain size


Year of
Introduction


Transistors

4004

1971

2250

8008

1972

2500

8080

1974

5000

8086

1978

29000

286

1982

120000

Intel386

1985

275000

Intel486

1989

1180000

Intel Pentium

1993

3100000

Intel Pentium II

1997

7500000

Intel Pentium III

1999

24000000

Intel Pentium 4

2000

42000000

Intel Itanium

2002

220000000

Intel Itanium 2

2003

410000000

Scaling problems

Oxide Scaling


Gate oxide thickness in short
channel effects as MOS gate
dimensions have been reduced
from 10um to 0.1um.



Relationship between oxide
thickness (T
ox
) and channel length
(L
E
).


L
E

= 45 * T
ox


Channel length divided by gate oxide
thickness versus channel length




Thickness of the channel
depletion layer for two


devices with different
oxide thicknesses :
3.2nm and 4.5nm and
both have same off
-
state
leakage.

Scaling Limit for SiO2



The thickness limit is the same
for both materials and is not
limited by manufacturing control.
Today, it is technically feasible
to manufacture 1.5 nm and
thinner oxides on 200 mm
wafers.


Thickness limit for SiO
2

is set
instead by gate
-
to
-
channel
tunneling leakage.


--
The tunneling leakage process
for an NMOS device biased in
inversion.


Direct tunneling leakage mechanism for thin


SiO
2
.

-

Assume the gate
leakage limit occurs for
devices with 0.1um gate
length designed for 1.0V
operation, the SiO2
thickness limit occurs at
~1.6 nm.

Gate leakage versus gate voltage for various


oxide thicknesses.


The centroid for the inversion
charge is ~1.0 nm from the
SiO2/Si interface. This increases
the effective SiO
12

thickness
(T
OX
EFF) by ~0.3 nm. By taking
into account the charge
distribution on both sides of the
gate, the minimum effective
oxide thickness for a MOS
device bias in inversion at
voltages used in our 0.25 is
increased by about 0.7 nm.
Thus, the 1.6 nm oxide tunneling
limit results in an effective oxide
thickness about 2.3 nm.

Position of inversion channel charge versus


depth.




Gate and channel length versus effective oxide


thickness.



Limit for gate and channel
length for an SiO
2

gate
dielectric MOSFET is
0.1um and 0.06um




Source/Drain Engineering


Scaling of source/drain
extension (SDE) depth and
gate overlap for MOSFET’ s
of 0.1um and below


A minimum SDE to gate
overlap of 15
-
20 nm is
needed to prevent
degradation of drive current
(IDSAT)


Scaling SDE vertical depths
below 30
-
40 nm results in
little to no performance
benefit for 0.1um devices
and beyond


Terminology used in this discussion



Reducing SDE junction
depths will improve device
short channel
characteristics by reducing
the amount of channel
charge controlled by the
drain.


The potential contours for
two devices with junction
depths of 30 and 150 nm

Potential contours for two devices biased in

an off
-
state condition (a) 150 nm deep junction and

(b) 30 nm shallow junction.

SDE Junction Scaling

DNA and Transistors


A functional electronic nano
-
device has been
manufactured using biological self
-
assembly for
the first time in 2003.



Using DNA stranding properties and carbon
nanotubes to create a new generation of
transistors working in room temperature.



Components must be compatible with the
biological reactions and the metal
-
plating process.


Transistor concept in biology
application


Berkeley researchers have
developed the world's first device
that manipulates the flow of
molecules using the concept of
transistor.


single
-
electron transistor


Made in 2004 by Germans and US
scientists.


Using a vibrating silicon arm 200
nanometers long, ten of nanometres across,
and tipped with gold.


This transistor will yield to a better
understanding of nanotechnology
fundamentals.


The Latest of the Latest

Pentium 4 HT


The 90 nanometer (nm) process is the next
generation after the 0.13
-
micron process.


Integration of strained silicon to improve the
performance of transistors


1.2
-
nm gate oxide thickness .


Low

K dielectric material.


Strained Silicon

Is it ever going to be small
enough?


Questions?