CMOS for next 15 years as the mainstream of nano device technology: problems, solutions and beyond that

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2 Νοε 2013 (πριν από 3 χρόνια και 5 μήνες)

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1


CMOS for next 15 years as the mainstream
of nano device technology:

problems, solutions and beyond that





Tokyo Institute of Technology, Japan



Hiroshi IWAI


2

16Gb

NAND,
SAMSUNG

Now: After 45 Years from the 1st single MOSFETs

3

Sub
-
10 nm CMOS transistors will be realized with new technologies
anyway.


Concerns of integration such huge number of transistors.


Already 16Gbit: larger than that of world population


comparable for the numbers of neurons


in human brain


128Gbit: comparable with those of galaxies

4

Concerns for the integration


1)

Too huge power consumption, heat generation?


2)Too huge variations in transistor characteristics, which could
make the circuit design impossible?


3)Too many number of transistors for the circuit designers to
manipulate? (design crisis)


4)No merit of transistor downsizing in performance and power,
because of CR of interconnect cannot be reduced?


8)Who will pay the huge production cost?


5

JEITA IC Handbook

150mm

wafer

200mm

wafer

300mm

wafer

Front
-
end
processing
equipments

Front
-
end
processing
buildings

Back
-
end
processing
equipments

Front
-
end
ancillary
facility

Back
-
end
processing
buildings

1M

4M

16M

64M

256M

1G

Bit DRAM

Amount of capital investment (M US$)

0

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

Amount of capital investment on Each of DRAM generation

Problem is the huge production cost and investment!

6

Examples of foundry facility: UMC

UMC

7

TSMC

Volume production with lager wafer is a solution

8

Concerns for Nano
-
CMOS

integration

9

9 yrs + 2 yrs delay*

9 yrs? + 2 yrs delay?


9 yrs + ?yrs delay

675mm/2021?

450mm/2012?

300mm/2001

200mm/1990
(125/150mm
-

1981)

We are here

When does this
happen?

When do we start planning for next wafer size
transition?

10

Furnace



Height: 12 m



Weight: 36 ton



Hot zone: 40 inch



Cusp
-
type super conductive magnet

Crystal



Diameter: 400 mm



Weight: over 400 kg



Body length: over 1m

Provided by Super Silicon Crystal
Research Institute Corp.(SSi)

Crystal pulling furnace becomes too huge

Si crystal height cannot be very long because of its weight

11

2004

2005

2006

2007

2008

2009

2010

2011

2012

2004

2005

2006

2007

2008

2009

2010

2011

2012

Carrier & lot
-
size

determination

Direct Transport

Standards

Production Equipment

Standards

Factory Control

System Standards

Interoperability Testing

& Reliability Verification

450mm wafer

Standards

There is a proposed time line from 300 to 450 mm,

but huge cost, work, energy are required,

And no one can take a leadership at this moment.

12

Concerns for the integration


1)

Too huge power consumption, heat generation?


2)Too huge variations in transistor characteristics, which could
make the circuit design impossible?


3)Too many number of transistors for the circuit designers to
manipulate? (design crisis)


4)No merit of transistor downsizing in performance and power,
because of CR of interconnect cannot be reduced?


8)Who will pay the huge production cost?


13

Those

concerns

have

been

talked

about

so

many

times

and

so

many

years
.

(Like

wolf

boy!)


Hopefully,

the

status

in

which

wolf

has

not

come,

would

continues

for

future
.


Each

concern

is

a

really

cri sis

and

cri tical

problem
.


However,

each

crisis

will

not

make

completely

useless

to

make

downsizing
.


We

will

find

a

practical

solution

with

many

compromises,

such

that

water

always

fine

a

lowest

places

and

keep

running
.


14

P. P. Gelsinger, “Microprocessor for the New Millennium: Challenges,
Opportunities, and New Frontiers,” Dig. Tech. 2001 ISSCC, San Francisco,
pp.22
-
23, February, 2001

Microprocessors Trend

Today: 2002 (Intel)

Lg sub
-
70 nm

Tox 1.4 nm

f 2.53 GHz

P several 10 W

N 50 M

Heat generation

2002


10
W/cm
2

Hot plate

2006


100
W/cm
2

Surface of nuclear reactor

2010


1000
W/cm
2

rocket nozzle

2016


10000
W/cm
2

Sun surface

2008 (Intel)

Lg sub
-
25 nm

Tox 0.7 nm

f 30 GHz

P 10 kW

N 1.8B

MIPS 1M MIPS (TIPS)

Increase in


Power consumption


Heat generation

Past: 1972 (Intel)

Lg 10,000 nm

Tox 1200 nm

f 0.00075 GHz

P a few 100 mW

N 2.25k

15

1
)Power

and

heat

increase

Maybe,

it

is

not

efficient

to

increase

the

clock

frequency

and

number

of

transistors


There

will

not

be

a

big

merit

without

improving

the

operating

frequency

of

board

or

package,

and

reduce

the

power

consumed

there
.


Main

job

of

my

PC

is

editing

of

the

document

and

accessing

to

internet
.

Such

an

extremely

high

clock

frequency

should

not

be

necessary
.


Improvement

of

PC

algorithm

such

that

using

file

searching

method

of

Google

will

save

the

power

very

much
.


Downsizing

of

Printed

Circuit

Board

will

also

save

the

power
.

16

5
)

Variation

of

transistor

characteristics


System

and

circuit

design

will

assume

such

variation
.


If

too

huge

variation,

Reconfigurable

circuit

and

system

desing

can

avoid

such

transistors

with

huge

variations
.

ECC

Err潲

䍯Crecti潮

䍯Ce


睩wl

helps

a

l潴
.


䍡Cn潴

suppress

the

癡vi慴i潮

under

cert慩n

le癥l,

扵b



c慮

offer

as

many

transistors

as

the

designers

want
.


It

is

also

important

to

use

the

larger

device

in

the

circuit,

depending

on

the

usage
.

Large

gate

are

is

useful

to

reduce

the

flicker

noise
.

17

6
)Desing

crisis

for

human

power


We

could

expect

the

progress

of

CAD
.

Then,

we

can

do

only

whatever

we

can

design

in

that

period

with

the

given

manpower
.



Multi
-
level

system/circuit

design,

such

as

multi
-
core

of

microprocessor

will

save

the

human

power,

for

example
.

18

7
)

Interconnect

R

&

C



It

has

been

continuously

said

from

2

or

3

micron

meter

generations

that

interconnects

limit

the

downsizing
.

But

fortunately,

it

has

never

happened

before
.


19

8
)Huge

development

and

production

cost
.


Leading

edge

company

in

memory,

microprocessor,

DSP,

foundry

make

huge

profit
.

They

should

cover

the

coat
.


20

40000

35000

30000

25000

20000

15000

10000

5000

0



B Yen


Intel

Samsung

TI

Runesus

Toshiba

TSMC

NEC

EL

Good Profit

JEITA;

IC Handbook

Profit

Revenue

Japanese maker

Smaller profit

21

8
)Huge

development

and

production

cost
.



Leading edge company will pay the cost.


Otherwise

they

will

drop

off

from

the

existent

race,

and

the

competitor

will

be

very

happy
.


2
nd

and

3
rd

tier

companies

could

enjoy

the

reduced

cost

of

the

development

and

production,

but

no

big

profit
.

They

cannot

be

too

late

to

proceed

to

the

downsizing,

because

China

will

catch

up

soon
.

22

Future

23

Post Scaling Issue

2030

3 nm

Gate length

Post scaling period

?

24

Anyway, we will reach the downsizing limit in 15
-

20 years.


It will not happen, suddenly:


“There is no downsizing from tomorrow and you do not need
to come to company from tomorrow”


Probably, period of each generation, or node will becomes
longer and downsizing eventually approaches to the limitation.

25

After

the

limit

of

downsizing?



No,

technology

node

change,

and

then,

no

design

of

new

microprocessors?


Same

lithography

mask

can

be

used

for

many

years?


Same

equipment

can

be

used

for

many

years?


2
nd
,

3
rd

companies

and

counties

reach

to

make

the

most

advanced

microprocessors

with

cheap

cost?


Then,

price

of

microprocessors

and

even

equipments

becomes

extremely

cheap?


It

will

be

a

very

good

thing

for

microprocessor

users
.

However,

will

it

be

a

very

serious

crisis

for

advanced

countries

and

companies

in

semiconductor?



If

there

is

no

more

downsizing,

the

semiconductor

engineers

will

lose

their

jobs?

26

There

are

many

jobs

after

the

downsizing
.


Technologies

of

the

introduction

of

new

material,

new

process,

new

structure,

will

not

be

completed

in

15

years
.

Note

that

introduction

of

new

materials

usually

take

more

than

10

years
.


There

are

also

other

many

works

remain
:


Hybrid

integration,

3
D

integration,

Miniaturization

of

board
.

Efficient

algorithm

for

system
.


There

would

be

a

revolution

for

manufacturing

process


Do

we

need

big

CR?


What

would

be

a

wafer

in

future?

Is

it

the

same

as

it

is

now?



27

Size


(Gate length etc


Saturation of Downsizing

2020



5 nm



New Materials, New Process, New Structure

Logic, Memory)

Hybrid integration of different functional Chip

Increase of SOC functionality

3D integration of memory cell

3D integration of logic devices

Low cost for LSI process

Revolution for
CR,
Equipment, Wafer

Miniaturization of Interconnects on
PCB

(Printed Circuit Board)

Introduction of algorithm

of bio
-
system

Brain of insects, human

28

Thank you

for your attention!