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David Kingston

CS3100 Homework #11

1

Due: 4/18/2002

Chapter 12, Exercises 1, 3, 4, 6, 7, 8b, 8c, 14

1. Why are the page size, the number of pages in the virtual address space, and the
number of page frames in the physical address space all a power of 2 in binary machines?

In binary machines, you are dealing with bits. Each bit can have one of two value
s. It is
either set or unset. It is either zero or one. At the hardware level, this may be represented
as the presence of voltage or the absence of voltage. The voltage is on or off. If we have
one bit, we have 2^1 or 2 possible values that can be rep
resented. If we have two bits, we
have 2^2 or 4 possible values that can be represented. If we have three bits, we have 2^3
or 8 possible values. And this continues as we add bits.

As mentioned above, at the hardware level we are dealing with bits that

are represented
by the presence or absence of voltage. By keeping the page size, the number of pages in
the virtual address space and the number of page frames in the physical address space all
a power of 2, we can use the entire address space without ha
space. For example, a page size of 1K is 1024 bytes (bytes 0 to 1023). Log

2

(1024) = 10
bits. If we make the page size 1000 bytes (bytes 0 to 999), Log

2
(1000) = 9.96578 bits.
However, you cannot have a partial bit; theref
ore, you need 10 bits to represent a page
size of 1000 bytes. Note that because this is binary, we still have the capability of
representing 1024 bytes even if the page size is only 1000 bytes. In this case, the bit
sequences that represent bytes 1000 to

1023 are invalid. This is wasted address space.
The binary machine has the capability of referencing them, but because we only go to
1000 bytes instead of 1024 bytes it creates gaps in the address space that point to invalid
byte numbers.

Therefore, be
cause of the nature of binary machines, it makes the most sense to have the
page size and the different address spaces be a power of two.

(YH) It is also more efficient to map the virtual address to the physical address.

3. Suppose the page size in a com
puting environment is 1KB. What is the page number
and the offset for the following:

3.a. 899 (a decimal number)

page # = 899 / 1024 = page 0

offset = 899 mod 1024 = offset 899

3.b. 23456 (a decimal number)

page # = 23456 / 1024 = page 22

offset
= 23456 mod 1024 = offset 928

page # = 0x3F244 / 0x400 = page 0xFC

David Kingston

CS3100 Homework #11

2

Due: 4/18/2002

Chapter 12, Exercises 1, 3, 4, 6, 7, 8b, 8c, 14

offset = 0x3F244 mod 0x400 = offset 0x244

page

# = 0x0017C / 0x400 = page 0

offset = 0x0017C mod 0x400 = offset 0x17C

4. Contemporary computers often have more than 100MB of physical memory. Suppose
the page size is 2KB. How many entries would an associative memory need in order to
implement a pag
e table for the memory?

100 x 1024 x 1024 / (2 x 1024) = 51200 pages = 50 K pages

We need 50 K entries in the table (1 for each page).

6. What factors could influence the size of the virtual address space in a modern
sider the memory mapping unit, compiler
technology, and instruction format.

To answer this question, we must consider the following information. A program address
is relative to the program and start at address 0. The CPU relocation register contains th
e
starting virtual address of where the program is located in virtual memory. The program
instruction being executed. This is sent to the Memory Management Unit (MMU).

The
MMU divides the virtual address up into two parts. The higher bits represent the memory
page. The lower bits represent the offset on the page. The higher bits of the virtual
address are looked up in the page translation table in the MMU to determi
ne the physical
memory page. The offset is then added to the physical memory address to get the
physical memory address of the instruction being executed.

Having given the above short analysis of what is taking place; I believe the most
important factor
in determining the virtual address space of a modern computer system is
the hardware architecture of the computer. This includes considering the size in bits of
the CPU registers, the communication channel between the CPU and the MMU, the CPU
instruction
that the computer is capable of handling. For example, if the computer is a 32 bit
computer it can handle a virtual address space of 2^32 (or 4GB). If the computer
architecture is
64 bits, it can handle a virtual address space of 2^64 (or 17,179,869,184
GB). The MMU then maps the virtual address to the physical address.

As far as compiler technology is concerned, it will assume that the program addresses
start at zero and that pro
grams have the entire virtual address space available to them. I
believe the compiler would mainly be concerned about not hitting the upper limit of the

David Kingston

CS3100 Homework #11

3

Due: 4/18/2002

Chapter 12, Exercises 1, 3, 4, 6, 7, 8b, 8c, 14

(YH) Instruction format works with instruction registers. Instructions such as load an
d
save may have different format for different virtual address space.

Other factors that determine the virtual address space include cost and complexity of the
architecture.

7. What factors could influence the size of the physical address space in a mode
rn
computer system (consider various parts of the hardware).

The computer architecture determines the maximum physical address space. For
example, a 32 bit architecture can have up to 2^32 bytes (or 4GB) of physical address
space. This is assuming the M
MU is capable of handling a physical address space equal
to the virtual address space. (Note that when the physical address space is equal to the
virtual address space, there is no need for the virtual address space to be different than the
ss space.)

The computer chip technology determines how many bits a single chip can hold. The
physical size of the memory card determines the number of chips a single card can hold.
The number of memory slots available determines the number of memory c
ards the
computer can hold. All of these things influence the size of the physical address space in
a modern computer system.

Other considerations include cost and complexity.

8. Suppose w = 2 3 4 3 2 4 3 2 4 5 6 7 5 6 7 4 5 6 7 2 1 is a page reference s
tream.

8.b. Given a page frame allocation of 3 and assuming the primary memory is initially
unloaded, how many page faults will the given reference stream incur under LRU (leased
recently used)?

This will have 12 page faults.

8.c. Given a page frame allocation of 3 and assuming the primary memory is initially
unloaded, how many page faults will the given reference stream incur under FIFO (first
-
in
-
first
-
out)?

This will have 12 page faults.

David Kingston

CS3100 Homework #11

4

Due: 4/18/2002

Chapter 12, Exercises 1, 3, 4, 6, 7, 8b, 8c, 14

14. In a

paging system, page boundaries are transparent to the programmer. Explain how
a loop might cause thrashing in a static allocation paging system when the memory
allocation is too small.

A static paging algorithm allocates a fixed number of page frames to

a process when it is
created. It is possible for a loop to contain instructions that require the program to get a
new page of instructions multiple times in a loop. For example, there may be function
calls in the loop that are located in different memor
y pages. To execute these functions,
the required text pages must be moved into primary memory. If the memory allocation is
too small, it is conceivable that each function call could require moving a different page
into primary memory from virtual memory
. As the loop starts again, the page with the
first function called could have been paged out. It must be paged in again. This could
continue with each iteration of the loop. This is one example of how a loop might result
in thrashing if the memory all
ocation is too small.