transientturn inAB CiS CO

greatgodlyΗλεκτρονική - Συσκευές

27 Νοε 2013 (πριν από 3 χρόνια και 8 μήνες)

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VLSI Design Homework 2

Due to
11/26


1.

Use Hspice to simulate the following circuit. Use 0.35um model file

(ls35_4_1.l
,copy to your working directory:cp ~r92029/lab2/* .
)
The s
ubstrate of
PMOS is connected to VDD,

and

the substrate of NMOS

is connected to
GN
D
.
U
se

transient

analysis and
turn in

plots of inputs
A
,

B
and

Ci

as well as outputs
S
and
C
O
.

Estimate the delay time from the waveforms. And report the power
consumption during the transient simulation.

(Hint:
Delay
time
is defined as the time difference

between an input transition
and the corresponding

output transition passing the 0.5VDD level
. To see the average
power, you need to add
.measure TRAN total_power AVG POWER
in your
simulation file, and you can see it in the *.lis file. You can type only

h
spice


after %
and generate the *.lis file.
)



VDD=3.3V

GND=0V

Input
:

A

,B

,Ci

Output: CO,S

NMOS W=1um,L=1um

PMOS W=2um,L=1um


Input pattern:

A: 0 0 0 0 1 1 1 1

B: 0 0 1 1 0 0 1 1

C: 0 1 0 1 0 1 0 1

Each state lasts for 10 ns
.

rise
time 0.5 ns

(from 0 to1)

fall time 0.5 ns

(from 1 to 0)


2.Use the netlist file extracted from your layout(*.cdl file) and hspice to verify the
function of your layout is correc
t.

H
and in your results and simulation waveform.


VDD=5V

GN
D=0V

Input pattern:

A:0 1 1 1 1 1

B:1 0 1 1 1 1

C:1 1 0 1 0 0

D:1 1 0 0 1 0

E:1 1 0 0 0 1

Each state lasts for 10 ns
.

rise time 0.5 ns

(from 0 to1)

fall time 0.5 ns

(from 1 to 0)

(Hint: Note the syntax of SUBCKT. And you need to re
place

NM


in your cdl file to

nch


and replace

PM


to

pch

)