Some assignments on VLSI Testing

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27 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

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Some assignments on VLSI Testing




1.

For the circuit shown in Figure
1
, perform the following.


(a)

Three test vectors
(0,1,1,1)
,
(0,0,1,1)
, and
(1,0,1,0)

are applied to the circuit in
sequence. Determine the faults detected using concurrent

fault simulation. Show
the intermediate fault lists after processing with each of the test vectors. The
initial fault list may be considered to consist of an uncollapsed list of all single
stuck
-
at faults in the circuit.

(b)

Repeat above for deductive fault s
imulation

(c)

Apply the method of Boolean difference to find all the test vectors that can detect
the fault
g stuck
-
at
-
1

in the circuit.

(d)

Use the
Justify

and
Propagate

functions of the simplified D algorithm as

was

disc
ussed in the class to generate

test
s

for t
he fault
s

h stuck
-
at
-
0

and
h stuck
-
at
-
1
.


2.

Find the minimal test sets required to detect all single stuck
-
at faults in the following:

(a)

A 759
-
input exclusive
-
OR gate

(b)

A 256
-
input exclusive
-
NOR gate

(c)

A 16
-
input NAND gate

(d)

An n
-
line to 1
-
line multiplexer








3.

Answer the following questions.








(a)

Consider a full
-
scan design, where there are
n

scan flip
-
flops, G gates in the
combinational logic portion, and
m

combinational test vectors used for testing the
combinational logic. Derive an e
xpression for the scan test length and percentage
gate overhead for scan design, when the scan flip
-
flops are distributed in
k

scan
chains of equal length. Assume that only one extra pin is available for test, but
the number of primary input and output pin
s is not limited. Clearly state any
assumptions you make.

(b)

For the circuit shown in Figure 2, suppose that three flip
-
flops are inserted
in the
feedback paths
between
(F,

C)
,
(k,

B)
,

and

(m,

D)
. Write the Verilog
/VHDL

description of the netlist where the fl
ip
-
flops are configured in a full
-
scan
configuration.


4.

(a)

For an autonomous LFSR being used as a pattern generator, show that if
the initial state is not the all
-
zero state, then it will never enter the all
-
zero
state.

(b)

Justify or contradict the statement:
an autonomous LFSR with odd number
of connections to the feedback EXOR gate can never realize a primitive
polynomial
.

(c)

Draw an internal EXOR LFSR with feedback polynomial f(x)=x
5
+x
2
+1.
Simulate the LFSR and obtain the first 16 bits of the sequence generated

at
the output of the last stage of the LFSR, when it is initially loaded with the
pattern 10000.

(d)

Modify the LFSR of the previous problem to implement a weighted
random pattern generator (WRPG) for the weight set {0.125, 0.375, 0.5,
0.75, 0.875}. That is,

the WRPG will have five outputs that will be
generating bit stream with the specified signal probabilities.


4.


(a)

Consider a synchronous sequential circuit that has n=4 primary inputs,
m=3 primary outputs, and k=3 state variables. Assume that test generation
has been performed on the combinational logic block of this circuit to
obtain the following test vectors and responses:


Input Vectors

Output Responses

Primary Inputs

Present State

Primary Outputs

Next State

1

0

1

1

0

1

1

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

0

1

0

0

1

1

1

1

0

1

0

1

1

0

0

1


Show the details of the scan chain design using a multiplexed
-
input scan
flip
-
flop. Also, describe how the test vectors and applied and the
corresponding response observed on a cycle
-
by
-
cycle basis.


A

B

C

D

F

a

b

c

d

e

f

g

h

i

j

k

m

FIGURE
1