IFIP Working Group 10.5 Minutes Meeting

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27 Νοε 2013 (πριν από 5 χρόνια και 5 μήνες)

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IFIP Working Group 10.5 Minutes Meeting

Dresden, 13/03/2012 (18:30


DATE Conference room 5

Preliminary version

Notes taken by Lionel Torres and Dominique Borrione

David Atienza

Jose L. Ayala, Juergen Becker,

Achim Bettberg (invit

Dominique Borrione, Kiyoung Choi, Luc Claesen, Ayse Coskun, Nikil Dutt, Michael Hübner,

Ahmed Jerraya,
Takashi Kambe

Wolfgang Nebel,
Franz J. Rammig,
Ricardo Reis, Sergey
Rosanov (representing Alexander Stenkovsky),
Donatella Sciuto, Leandro Soares I
Lionel Torres, Chi
Ying Tsui,
Fatih Ugurdad, Eugenio Villar.

Participation by skype:
Salvador Mir, Luis Mig
uel Silveira.

: Einar J. Aas, Matthew R. Guthaus,

Reiner Hartenstein

Masaharu Imai, Klaus
Glaser, Osamu Karatsu, Ian

O'Connor, Hillel Ofek, Adam Pawlak, Flávio Rech
Wagner, Michel Robert, Wolfgang Rosenstiel, P.A. Subrahmanyam, Ronald Waxman.

The minutes are complemented by several slide presentations used during the meeting,
which are attached as a separate document

Contents of the slide presentations are not
necessarily repeated in the minutes.


Welcome of Participants,

Approval of Agenda


Minutes Hong Kong meeting

Minutes of Hong Kong are approved by all the attendees

Introduction of new members

New me
mbers introduced themselves and were welcome to the WG by applause


Ayse K. Coskun
, Boston University,

Research topic: Performance and Energy aware computing laboratory

Key words : 3D, Thermal modelling, Dynamic Management, Novel Architecture, Green
Software (Virtualisation and Scheduling), many core


Leandro Indrusiak
, York University.

Key words
: Model Driven design of Embedded systems, Real time systems, Energy
aware computing,
Transaction level simulation for NoC and MPSoC

Takashi Kambe
, Univ. OSAKA, Japan.

Key words

automatic layout, VLSI Circuits, System level design, CAD

Michael Huebner
, KIT, Germany.

Key words
: processor and reconfigurable HW, HW/SW partitioning, applica
tion specific
processor, CAD tool/Design flow for reconfigurable, Dynamic reconfiguration


Update on FDL 2012

by Dominique Borrione

Call for paper is out and was distributed by e

Paper submission deadline is April 1st.

Paper work for IFIP WG 10
.5 co
sponsorship without financial involvement is being
done. IFIP logo will be added immediately after.

Please promote this event
: http://www.ecsi.org/fdl


Update on VLSI
SoC 2012

by Ayse K. Coskun using presentation prepared by
Matthew Guthaus (see
attached .ppt document)

Two sessions in parallel, TPC is set up, PhD Forum

12 Tracks, Ayse will communicate the TPC member list to the working group. and/or to
The Web site is to be updated with the TPC member list.

The presentation done shows

clearly that the conference organization is well advanced.

Please promote VLSI 2012,


Update on VLSI
SoC 2013

by Fatih Ugurdag (see attached .ppt document)

Istanbul, Tur

: still to be finalized. Will try to avoid overlap with ES Week if their dates can be
obtained quickly.

General Chair: Fatih Ugurdag, Ozyegin University, Istanbul, Turkey

General Co
Chair: Luis Miguel Silveira, INESC ID/IST, PT

Program Co

Alex Orailoglu, UC San Diego, US

Luigi Carro, UFRGS, Brasil

: Several candidate hotels (under discussion/negot
iation) See de
tails and location
on slides. First choice

of Fatih Ugurdag: Novotel near the sea. WG approves.

Local organization team i
s set up (see slides).

Budget is shown (see in slide link). Participation of 150 would be beneficial.

Paper work with IFIP, and MOU with IEEE.

The University has

expanded their insurance to cover the IEEE request for liability
insurance amount.

The only u
nacceptable item in the IEEE MOU for Ozyegin University: to refer to the court
of New York in case of disagreement. It is suggested to remove the paragraph and
submit it to IEEE as such.

New: IFIP is changing from paper to electronic submission of event a
pproval forms.

Please refer to e
mail being forwarded by Dominique on this topic just after these


SOC 2014

There is a proposal from Virendra Singh to organize VLSI
SOC 2014 in India, Mumbai
(Bombay). Dominique reads some indications rece
ived by e
mail. The venu
e would be at
the University premis

In the discussion about the India proposal, the following pros and cons were raised:


SOC was never in India


Con: Mumbai would be less attractive than e.g. Delhi or Bangalore to foreig
participants, and that this would lower attendance.


Traffic in Mumbai is very difficult


Question: what about the presence of local EDA or circuit industry that would
find it attractive to support the event and send participants


For lack of information
, the proposal will need to be presented in more
tails for
possible approval at the October meeting in Santa

Post meeting information: Virendra Singh sent slides the day after the meeting.

They are attached as appendix to these minutes for the WG


Ricardo Reis also ment
ions another proposal to have VLSI
SOC in Mexico. No details
were provided.




Fixed address for the conference VLSI
SOC should be arranged to repatriate web
site and information on past events and VLSI
books; and to have a unique entry
point. To be dealt with by the executive committee.


VLSI BOOK 2010 was published last year, it is available.


For VLSI 2011, 9 chapters received, 7 have been reviewed, 2 chapters reviews
still missing. Publication before O
ctober, so that the book is available at the Santa
Cruz venue is expected.

Next meetings

San Francisco, June 2012, in conjunction with DAC

Santa Cruz, October 2012, in conjunction with VLSI

Grenoble, March 2013, in conjunction with DATE