VLSI DOMAIN
S.No
TITLE
YEAR
1
A high
-
throughput low
-
latency arithmetic encoder design for HDTV.
IEEE 2013
2
Field
-
programmable gate array implementation of low
-
density parity
-
check
codes decoder and hardware testbed.
IEEE 2013
3
FPGA
-
Based Fast Detection With Re
duced Sensor Count for a Fault
-
Tolerant Three
-
Phase converter.
IEEE 2013
4
A Reconfigurable Application
-
specific Instruction
-
set Processor for Fast
Fourier Transform processing.
IEEE 2013
5
A survey of FPGA based Interference cancellation architectures f
or
biomedical signals.
IEEE 2013
6
Efficient Elliptic Curve Point Multiplication Using Digit
-
Serial Binary
Field Operations.
IEEE 2013
7
Specific processor in FPGA for BLAKE algorithm.
IEEE 2013
8
Total Design of an FPGA
-
Based Brain
–
C潭灵p敲⁉湴敲f慣攠e
潮tr潬
H潳灩t慬⁂敤⁎畲獩湧⁓ 獴em.
I䕅䔠㈰ㄳ
9
Hig栠獰h敤慲摷ar攠erbitr慴i潮異灯pti湧⁰ i潲itie猠s湤潵湤敤ervi捥
l慴敮ey.
I䕅䔠㈰ㄳ
N潶敬⁁r捨ct散tur攠e潲⁅ffi捩敮t⁆ GA⁉m灬em敮e慴io渠潦⁅ li灴i挠䍵rv攠
Cry灴潧r慰桩c⁐牯捥獳潲⁏v敲⁇䘨㊹
⁶
댩³
I䕅䔠㈰ㄳ
ㄱ
A⁍畬ti
-
R敳潬畴i潮⁆oGA
-
B慳敤⁁e捨ct散tur攠e潲⁒eal
-
Tim攠䕤e攠e湤n
C潲湥n⁄整e捴i潮o
I䕅䔠㈰ㄳ
ㄲ
V䱓I Im灬em敮e慴i潮f 䱯L
-
C潳o⁈igh
-
Q畡uity⁉m慧攠卣eli湧⁐牯 e獳or
I䕅䔠㈰ㄳ
ㄳ
H整敲潧敮e潵猠䵵Mti
-
C潲攠卹獴敭Ⱐ獹湣桲潮oz敤e⁐整
ri⁐ 潣o獳潲渠
䙐GA.
I䕅䔠㈰ㄳ
ㄴ
D敳ig渠慮搠im灬敭敮e慴i潮 g栠h桲潵o桰ht 摩r散ti潮ol⁆慮 散o摩湧.
I䕅䔠㈰ㄳ
ㄵ
A⁎潶敬⁖䱓I⁄HT⁁lg潲it桭潲⁈楧桬y⁍潤 lar湤⁐慲慬l敬
Ar捨ct散tur攮
I䕅䔠㈰ㄳ
ㄶ
V䱓I⁁r捨cte捴ure猠sor⁴桥h4
-
T慰湤‶
-
T慰a
2
-
D⁄慵扥捨c敳 坡v敬et
䙩Ft敲猠啳s湧⁁lg敢e慩c⁉湴敧敲献
I䕅䔠㈰ㄳ
VLSI DOMAIN
17
Design of Sobel operator using Field Programmable Gate Arrays.
IEEE 2013
18
A real
-
time video denoising implementation on FPGA using contourlet
transform.
IEEE 2013
19
20
-
Bit RISC and
DSP System Design in an FPGA.
IEEE 2013
20
FPGA based design and implementation of modified Viterbi decoder for a
Wi
-
Fi receiver.
IEEE 2013
21
GF(q) LDPC decoder design for FPGA implementation.
IEEE 2013
22
Performance evaluation of FFT processor using
conventional and Vedic
algorithm.
IEEE 2013
23
Design and Implementation of a High Speed MAP Decoder Architecture for
Turbo Decoding.
IEEE 2013
24
Combining checkpointing and scrubbing in FPGA
-
based real
-
time systems.
IEEE 2013
25
Simulation and implem
entation of LDPC code in FPGA.
IEEE 2013
26
Improved low
-
cost FPGA image processor architecture with external line
memory.
IEEE 2013
27
An area efficient multiplexer based CORDIC.
IEEE 2013
28
Design and implementation of hardware architecture for denoi
sing using
FPGA.
IEEE 2013
29
Transducerless Acquisition of the Rotor Position for Predictive Torque
Controlled PM Synchronous Machines Based on a DSP
-
FPGA Digital
System.
IEEE 2013
30
Speed optimization of a FPGA based modified viterbi decoder.
IEEE 201
3
31
A Superregenerative QPSK Receiver.
IEEE 2013
32
FPGA implementation for real
-
time Chroma
-
key effect using Coarse and
Fine Filter.
IEEE 2013
33
Low cost permanent fault detection using ultra
-
reduced instruction set co
-
processors.
IEEE 2013
34
A nov
el technique for run
-
time loading for MIPS soft
-
core processor.
IEEE 2013
35
Novel high speed vedic mathematics multiplier using compressors.
IEEE 2013
36
Implementation of binary to floating point converter using HDL.
IEEE 2013
37
Modified FPGA based d
esign and implementation of reconfigurable FFT
IEEE 2013
VLSI DOMAIN
architecture.
38
Reconfigurable pipelined coprocessor for multi
-
mode communication
transmission.
IEEE 2013
39
An approach for redundancy in FlexRay networks using FPGA partial
reconfiguration.
IEEE
2013
40
A high speed binary floating point multiplier using Dadda algorithm.
IEEE 2013
41
A Design Approach of Low Power VLSI for Downsampler Using Multirate
Technique.
IEEE 2013
42
VLSI Implementation of Enhanced Edge Preserving Impulse Noise
Removal
Technique.
IEEE 2013
43
A factorization method for FPGA implementation of sample rate converter
for a multi
-
standard radio communications.
IEEE 2013
44
Embedded System for Biometric Online Signature Verification.
IEEE 2013
45
Throughput/Resource
-
Efficie
nt Reconfigurable Processor for Multimedia
Applications.
IEEE 2013
46
Comparison of number formats on FPGA
-
based OFDM modem
architecture.
IEEE 2013
47
Adaptive Multiset Stochastic Decoding of Non
-
Binary LDPC Codes.
IEEE 2013
48
A 2.0 Gb/s Throughput Dec
oder for QC
-
LDPC Convolutional Codes.
IEEE 2013
49
A real time high definition architecture for the Variable
-
Length Reference
Frame Decoder.
IEEE 2013
50
FPGA architecture for OFDM Software Defined Radio with an optimized
Direct Digital Frequency Synthes
izer.
IEEE 2013
51
Efficient FPGA Implementation of Address Generator for WiMAX
Deinterleaver.
IEEE 2013
52
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation
Mapping.
IEEE 2013
53
FPGA implementation of pipelined CORDIC based quadrature dir
ect digital
synthesizer with improved SFDR.
IEEE 2013
54
FPGA implementation of digital modulation techniques.
IEEE 2013
55
FPGA implementation of QAM modems using PR for reconfigurable
IEEE 2013
VLSI DOMAIN
wireless radios.
56
Dynamically reconfigurable PWM contro
ller for a single phase rectifier.
IEEE 2013
57
A Unique Technique for Reducing the Effects of Hot
-
carrier Induced
Degradations in CMOS BistableCircuits for Fault Tolerant VLSI Design.
IEEE 2013
58
DS
-
CDMA Implementation With Iterative Multiple Access In
terference
Cancellation.
IEEE 2013
59
Power
-
Up Sequence Control for MTCMOS Designs.
IEEE 2013
60
CORDIC Designs for Fixed Angle of Rotation.
IEEE 2013
61
Low power reconfigurable FPGA based on SRAM.
IEEE 2013
62
Research and implementation on multi
-
DDS
technology in high
performance digital up
-
conversion.
IEEE 2013
63
Hardware
-
software extensions to a softcore processor for FPGA
-
based
adaptive PID control.
IEEE 2013
Enter the password to open this PDF file:
File name:
-
File size:
-
Title:
-
Author:
-
Subject:
-
Keywords:
-
Creation Date:
-
Modification Date:
-
Creator:
-
PDF Producer:
-
PDF Version:
-
Page Count:
-
Preparing document for printing…
0%
Σχόλια 0
Συνδεθείτε για να κοινοποιήσετε σχόλιο