Design of 5 Stages Pipelined 32 Bit RISC Processor

georgenameΗλεκτρονική - Συσκευές

27 Νοε 2013 (πριν από 3 χρόνια και 11 μήνες)

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Design of 5 Stages

Pipelined 32 Bit RISC Processor

Prof
. Sharda
P.
Katke

sharda.katke@gmail.com

Department of
ENTC

BMIT solapur
-

413006 INDIA


ABSTRACT
:


The proposed work is the design of a 32 bit

RISC (Reduced Instruction Set Computer)
processor
. The
design

will help to improve the speed of processor, and to give the higher
performance of the processor.
It has 5 stages of pipeline viz. instruction fetch, instruction
decode, instruction execute, me
mory access and write back
all in one clock cycle.

The
control unit controls the operations performed in these stages. All the modules in the design
are coded in VHDL. Particular attention will be paid to the reduction of clock cycles as well
as to improve

the speed of processor.
This can be targeted to any FPGA for several
applications
. The processor will Synthesize using Xilinx Web pack and simulate using Model
Sim simulator
.


KEYWORDS
:

Reduced

instruction set computer (
RISC)
,
VLSI
,
VHDL,

Pipelined architecture
.


International Journal of Electronics & Communication Engineering and technology
(IJECET)