Draft specifications v5.0 of GBT-SCA - LHCb Electronics

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Rev 5.0

Preliminary


1





GBT
-
SC
A


The Slow Control Adapter

for the

GBT

System




Alessandro Gabrielli

(
Kostas

Kloukinas
,
Paulo Moreira
,
Alessandro Marchioro
,
Sandro Bonacini
,
Filipe Sousa
)







Rev 5.0

Preliminary


2

1.

DOCUMENT HISTORY

18/04/2008 Rev 1.0


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Rev 5.0

Preliminary


3

2.

GENERAL

This document describes the GBT
-
SCA
, a general
-
purpose integrated circuit for the monitoring and
control of the electronics in HEP experiments.

This document focuses on the user
-
visible aspects of the component such as its logical and
electrical interfaces, programming features and operating modes. It also includes detailed
descriptions and specificat
ions of the chip pin
-
out and electrical characteristics.

The Slow Control Adapter (SCA) chip is designed to work in parallel with to the GBT

optical link
bidirectional transceiver system of which it extends the functionality.

To understand the

SCA in a system using GBT

links, a brief explanation of a GBT based system is
provided in the next section.

2.1.

Overview of the GBT

System

Typical High Energy Physics systems are today composed of three functional subsystems each of
which traditionally implements its transmission system from the control room to the electronics
located in the detectors. These systems are:



A fast timing distribution system responsible to deliver to the experiment the system clock
and several fast trigge
r signals, and sometimes some fast signal from the detector to the
control room



A data acquisition link carrying the collected data from the detector to the control room



A Slow control system carrying bidirectional traffic from and to the control room and
the
embedded electronics in the detectors


The GBT

project aims at providing a bidirectional system carrying all three types of traffics
mentioned above. Clearly this is achieved by sharing a common medium, which in the GBT system
is expected t
o be a pair of unidirectional optical fibers each one with a capacity of about 4.8 Gbit/s.
An appropriate bandwidth is allocated to each of the three tasks in the GBT system.

The slow control part is one of the subsystems served by the GBT
. The

GBT protocol is totally
transparent to the slow control protocol. The GBT encoded slow control information in the counting
room, carries it along the other traffic on the optical fibers, and delivers the information unmodified to
the GBT
-
SCA

in the embedded system.

A block diagram of the GBT

system in illustrated in Figure 1

The GBT

system consists physically of a dedicated ASIC called GBTX in the embedded electronics
and of an FPGA called GBTFA containing several GB
T channels in the counting room. The GBT
-
SCA

is connected physically to the GBTX, which implements the long
-
haul transmission medium for
it.

As the GBT

system is based on a point
-
to
-
point architecture, the slow control system co
nsists
essentially in a local area network using a point
-
to
-
point topology.

The bandwidth allocated by the GBT

system to the slow control function is 80 Mbit/s.

Rev 5.0

Preliminary


4


Figure
1

Control module, simplified view


The arrangeme
nt shown in the figure assumes that the connection between the GBT13 and the
GBTFA is done via optical fibers, the connections between embedded Control modules is done
electrically using low voltage differential lines (LLVDS).


2.2.

Overview of the GBT
-
SCA

Architecture


A complete system for the control of the embedded electronics is normally composed of the following
four components:



A computer in a remote control room is the brain of the system: it runs an operating system and
an
application program that by performing remote actions on an SCA is capable of reading and
writing the user registers in peripheral chips connected to the SCA peripheral ports.



A transport network, in this case the GBT

system, carries physically

information under the form
of packets in a unified format between the counting room and the embedded SCA.



The SCA itself is the embedded node of the system and translates the unified packets sent by
the computer above into a transfer to one of the periphe
ral ports or an action performed by one
of the embedded peripherals.



The SCA has two independent e
-
ports to connect to the GBT
s
. One of the two
ports
is primary

and must be connected in any case
.
The second one is to be used if two different GBTs need to
s
hare the slow
-
control. In this way, even if one of the two e
-
link brakes up, the second one can
take the control of the SCA.
Th
us, th
is schema allows interfacing with one individual SCA
Rev 5.0

Preliminary


5

through two different GBTs. In this way
an automatic double e
-
port
redundancy is guaranteed. A
block diagram of this redundancy is shown in Figure 2.


Figure
2

E
-
port Redundancy




The peripherals to the SCA are electronic components accessible via one of the buses
implemented in the SCA. These bus
es are, for example, I2C
, JTAG
, parallel I/O bus etc, as we
will explain in detail below. In an HEP experiment these components can be front
-
end chips
dedicated to the read
-
out of specific detectors, or monitoring chips for the con
trol of
environmental variables such as local voltages, temperatures etc.


The communication protocol used between the control remote computer and the peripheral chips is
a system is based on two layers:



The first layer connects the remote control compute
r to the SCAs; the protocol on this layer is
message based and is implemented in a way similar to standard computer LAN networks. In the
GBT
-
SCA

system, the GBT is completely agnostic to this protocol; packets from the remote
co
mputer to the SCA are transmitted unmodified by the GBT link.



The second layer connects the SCA to the peripheral chips in the system via so called
Channel
Ports
. The protocols used here are called the
Channel Protocols
.

The first layer is unified and comm
on to all SCAs, and is based on LAN architecture transporting
data packets to and from the GBT

and remote controllers. The second layer is specific to the
channel, and different kind of physical implementations of the channels are foreseen.

Th
e SCA contains the blocks as shown in

Fig.
3
:



On the GBT

side



A
MAC

Controller



A
Network Controller

(NC). The SCA internal control and status registers are seen through a
special interface capable for instance to report the status of the other SCA channels.



An
Arbiter
, based upon Round
-
Robin technique, to enable the user ports, the monitors or the
NC, o
ne at a time, to send data backwards towards the GBT

upon reply of previous requests.
In
this view the NC is also seen like the other ports and if a command is addressed to the NC, it
sends an enable request to the Arbiter before sending data b
ackwards.



On the user side the SCA has a number of channel ports, sometimes including dedicated
controllers, and organized as follows:



A group of
16 I2C

master

controllers



One JTAG

master controller



A group of
4

8
-
bit fully program
mable and bidirectional IO ports
, functionally similar the ones
used in the Motorola
PIA

etc.

These ports are multiplexed with the Memory Channel

to save I/O
pads
.

The selection is made via a hardwired input pin.

Rev 5.0

Preliminary


6



One

memo
ry
-
like

bus
master
controller with 8 bit data and 16 bit address data path, to access
devices such as static memories, A/D converters etc
.
As stated above, t
his port is multiplexed
with the 4 PIA

ports
.



One serial
SPI

master
bus
.



32

analog
channels
, to be used one at a time,

to be converted to a 12
-
bit value via an
ADC

port.



4

DAC

8
-
bit
port
s
.



4 asynchronous
external
interrupts
.
These interrupts are continuously polled by the
NC

that
provides a dedicated packet backwards to the GBT

to let the users aware of the interrupt

request
s.


The communication between these user ac
cessible ports and the
Network C
ontroller

handling the
high level protocol with the remote computer is done via appropriate internal buses and is not visible
by the user of the SCA.

The dual network layer architecture introduced above is necessary to support applications where
long cables/fibers are used between the control room of the experiment and the embedded SCA
(therefore generating long delays) and to support the relatively slow buses chosen to interface to the
front end chips, such as the I2C

bus. This archit
ecture assumes that the control is done by sending
data packets (messages) to the respective channels, which interpret the messages as commands,
execute them on their external interfaces (for example just a read or write operation to a memory

bus) and return a status reply to the GBT

via another message. The commands can be either
addressed to registers located within the channel ports


configuration registers


or to devices
located in the far front
-
end. In this latter case the
command interpretation and execution is
demanded to the front
-
end electronics.

This protocol assumes that the remote devices controlled by the SCAs are seen from the control
computer as remote independent channels, each one with a particular set of control

registers and/or
allocated memory

locations. The channels operate independently from each other to allow
concurrent transactions. The channels can perform transfers to their end
-
devices concurrently.

To decouple the operation on the channel

ports with respect to the one of the GBT

link, the
architecture assumes that all operations on the channels are asynchronous and do not demand an
immediate response. Basically this means that all commands carried by the GBT link under the form

of network messages are posted to the channel interfaces. This is easy to implement for write
operations, where practically one works by posting write operations to the channels. For read
operations a read request is sent to the channel; the channel perfo
rms the operation on its interface
and returns a request of attention to the
Arbiter
. All upwards packets are acknowledged via either
status or data words depending on the command type. Read commands send data backwards,
which are auto
-
acknowledged; write
commands send just the status of the channel as a backward
reply.

Figure 3 shows the GBT
-
SCA

architecture as described above. A few details concerning the internal
channels are also provided.

Figure 4 instead shows a block schem
a of the MAC controller.

Figure 4 shows the Reset Tree

of the SCA. In particular the chip and internal blocks can be reset in
different ways via:



an external

asynchronous reset pin

that resets the entire chip,



a

GBT command to the MAC controller. In this way all the blocks except the MAC controller
are reset as it was used the external asynchronous reset pin,



a GBT command
delivered through

the NC to the

uniquely

addressed IO port,



a GBT command to the NC that is

broadcasted to all
the IO ports except the Arbiter.



Rev 5.0

Preliminary


7


Figure
3
:

block diagram of the GBT
-
SCA
:



Figure
4
:
Logic Reset Tree

of the GBT
-
SCA


Rev 5.0

Preliminary


8


Figure
5
:
MAC to
Network Controller

interface


2.3.

Radiation tolerance features

To be able to operate in an LHC environment, the SCA is designed with some rad
-
tolerant features.
These features include:



Resistance to

high total
ionizing
dose
(TID)
as required by LHC electronic systems



Inclusion of
triple
redundant circuitry on so
me critical logic blocks for single event effects (SEE)

robustness.

Critical control state machines and logic are protected by redundancy. Th
is will be implemented
using either spatial or temporal redundancy as required.

The data path on the SCA instead is not protected by redundancy and e
rrors that will occur due to
SEE

will be detected through parity mechanisms. Such errors are not critical f
or the operation of the
SCA, as corrupted commands can be re
-
executed by the remote controlling software.



Rev 5.0

Preliminary


9

3.

SCA PACKET DESCRIPTI
ON

3.1.

The protocol


The SCA exchanges information with the remote computer using as transport layer the GBT

link.
The p
ackets exchanged along this route are of a unified format. The remote computer typically
initiates all actions by sending some command
s

to the SCA which then translates this command into
an action to be performed onto one of its peripheral ports.

The conne
ction between the remote computer and the embedded S
CA is of a point
-
to
-
point type
therefore no addressing information is needed to be dispatched to the SCA along the GBT

link.

To acknowledge reception of each command packet, the SCA returns
the received packet to the
remote computer. In this way the remote computer knows that the command has been received at
the destined SCA.

The link between the SCA and the computer (through the GBT
) exchanges only two type
s

of
packets:



IDLE: whe
n no useful information is to be sent, an idle is inserted by the transmitter and
discarded at the receiver. This packet is a single byte long.



DATA: Useful information is instead encapsulated in a structure which is defined as follows:

o

A S
tart
O
f
F
rame (S
OF)

byte

o

PAYLOAD bytes

o

A

CRC

byte

o

An E
nd
O
f
F
rame (EOF)

byte

The length of this packet is variable and delimited by the EOF byte. The MAC reads also the content
of the LEN byte (see below) in the PAYLOAD and checks that the length of the packet

is correct by
verifying that the last byte is indeed an EOF byte. The MAC also verifies the correctness of the CRC
.

The MAC adapter strips the SOF, CRC

and EOF at the input of the SCA, and
only
the PAYLOAD
content is delivered to t
he internal part of the SCA.

The SCA can also generate packets to the control computer. Such messages are generated, for
instance, upon generation of an interrupt in the SCA and upon completion of a read operation on an
external peripheral port.
In any ca
se the SCA acknowledges the packets coming from the GBT

via a
so
-
called acknowledge packet. Figure 5 shows the forward and backward packet communications.

When not transmitting useful data packets, the SCA generates idle packets. These idle pac
kets are
the same in both directions.


Figure
6
:
SCA Packet

communication

system

Rev 5.0

Preliminary


10


3.2.

PAYLOAD Format

The content of the PAYLOAD section is depicted below:







Figure
7
:
SCA
-
to
-
Port

Command
Packet

example


Figure
6

shows how
a

command

is sent to a specific port. In any case a reply
-

Fig. 7

-

is for
eseen
and this is sent back with a different PAYLOAD. In particular, the
ACK

byte is used to state the
command status. In this way is the command has been correctly received by the addressed port is
visible through the
ACK

byte. Only the RESET commands sent to the ports are not acknowledged
with a reply packet.





Figure
8
:
Port
-
to
-
SCA
Reply
Packet

example


This is delivered by the SCA Node Controller to the channel identified by the CHAN field.

The different field are defined as follows::



CH#

specifies the SCA internal port to be addressed


i.e. I2C
, JTAG
, NC, SPI
, etc.
-
,



TR#

is a byte used to identify the operation being carried out. This value is returned during
the acknowledgement of completion of operations by the SCA to the remote computer.



CMD

is a command code that specifies a given operation to be performed on a chann
el port.
The operation can refer to a specific internal register of the channel


i.e. a configuration
register


or to a n external bus related operation, such as, for example, an I2C

read or
write. In this case an address field follows the co
mmand.



DATA

is a command dependent variable length field.



LEN

is an optional field that specifies the PAYLOAD length and can be considered as part of
the
DATA

field.

It is only used for I
2
C channels

and accepts values from 1 to 28 depending
on the commands
: if the commands
is the

multiple write in extended addressing mode, i.
e.
two bytes are used for the address, 26 bytes can be written at most
.

On the contrary, if the
command is the multiple write with normal addressing mode, i.e. one byte only is used for

the address, then 27 bytes are available for writing.





CH
#


TR
#

CMD


DATA

Optional (LEN)

1 byte

1 byte

1 byte

1 to
N bytes

CH#


TR#

ACK


DATA

1 byte

1 byte

1 byte

1 to N bytes

Rev 5.0

Preliminary


11

4.

CHANNELS IN GBT
-
SCA

4.1.

General

Channels receive commands from the node controller and control the actions on the bus to which
they connect as masters. These commands are co
ntained in the data packet and therefore data
contents, in a given packet, interpreted differently by each channel.

The command sub
-
field (typically the third byte in a message to a channel) contains the code for the
requested operation. Each channel has
a set of valid commands as explained in this chapter.
Channels receiving an invalid command do not execute any action and report the error condition to
the node controller.

Upon reception of a command a channel performs the required operation on its interf
ace and then,
depending on the specifics of the command, can return a reply to the node controller as a data block,
which is then transmitted, to the destination in a message packet.

The distinction between channels at the level of the
GBT

is
performed essentially by software.

The following paragraphs specify the content of the packets for each type of channel.

In this implementation, the GBT
-
SCA

does not support command queuing for the I2C

channels. Only
one command can be in execution at any one time.

4.2.

Allocations of channels in the GBT
-
SCA

Each channel in a network data packet (message) is identified by the first data byte in the data
payload. The following tabl
e gives the internal address allocation for channels in the GBT
-
SCA
:

Channel Number

[Hex]

Function

0x
00

Network

Controller

0x
02

Master SPI

(Serial Peripheral

Interface)

0x
10

0x
1F

Master I2C

C
hannels (16 identical)

0x
30

0x
33

Master
PIA

C
hannels (4 identical)

0x
40

Master
Memory C
hannel

0x
60

Master JTAG

C
hannel

0x
7
0

1 out of 32 selectable Analog

Input Channels (ADC
)

0x
80

0x
83

DAC

Analog Output Channel

(4 identical)

0x
AA

SCA Reset

channel, if combined with 0xAA command

0x
FC

Interrupt Channel

0, not addressable, active low

0x
FD

Interrupt Channel

1, not addressable, active low

0x
FE

Interrupt Channel

2, not addressable, active low

0x
FF

Interrupt Channel

3, not addressable, active low

Figure
9
:

Channel number allocation

The 0x
F
C
-
0xFF addresses are
Reserved

for the interrupts

so cannot be used for
CH#
. 0xFF is
then a
Reserved

TR# ID.



Rev 5.0

Preliminary


12

4.3.

GBT
-
SCA

controller


The GBT
-
SCA

controller is a dedicated logic block inside each GBT
-
SCA, which is needed mainly
for network and internal channels supervision. The GBT
-
SCA controller is reachable with the same
protocol used to transfer data to the other port channe
ls.

The following registers are defined in the controller:

Name

Function

CRA

Control

R
egister A

-

general

CRB

Control

R
egister B



I/O Port Enable



default is 0, disabled

CRC

Control Register C


I/O Port Enable



default is 0,
disabled

CRD

Control Register D


I/O Port Enable



default is 0, disabled

CRE

Control Register E


I/O Port Enable



default is 0, disabled

SRA

Status Register A

SRB

Status Register B

Figure
10
:

Control and Status registers in GBT
-
SCA

Controller

Control registers are all read/write registers. They can be read back after a write operation to verify
their contents. Status registers are
read
-
only registers, as they are set typically by hardware inside
the GBT
-
SCA
.

4.3.1.1.

Control Register A

Control register A is a general control register for the GBT
-
SCA
. It contains control bits, which are
relevant for the operation of all channels in the GBT
-
SCA.

The following bits are defined:

Bit

Name

Function

Comment

0

MEM_PIA

Memory vs PIA

selection

Default at 0 to select the 4 PIA

ports. When at 1 Memory channel
is available

1
-
4

Reserved



5

EXTRES

Generates external
reset

Writing a “1” to this bit
generates a 10
μ
s reset pulse on
the Reset_Out

pin
. This bit is
always read back as “0”.

Read as a “1” during the
reset
time.

6

Reserved



7

Reserved



Figure
11

Network

C
ontroller

control

register A



Rev 5.0

Preliminary


13

4.3.1.2.

Control Register B
-
C
-
D
-
E

The node controll
er Control registers B
-
C
-
D
-
E are

defined to enable, individually, the ports in such a
way that if any port is disabled, it does not receive the clock. In this way the power consumption can
be reduced at the lowest value according to the user constraints.

By default all the ports are
disa
bled.

Bit

Name

Function

Comment

B
-
0


B0


Enable port I2C
-
0


Enable address 0x10

B
-
1


B1


Enable port I2C
-
1


Enable address 0x11

B
-
2


B2


Enable port I2C
-
2


Enable address 0x12

B
-
3


B3


Enable port I2C
-
3


Enable address 0x13

B
-
4


B4


Enable port I2C
-
4


Enable address 0x14

B
-
5


B5


Enable port I2C
-
5


Enable address 0x15

B
-
6


B6


Enable port I2C
-
6


Enable address 0x16

B
-
7


B7


Enable port I2C
-
7


Enable
address 0x17

C
-
0


C0


Enable port I2C
-
8


Enable address 0x18

C
-
1


C1


Enable port I2C
-
9


Enable address 0x19

C
-
2


C2


Enable port I2C
-
10


Enable address 0x1A

C
-
3


C3


Enable port I2C
-
11


Enable address
0x1B

C
-
4


C4


Enable port I2C
-
12


Enable address 0x1C

C
-
5


C5


Enable port I2C
-
13


Enable address 0x1D

C
-
6


C6


Enable port I2C
-
14


Enable address 0x1E

C
-
7


C7


Enable port I2C
-
1
5


Enable address 0x1F

D
-
0


D0


Enable port JTAG


Enable address 0x60

D
-
1


D1


Enable port SPI


Enable address 0x02

D
-
2


D2


Enable port Memory


Enable address 0x40

D
-
3


D3


Enable port ADC


Enable address 0x70

D
-
4


D4


Enable port PIA
-
A


Enable address 0x30

D
-
5


D5


Enable port PIA
-
B


Enable address 0x31

D
-
6


D6


Enable port PIA
-
C


Enable address 0x32

D
-
7


D7


Enable port PIA
-
D


Enable address 0x33

E
-
0


E0


Enable port DAC
-
0


Enable address 0x80

E
-
1


E1


Enable port DAC
-
1


Enable address 0x81

E
-
2


E2


Enable port DAC
-
2


Enable address 0x82

E
-
3


E3


Enable port DAC
-
3


Enable address 0x83

E
-
4


E4


Enable port Interrupt0


Enable address 0xFC

E
-
5


E5


Enable port Interrupt1


Enable address 0xFD

E
-
6


E6


Enable port Interrupt2


Enable address 0xFE

E
-
7


E7


Enable port Interrupt3


Enable address 0xFF

Figure
12

Control

register B
-
C
-
D
-
E

in
Network

C
ontroller

Rev 5.0

Preliminary


14

4.3.1.3.

Status Register A

The node controller status register A is defined as follows:

Bit

Name

Function

0

Err CHN

Flag Error invalid channel

1

Err ERR

Flag Error error bit on AI

2

Err TR

Flag Error invalid Transaction (FF is
Reserved

for
Interrupts)

3

Err CMD

Flag Error invalid command

4
-
6





7

GE

This bit is the global OR of all error bits generated
in any channel in the GBT
-
SCA
.

Figure
13

Node
C
ontroller status register A

4.3.1.4.

Status Register B

The status register B is an 8
-
bit register containing the transaction number (TR#) of the last correctly
received command for any of the GBT
-
SCA

channels. This is necessary to support the case when a
packet traveling through the network gets corrupted after having reached the destination and the
GBT

has to find out whether the packet had already reached its destination or not.

4.3.1.5.

Command codes

The fo
llowing table summarizes the commands accepted by the node controller for operations on its
registers.

Below CH# is 0x4
0 except for “SCA Reset

.

Command

CMD

[Hex]

Command and

Reply Formats

Operation

Write
CR
A

0x00

C:
CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK

+ CRA

The
CR
A

is written with a byte

Write
CR
B

0x01

C:
CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK

+ CRB

The CR
B is written with a byte

Write CRC

0x02

C:
CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CR
C

The CRB is written with a byte

Write CRD

0x03

C:
CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CR
D

The CRC

is written with a byte

Write CRE

0x04

C:
CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CR
E

The CRE

is written with a byte

Read CRA

0x10

C:
CH#

+

TR#

+

CMD

R:

CH#

+

TR#

+ ACK + CRA

Read CRA

Read CRB

0x11

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CRB

Read CRB

Read CRC

0x1
2

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CR
C

Read CRC

Read CRD

0x1
3

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CR
D

Read CRD

Rev 5.0

Preliminary


15

Read CRE

0x1
4

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CR
E

Read CRE

Read SRA

0x20

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SRA

Send back the status register A

Read SRB

0x21

C:
CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SRB

Send back the status register B

Reset

0xFF

C:
CH# + TR# + CMD

R:
none

Reset the NC

SCA Reset

0xAA

C:
CH#=0xAA

+ TR# + CMD
=0xAA

R:
none

Reset the NC and all the front
-
end
ports

Figure
14

Commands for
the Network C
ontroller



Rev 5.0

Preliminary


16

5.

I
2
C CHANNEL

5.1.

General

The I2C

interface implements normal 7 bit addressing, long 10 bit addressing I2C transactions and
extended RAL mode transfers. The operations performed by the I2C interface are:



Single
byte read
-
write with normal 7 bit I2C

addressing



Single byte read
-
write extended I2C

with 10 bits addressing



Multi byte read
-
write extended I2C

with 10 bits addressing

5.1.1.1.

I2C

interface registers

Several
registers control the operation of the I2C

interface and are implemented in each of the 16
I2C channels.

The registers are cleared at reset.


Name

Comment

CRA

Control register A

MSK

Mask register for logical operations

SRA

Status register A

SRB

Status register B

Figure
15

Control and Status registers in I2C

channel

5.1.2.

I2C

Control registers

The Control register A in the I2C

interface is defined as follows:

Bit

Name

Function

1
-
0

SPEED

Denotes the speed of operation of the I2C

interface
(SCL clock rate):

00


100 kHz

01


200 kHz

10


400 kHz

11


1 MHz

2
-
4


-----


Reserved

5

EBRDCST

Enable broadcast operations.

Once set to “1” this bit enables the channel to accept
I2C

broadcast operations. This bit is initialised to
“0” after reset.

6

FACKW

Force acknowledge for write or RMW operation

Write operations and RMW
operations, which do not
generate errors, are not acknowledged. Setting this
bit to “1” forces an acknowledgement packet. This bit
is cleared at reset.

7


-----


Reserved

Figure
16

Control

register A in I2C

interface

5.1.3.

Logical mask register

This register can be written with an 8
-
bit value, which is used during logical operations on the I2C

bus.
Read
-
modify
-
write operations
and can only be executed in single
-
byte mode.

Rev 5.0

Preliminary


17

Three basic operations are allowed:

Logi
cal
AND
,
Logical
OR
,
Logical
XOR

a
nd are performed in
the following way:

1.

the I2C

interface reads a byte from the specified address

2.

a logical operation is performed with the mask register value

3.

the result is written back into the I2C

address

4.

the original value is returned to the GBT

(if CRA
[6] is set).

5.1.4.

I2C

Status Registers

Several registers are used to report the status of the I2C

channel

5.1.4.1.

Status Register A

This register contains the
following information:

Bit

Name

Function

0

Flag_error_Byte2NC

This bit reports the reply from the I2C

port
to the NC
. It is set if the reply word to
the NC fails.

1

Flag_error_PortBusy

This bit reports I2C

port busy status. If a
new command arrives when the port is still
busy

the flag is set.

2

SUCC

This bit is set when the last I2C

transaction was successfully executed.

3

I2CLOW

This bit is set to ‘1’ if the I2C

master
port finds
that the SDA line is pulled low
(“0”) before initiating a transaction. If
this happens the I2C bus is probably broken.
The bit represents the status of the SDA
line and cannot be reset.

4

Flag_error_rw

This bit is set if the commands that
requires

a specific code for read and write
operations make conflicts the command code.

5

INVCOM

This bit is set if an invalid command was
sent to the I2C

channel. The bit is cleared
by a channel reset.

6

NOACK

This bit
is set if the last operation has
not been acknowledged by the I2C

slave
acknowledge. This bit is set/reset at the
end of each I2C transaction

7

GE

This bit is set if any error has occurred on
the I2C

channel and is clear
ed only by a
channel reset command

Figure
17

Status register A in I2C

interface

5.1.4.2.

Status Register B

Status register B contains the number of the last correctly executed transaction (TR#). This register
is overwritten aft
er every I2C

transaction except read and write operations to/from the control and
status register.



Rev 5.0

Preliminary


18

5.1.5.

I2C

Commands

The following table summarizes all the commands accepted by the I2C

channels.

Below CH# is
0x10
-
0x1F
except for “SCA Reset
”.

Command

CMD

[Hex]

Command and

Reply Format

Single byte write normal mode

0x00

C:

CH#

+

TR#

+

CMD

+

A[7:0]

+

DW

R:

CH#

+

TR#

+

ACK

+

DR

Single byte read normal mode

0x01

C:

CH#

+

TR#

+

CMD

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

Single byte write extended
mode

0x02

C:

CH#

+

TR#

+

CMD

+

A[9:8]

+

A[7:0]

+

DW

R:

CH#

+

TR#

+

ACK

+

DR

Single byte read extended mode

0x03

C:

CH#

+

TR#

+

CMD

+

A[9:8]

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
AND in normal mode

0x80

C:

CH#

+

TR#

+

CMD

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
OR in normal mode

0x81

C:

CH#

+

TR#

+

CMD

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
XOR in normal mode

0x82

C:

CH#

+

TR#

+

CMD

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
AND in extended mode

0x83

C:

CH#

+

TR#

+

CMD

+

A[
9:8]

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
OR in extended mode

0x84

C:

CH#

+

TR#

+

CMD

+ A[9:8]

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

RMW
-
XOR in extended mode

0x85

C:

CH#

+

TR#

+

CMD

+ A[9:8]

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

Multiple Byte Write in extended
mode

(LEN <=28
=2
x
A
+26
x
DW
)

0x86

C:

CH#

+

TR#

+

CMD

+
LEN +
A[9:8]

+

A[7:0]

+

DW


R:

CH#

+

TR#

+

ACK

+

DR

Multiple Byte Read in extended
mode

(LEN <=28
=2+26
)

0x87

C:

CH#

+

TR#

+

CMD

+
LEN +
A[9:8]

+

A[7:0]

R:

CH#

+

TR#

+

ACK

+

DR

(LEN
-
2 bytes)

Multiple
Byte Write in normal
mode

(LEN <=28
=1
x
A
+27
x
DW
)

0x88

C:

CH# + TR# + CMD + LEN + A[7:0] + DW

R:
CH# + TR# + ACK + DR

Multiple Byte Read in normal
mode

(LEN <=28
=1
-
A
+27
-
DR
)

0x89

C:

CH# + TR# + CMD + LEN + A[7:0]

R:
CH# + TR# + ACK + DR

(LEN
-
1 bytes
)

Write

Control register A

0xf0

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH#

+

TR#

+

ACK

+

DR

Read Control register A

0xf1

C:

CH#

+

TR#

+

CMD

R:

CH#

+

TR#

+

ACK

+

DR

Read Status register A

0xf2

C:

CH#

+

TR#

+

CMD

R:

CH#

+

TR#

+

ACK

+

DR

Rev 5.0

Preliminary


19

Read Status register B

0xf3

C:

CH#

+

TR#

+

CMD

R:

CH#

+

TR#

+

ACK

+

DR

Write Mask register

0xf6

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH#

+

TR#

+

ACK

+

DR

Read Mask register

0xf7

C:

CH#

+

TR#

+

CMD

R:

CH#

+

TR#

+

ACK

+

DR

I2C

channel reset

0xff

C:

CH#

+

TR#

+

CMD

R:
none

SCA Reset




0xAA

C
: CH#=0xAA + TR# + CMD=0xAA

R
:

none


Reset the NC and all the front
-
end ports

Figure
18

Commands for I2C

channel



Rev 5.0

Preliminary


20

6.

ADC CHANNEL

6.1.

General

6.1.1.

ADC

Commands

The commands used for

operating the ADC

interface are defined in this paragraph.

Below CH# is
0x70 except for “SCA Reset
”.

Action

CMD

[Hex]

Command Packet Format

ADC

Reset channel

0xFF

C:

CH#

+

TR#

+

CMD

R:

none

Write control
register

0xF0

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CR

Read Control Register

0x
F1

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CR

Read Status Register

0x
F2

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SR

Write ADC

register

0xF3

C:

CH# + TR# + CMD + ADR
<X,X,5:0>

+ DATA

R:

CH# + TR# + ACK + SR

Read ADC

register

0x
F4

C:

CH# + TR# + CMD + ADR
<X,X,5:0>

R:

CH# + TR# + ACK + DR

SCA Reset




0xAA

C
: CH#=
0
xAA + TR# + CMD=
0
xAA

R
:

none


Reset the NC and all the front
-
end ports

Figure
19

ADC
channel Commands

NB. Here the ADC

Reset and SCA Reset

commands force the ADC internal channel
to be reset for
20 clock cycles.


There are
32
external
inputs for the ADC

module plus 2 internal channels
-

6
-
bit addressing
-

for
temperature and supply voltage monitoring.

The

architecture of the ADC

is shown in

Figure
32
.

Rev 5.0

Preliminary


21



Figure
20

SCA_ADC

architecture


6.1.2.

ADC

Blocks

The ADC

contains the following main blocks:




a wishbone slave interface,



a bandgap voltage reference,



a

12
-
bit ADC
,



calibration registers,



conversion and Calibration

Logic



a set of fuses that fixes the bandgap voltage reference.

The access to the internal registers of the ADC

is available through a wishbone interface. The user
can select one of the ADC input channels, start an ADC acquisition and read the ADC output simply
by accessing different registers.

A bandgap voltage reference gives to the ADC

a stable refer
ence voltage which can be adjusted for
a specific voltage by fusing the fuses. The reference voltage can also be adjust by adjusting the
value of the bandgap register.


Specifications



Digital interface I/O: Wishbone Standard Protocol



Operating temperature

range:
-
50°C
-
> +80°C



Power consumption: <
X??X
mW (VDD = 1.2V, T = 25°C


I =
X??X

mA)
?????



Supply voltage: single VDD @ 1.2V



Clock frequency: 40MHz

Rev 5.0

Preliminary


22

6.1.1.

SCA_ADC

Internal Registers

The ADC

contains thirteen user
-
accessible registers, which are listed in

Table
1
. Three registers
[SREG
, DLREG
, and DHREG
] are read only. All the others are write/read. However only ICREG

and
CALREG

can

be written at any time, the others may be written with some time restriction [see details
on the definition of each registers]. To address a specific register 4 bits are used, the address for
each register is indicated on the table below.


Wishbone
address
ADR_I<3:0>

Register name


Default content

[after reset]

0

0000

Status Register

SREG

-

1

0001

Control Register

CREG

0000_0000

2

0010

Input Channel Register

ICREG

0000_0000

3

0011

Data High Register

DHREG

0000_0000

4

0100

Data Low Register

DLREG

0000_0000

5

0101

Calibration

Register

CALREG

0000_0000

6

0110

BandgapCal High
Register

BGHREG

<fuses>

7

0111

BandgapCal Low
Register

BGLREG

<fuses>

8

1000

GmCal

High Register

GMHREG

0000_0001

9

1001

GmCal

Low Register

GMLREG

1111_1111

10

1010

IdCal High Register

IDHREG

0000_0001

11

1011

IdCal Low Register

IDLREG

1111_1111

12

1100

Test
Register

TREG

0000_0000

Table
1
. The SCA_ADC

register file

6.1.1.1.

Status Register (SREG
)

The Status Register is used to inform the user of the actual state of the converter.


Bit(s)

Name

Description

7

ready


If “1” ready for a new conversion
=
S
=
摯湥
=
If “1” conversion is finished and the value is available in
aAqA
=
R
=
calibrating
=
Calibration
=
in=progress
=
4
=
converting
=
Conversion= in=progress
=
P
=
sleeping
=
If “1” ADC
=
is=in=power=save=mode
=
O
=
testing
=
If “1” ADC
=
is=in=test=mode
=
<1WM[
=
rkrpba
=
=
Table
2
. Bit assignment of Status register (SREG
).

ready:


when [SREG
<7> = “1”] the ADC

is prepared to follow a new command.

done:

if [SREG
<6> = “1”] it means that the value on the Data registers is ready to be fetched.
Otherwise the value on DHREG

and DLREG

are not meaningful.

calibrating
, converting, sleeping:
reports the actual state of the converter.


6.1.1.2.

Control Register (CREG
) [write/read]

This register is used to control the converter. This registers can only be written when [SREG
<7> =
“1”] or [SREG<3> = “1”]
, this is, the converter is “ready” or in “power save” state.


Bit(s)

Name

Description

7

RESET

“1” to reset and after it is automatically set to “0” after
reset
=
S
=
tAhb=rm
=
“1” to end the “power save” mode
=
Rev 5.0

Preliminary


23

5

CALIBRATE

“1” to calibrate the ADC


and in the end is automatically set to “0”

4

CONVERT

“1” to start an A to D conversion

and in the end is automatically set to “0”

3

SLEEP

“1” to set ADC

in “Power save” mode

<2:0>

TEST MODE

“111” to start test mode

Table
3
. Bit assignment of Control register (CREG
).

reset:
setting this bit to “1” all the register will be set to their default value. This bit is also set
automatically to “0” during the reset state.

wake_up :

setting [C
REG
<6> = “1”] when the ADC

is in “power save” state will make the ADC
leave that same state. Otherwise the bit CREG<6> will have no effect. In both cases the bit is set “0”
on the following clock cycle.

calibrate:

when [CREG
<5> = “1”] the converter will start the calibration routine if the converter is
“ready ” [SREG

<5> = “7”]. After the calibration routine start the bit is set to “0”.

convert:
when [CREG
<4> = “1”] the converter will start
the calibration routine if the converter is
“ready ” [SREG

<5> = “7”] and [CREG<5> = “0”]. After the calibration routine start the bit is set to
“0”.

sleep:

if [CREG
<3> = “1”] and only when [CREG<5> = CREG<4>= “0”] the converter

will enter in
the “power save” state. This bit is only set to “0” by the user or if the converter is reset. Which means
that while this bit is “1” and if no more command are to be done the converter will enter/stay in the
power mode state.

test_mode:
when

[CREG
<2:0> = “1”] the test mode is enable.

6.1.1.3.

Input Channel Register (ICREG
)

This register will select the input channel from which the ADC

will convert.


Bit(s)

Name

Description

<7:6>

UNUSED


<5:0>

CHANNEL

Selects
the ADC

input channel

Table
4
. Bit assignment of Input channel register (ICREG
).

6.1.1.4.

Data High/Low Registers

When [SREG
<6> = “1”] the value stored in DATA is the result of the last acquisition.


Register

Bit(s)

Name

DHREG

<7:5>

UNUSED

<4:0>

DATA<12:8>

DLREG

<7:0>

DATA<7:0>

Table
5
. Bit assignment of Data High and Low registers (DHREG
/DLREG
).

6.1.1.5.

Calibration

Register (CALREG
)

Bit(s)

Name

Description

7

Enable_bgCal

“1” to use bgCal instead of fuses

6

Enable_gmCal

“1” to allow the user to write into gmCal register

5

Enable_idCal

“1” to allow the user to write into idCal

register

<4:0>

UNUSED


Table
6
. Bit assignment of Calibration

register (CALREG
).

Enable_bgCal:

when set [SREG
<7> = “1”] bits {BGHREG
<1:0>, BGLREG
<7:0>
} can be changed
to set the badgap voltage to another value.

Enable_gmCal :

when set [SREG
<6> = “1”] bits {GMHREG<1:0>, GMLREG<7:0>} can be
changed to set another value for the maximum charge current.

Rev 5.0

Preliminary


24

Enable_idCal :

when set [SREG
<5> = “1”] bits {BGHREG
<1:0>, BGLREG
<7:0>} can be changed
to set the another value for the maximum discharge current.

6.1.1.6.

BandgapCal High/Low Registers:


Register

Bit(s)

Name

BGHREG

<7:2>

UNUSED

<1:0>

bgCal <
9:8>

BGLREG

<7:0>

bgCal<7:0>

Table
7
. Bit assignment of BandgapCal High and Low registers (BGHREG
/BGLREG
).

6.1.1.7.

GmCal

High/Low Registers


Register

Bit(s)

Function/internal
signals

GMHREG

<7:2>

UNUSED

<1:0>

gmCal <9:8>

GMLREG

<7:0>

gmCal<7:0>

Table
8
. Bit assignment of GmCal

High and Low registers (GMHREG/GMLREG).

6.1.1.8.

IdCal High/Low Registers


Register

Bit(s)

Function/internal signals

IDHREG

<7:2>

UNUSED

<1:0>

idCal <9:8>

IDLREG

<7:0>

idCal<7:0>

Table
9
. Bit assignment of IdCal High and Low registers (IDHREG/IDLREG).

6.1.1.9.


Test Register (TREG
)

The bit allocation of the Test Register is described
below:


Table
10
. Bit assignment of Test register (TREG
).

noWait :

when set [TREG
<2> = “1”] the change from the charging phase to the discharge phase is
made in one clock cycle, this is, without having a clock cycle where the capacitor is not charging nor
discharging.

noGM, noID :

When both are “1” and if test mode active no calibration routine is performed.

6.1.1.10.

Register Access via the wishbone bus


WISHBONE is a system
-
on
-
Chip (SOC) interconnection architecture for portable IP cores, which
define parallel communication protocol betw
een IP cores.

(1)


The ADC

has a Wishbone Slave Interface that allows the user to read and write on the registers.


Interface description:


Bit(s)

Name

Function

<7:3>

UNUSED


2

noWait

When “1” the change from the charging phase to the discharge phase
is made in one clock cycle, this is, without having a clock cycle where
the capacitor is not charging nor discharging

1

noGM

If
testing mode is active this bit should be set equal to CALREG
<6>

0

noID

If testing mode is active this bit should be set equal to CALREG
<5>

Rev 5.0

Preliminary


25

Input Pin

Activity

Description

CLK_I



Clock input

RST_I

HIGH

Synchronous reset

WE_I

HIGH

Write Enable input indicates the current local bus cycle:

HIGH for write cycles, LOW for read cycles

CYC_I

HIGH

Cycle input indicates that a valid bus cycle is in progress.

STB_I

HIGH

Strobe input indicates that the slave is

selected.

ADR_I[3:0]



Address input bus

DAT_I[7:0]



Unidirectional data input bus


Output Pin

Activity

Description

ACK_O

HIGH

Acknowledge output indicates the termination of a normal
bus cycle

DAT_O[7:0]



Unidirectional data output bus

Table
11
. Wishbone signals


6.1.2.

Supported cycles

6.1.2.1.

SINGLE READ Cycle

The fig
ure sho
ws a SINGLE READ cycle. The bus protocol
works as follows:


CLOCK EDGE 0:
MASTER presents a valid address on
[ADR_I()] .

MASTER negates [WE_I] to indicate a READ cycle.

MASTER asserts [CYC_I] to indicate the start of the cycle.

MASTER asserts [STB_I] to indicate the start of the phase.


SETUP, EDGE 1: SLAVE decodes inputs, and r
esponding
SLAVE asserts [ACK_O].

SLAVE presents valid data on [DAT_O()].

SLAVE asserts [ACK_O] in response to [STB_I] to indicate
valid data.

MASTER monitors [ACK_O], and prepares to latch data on
[DAT_O()].


CLOCK EDGE 1: MASTER latches data on [DAT_O()] .

MASTER negates [STB_I] and [CYC_I] to indicate the end of
the cycle.

SLAVE negates [ACK_O] in response to negated [STB_I].

6.1.2.2.

SINGLE WRITE Cycle

The figure
shows a SINGLE
WRITE cycle. The bus protocol
works as follows:

CLOCK EDGE 0: MASTER presents a valid address on
[ADR_I()].

MASTER presents valid data on [DAT_I()].

MASTER asserts [WE_I] to indicate a WRITE cycle.

MASTER asserts [CYC_I] and to indicate the start of the
cycle.

MASTER asserts [STB_I] to indicate the start of the phase.


SETUP, EDGE 1: SLAVE decodes inputs, and responding
SLAVE asserts [ACK_O].

SLAVE prepares to latch data on [DAT_I()].


Figure
21

Single
read

cycle



Figure
22

Single write cycle

Rev 5.0

Preliminary


26

SLAVE asserts [ACK_O] in response to [STB_I] to indicate latched data.

MASTER monitors [ACK_O], and prepares to terminate the cycle.


CLOCK EDGE 1: SLAVE latches data on [DAT_I()].

MASTER negates [STB_I] and [CYC_I] to indicate the end of the cycle.

SLAVE negates [ACK_O[ in response to negated [STB_I].



6.1.2.3.

Block Read and Write
cycle

Block Read and Block Write cycle allows read/write in every clock cycle. The protocol is the same for
the single Cycle with the difference that the master should keep the CYC_I and STB_I signals
always to “1” during

the block cycle.


Description

Specification

General description:

8
-
bit Wishbone SLAVE

Supported cycles:

SLAVE, READ/WRITE

SLAVE, BLOCK READ/WRITE

Data port, size:

(1)

Data port, granularity:

Data port, maximum operand
size:

Data transfer ordering:

Data transfer sequencing:

8
-
bit

8
-
bit

8
-
bit

little endian

Undefined

Clock frequency constraints:

40M Hz

Supported signal list and cross
reference

to equivalent WISHBONE signals:

Signal Name

WISHBONE Equiv.

ACK_O

ACK_O

ADR_I(3..0)

ADR_I()

CLK_I

CLK_I

CYC_I

CYC_I

DAT_I(7..0)

DAT_I()

DAT_O(7..0)

DAT_O()

RST_I

RST_I

STB_I

STB_I

WE_I

WE_I

Table
12
. WISHBONE DATASHEET for the SCA_ADC

6.1.2.4.


ADC

Operations

HW reset


A hardware reset of the SCA_ADC

registers is performed forcing to 1 the WB_RST pin. As this reset
is used also to reset the bangap the WB_RST pin should be forced to “1” no less than 250ns [or 10
clock cycles @ 40 MHz].


SW reset

A software reset of the SCA_ADC

is performed when a “1” is written into the bit 7 of the Control
Register CREG

[CREG<7>].



Wake up

When the ADC

is in the “power save” state and in order to start a calibration or a conversion it is
needed to write a “1” into the bit 5 of the Control Register CREG

[CREG<5>
-
> wake_up] or write a
“0” into the bit 3 of the Control Register CREG [CREG<3>

-
> sleep].


Calibration

A calibration is performed when a “1” is written into the bit 5 of the Control Register CREG

[CREG<5>] and only if the ADC

is on “ready” state [SREG
<7> = “1”].


Set input
channel

Rev 5.0

Preliminary


27

The user should select which input channel the ADC

must use. For doing that is enough to write in
the Input Channel Register [ICREG
] the address of corresponding input channel according with the
table below.


ICREG
<5:0>

Name


ICREG
<5:0>

Name

000000

InputChannel_1

010000

InputChannel_17

000001

InputChannel_2

010001

InputChannel_18

000010

InputChannel_3

010010

InputChannel_19

000011

InputChannel_4

010011

InputChannel_20

000100

InputChannel_5

010100

InputChannel_21

000101

InputChannel_6

010101

InputChannel_22

000110

InputChannel_7

010110

InputChannel_23

000111

InputChannel_8

010111

InputChannel_24

001000

InputChannel_9

011000

InputChannel_25

001001

InputChannel_10

011001

InputChannel_26

001010

InputChannel_11

011010

InputChannel_27

001011

InputChannel_12

011011

InputChannel_28

001100

InputChannel_13

011100

InputChannel_29

001101

InputChannel_14

011101

InputChannel_30

001110

InputChannel_15

011110

InputChannel_31

001111

InputChannel_16

011111

InputChannel_32



100000

GND

100001

BandGap voltage


100010

Half_VDD

100011

GND

Table
13
. Input channel addresses.

Conversion/acquisition

A conversion is performed when a “1” is written into the bit 4 of the Control Register CREG

[CREG<4>] and only if the ADC

is on “ready” state [SREG
<7> = “1”] and CREG<5> is “0”, this is, no
calibration command is pending.


Read Result


When the bit 6 of the Status Register SREG
<6> contains a “1”, the result of the last acquisition can
be read:

o

Data<12:8> = DHREG
<4:0>

o

Data<7:0> = DLREG
<7:0>

SCA_ADC

conversion Operation

A conversion cycle of the ADC

can be simply started by setting the proper channel address in the
Input Channel Register and setting the conversion bit in the Control Register CREG
<
4>. The
conversion bit CREG<4> is cleared automatically at the beginning of the conversion. For instance, a
conversion on the input channel 5 can be started by writing “00000100” [0x04] into ICREG

to select
the desired input channel and then writing “00010000” [0x10] into the Control Register [CREG].



Rev 5.0

Preliminary


28

7.

JTAG CHANNEL

7.1.

General


A simplified JTAG

master channel is implemented in the GBT
-
SCA
. The
JTAG mas
ter generates the
three signals

TCK
,
TMS

and
TDO
.
TCK

is the scan chain clock,
TMS

the mode control bit for the
JTAG slave state machines and
TDO

is
the serial data sent to the scan chain. Data is returned on
the
TDI

line. The transitions on
TMS

and
TDO

take place upon the
rising

edge of
TCK
.
TDI

is
sampled on the positive edge of
TCK
. There is no autonomous JTAG controller


TAP state machine

and
the protocol
must be

implemented in software.

Each

com
mand is composed of 256 bits, which are split into

128 couples of
TMS

and
TDO

bits. It
takes 16
clock
cycles to load the command
into the port
BUFFER

as the Wish
-
Bone bus
is 16
-
bit
wide
. The control register
CRA

contains
an

ENREAD

bit that, if set at 1 via a
JTAG

CMD
WRITE
CRA

command, indicates that the
TDI

bit must be sampled and sent back along with the reply
packet. Hence, there are two possible replies, one

is the normal reply packet to acknowledge the
command and the other one contains also the
TDI

data which is sampled to fill
the first
128
LSB
bits

of the same
BUFFER
. Thus, any JTAG command must be fragmented into frames of 128 couples of
128 bits


(
TMS
,
T
DO
)


from the SCA to the front end and into frames of 128 bits (
TDI
) from the
front end to the SCA.
In other words, a command of any length can be composed into fragments of
128 bits for
TDO

and
TDI

and the last fragment must be completed with idle bits.

In addition, a
RES_OUT

pin (
CRA[7]
) is available to force an output pin to a continuous reset value.









Figure
23

256
-
bit JTAG

BUFFER


Through the WishBone bus the packets are segmented and transferred via couples of bytes as
shown in the top side of the figure below.




BYTE













The
JTAG

packets are segmented with an unlimited number of bytes.

Figure
24

JTAG

packets



The following registers control the operation of each JTAG

channel:


BUFFER

256
-
bit

(TMS TDO)

16
-
bit WB bus

TMS

TDO

TCK

TDI

WishBone segmentation





JTAG segmentation

RES_OUT

Rev 5.0

Preliminary


29


Name

Function

CRA

Control

R
egister

SRA

Status Register

Figure
25

Registers in JTAG

bus

The JTAG

Control register
CRA

is defined as follows:

Bit

Name

Function

1
-
0

SPEED

Denotes the width of the
strobe signals on the
port

00


1000ns

01


500ns

10


200ns

11


100ns.

Initialised to “00” after power up and reset.

4
-
2


-----

Reserved

5

ENREAD

Enable read

6

FACKW


7

RES_OUT

Reset Output Pin: default @ 0

Figure
26

Control Register in JTAG

channel

The JTAG

Status register
SRA

is defined as follows:

Bit

Name

Function

1
-
0


-----

Reserved

2

SUCC

Command succeded

4
-
3


-----

Reserved

5

INVCOM

Invalid Command

6

NOACK

No acknowledge

7

GE

Global error

Figure
27

Staus Register in JTAG

channel




Rev 5.0

Preliminary


30

7.1.1.

JTAG

command

The following table summarizes all the commands

accepted by the JTAG

channel.

Below CH# is
0x60 except for “SCA Reset
”.


Action

CMD

[Hex]

Command Packet Format

JTAG

CMD WRITE CRA

0xF0

C:

CH# + TR# + CMD +
DW

R:

CH# + TR# + ACK +
SRA

JTAG

CMD READ CRA

0xF1

C:

CH# + TR# + CMD

R:

CH# + TR# + ACK +
CRA

JTAG

CMD READ SRA

0xF2

C:

CH# + TR# + CMD

R:

CH# + TR# + ACK

+ SRA

JTAG

CMD RW

0xF3

C:

CH# + TR# + CMD + (TMS
,TDO
)[255:0]

R:

CH# + TR# + ACK + TDI
[127:0]

if ENREAD
=1

R:

CH# + TR# + ACK
+ CRA

if ENREAD
=0

JTAG

CMD RESET

0xFF

C:

CH# + TR# + CMD

R:

none

SCA Reset




0xAA

C
: CH#=0xAA

+ TR# + CMD=0xAA

R
:

none


Reset the NC and all the front
-
end ports


Figure
28

Commands

in JTAG

port

Rev 5.0

Preliminary


31

8.

MEMORY CHANNEL

8.1.

General


The Memory Data
bus implemented on the GBT
-
SCA

can address a 64KB memory

through a 16
-
bit
address and16
-
bit wide data interface. It can perform single and multiple byte read
-
write operations
as on a normal byte
-
wide memory device
. The operations foreseen are:



single byte read
-
write to address



multiple (up to 2K) bytes read
-
write to address with automatically incremented addresses



read
-
modify
-
write single byte to address with mask


Several registers control the operation of the memory

bus channel.

Name

Comment

CRA

Control register A

SRA

Status register A

Figure
29

Registers in memory

bus channel

To
simplify the design of simple peripheral devices connected to the GBT
-
SCA

memory

channel, the
GBT
-
SCA provides pre
-
decoding of up to two memory ranges defined in the window registers.

8.1.1.

Memory Bus Control registers

The Control register is defined as follows:

Bit

Name

Function

---

------


Reserved

Figure
30

Control register A in memory

channel

8.1.2.

Memory Bus Status Registers

Bit

Name

Function

0
-
4

------

Reserved

5

INVCOM

Invalid command received. Cleared by channel reset.

6

INVADD

Invalid address. One command with a memory

write
operation was received with an address outside both
window ranges. Cleared by channel reset.

7

GE

Global error. Logical OR of all error conditions in
the interface

Figure
31

Status register in memory

channel



Rev 5.0

Preliminary


32

8.1.3.

Memory Bus Commands

The commands used for operating the Memory Bus interface are defined in this
paragraph.

Below
CH# is 0x40 except for “SCA Reset
”.

Action

CMD

[Hex]

Command Packet Format

MBUS Reset channel

0xFF

C:

CH#

+

TR#

+

CMD

R:

none

Write control register

A

0x01

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CRA

Read Control Register

A

0x02

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CRA

Read Status Register

0x0f

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SRA

Single
16
-
bit Word

Write
to memory

0x10

C:

CH#

+

TR#

+

CMD

+

AH

+

AL

+

DH + DL

R:

CH# + TR# + ACK + SRA

Single
16
-
bit Word

Read
from memory

0x11

C:

CH#

+

TR#

+

CMD +

AH

+

AL

R:

CH# + TR# + ACK +
DH +

DL

SCA Reset




0xAA

C
: CH#=0xAA + TR# + CMD=0xAA

R
:

none


Reset the NC and all the front
-
end ports

Figure
32

Memory Bus channel Commands

The Memory address is divided into the two bytes AH and AL, for the
high and low part of the
address respectively. The block length (max 2 K) is also divided into two bytes, LENH and LENL.

In case of corrupted the GBT
-
SCA

signals the error condition through the bit 0 in Status Register A
in the Network Controller
.




Figure
33

Memory Bus Command Windows




Rev 5.0

Preliminary


33

9.

PARALLEL I/O CHANNEL

BUS (PIA)

9.1.

General


The
parallel I/O bus channel is an adapter similar to a Motorola PIA

interface, allowing parallel
connections with individually programmable direction in groups of 8 bits. Four independent byte PI
A

adapter channels are available in the GBT
-
SCA
.

These PIA ports are selected by default, at power
on, over the Memory channel as they share the same 40 output pins. To deselect this mode, and
serve the Memory channel, please refer to
Network Controller

CRA
<0>

bit that must be set to 1 via
a CRA write command.

The 4 PIA

ports also have
The following registers control the operation of each PIO channel:


Name

Function

GCR

General

control

register

SR

Status Register

DDR

Data
direction register for Port

DREG
_IN

Data
input
register

DREG
_OUT

Data
output
register

Figure
34

Registers in Parallel IO bus

9.1.1.

Registers in PIA

channel

The functions of the registers
are detailed in the following paragraphs.

An input strobe (
STRIN
), active high, is used to latch the PIO port to the DREG_IN

register. The
STRIN

ping is sampled by the clock and synchronized to avoid metastability
. For this reason it is
required the
STRIN

pin being high for at least 25 ns. Thus, at the rising edge of this pin the PIA

port is read out and saved into the DREG_IN, according to the DDREG bits, i.e. only the input pins
are updated.

The seve
nth bit of the
GCR
,
EN_STRIN
, can force the update independently of the
STRIN

pin. In
this case, with
EN_STRIN

at 1, the
DREG_IN

is continuously updated.


The
STROUT

pin indicated when the
DREG_OUT

has been updated to the
PI
A

port.





PIA


GCR, SR, DDR

DREG_IN

DREG_OUT

STRIN

STROUT

PIA 8

Rev 5.0

Preliminary


34

9.1.1.1.

General Control Register in PIO

The PIO Control register is defined as follows:

Bit

Name

Function

0

-

4


-----


Reserved

5

ENINTA

Enables generation of Interrupt messa
ge to GBT

on
reception of STRIN
. The reply will be in the form:

<#PORT> + FF + 00 + <DREG_IN
>

6


-----


Reserved

7

EN_STRIN

Enables the DATA_IN register
to be automatically
updated with the PIA

port: no STROBE_IN is
required. Default @ 0.

Figure
35

General Control Register in PIO channel

9.1.1.2.

Status Register in PIA

Bit

Name

Function

0

INT

An interrupt was
generated by a strobe on Port.
Cleared by writing a “1” to the CLR bit in GCR.

1
-
4

Reserved


5

INVCOM

Invalid command received. Cleared by channel
reset. Does not generate a GE

bit (see below)

6


-----


Reserved

7

GE

Global error. Logical OR of all error conditions
in the PIO interface

Figure
36

Status register in PIO channel



Rev 5.0

Preliminary


35

9.1.2.

Commands for PIA

channel

The following commands are defined for the PIO channel. Below CH# is 0x30
-
0x33

except for “SCA
Reset
”.

Action

CMD

[Hex]

Command Packet Format

Write General Control
Register

(GCR)

0x01

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + GCR

Read General Control
Register

(GCR)

0x02

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + GCR

Read Status Register

(SR)

0x03

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SR

Write
Data Direction
Register (
DDR
)

0x04

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + DDR

Read
Data Direction
Register (
DDR
)

0x05

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + DDR

Write Data Register

Out
(DREG_OUT
)

0x06

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + DREG
_OUT

Read Data Register

Out
(DREG_OUT
)

0x07

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + DREG
_OUT

CMD Read/Write PIA

0x08

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + DREG
_IN

PIA

Reset channel

0xFF

C:

CH#

+

TR#

+

CMD

R:

none

SCA Reset




0xAA

C
: CH#=0xAA + TR# + CMD=0xAA

R
:

none


Reset the NC and all the front
-
end ports

Figure
37

Commands for PIO channel



Rev 5.0

Preliminary


36

10.

DAC CHANNEL

10.1.

General

10.1.1.

DAC

Commands

The commands used for operating the DAC

interface are defined in this paragraph.

It consists of an
8
-
bit register that can be written or read out. Its value is then converted to the output analog port.

Below CH# is 0x80
-
83

except for “SCA Reset
”.

Action

CMD

[Hex]

Command
Packet Format

DAC

Reset channel

0xFF

C:

CH#

+

TR#

+

CMD

R:

none

Write control register

0xF0

C:

CH#

+

TR#

+

CMD

+

DW

R:

CH# + TR# + ACK + CR

Read Control Register

0x
F1

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + CR

Read Status Register

0x
F2

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + SR

Write DAC

register

0x
F3

C:

CH#

+

TR#

+

CMD

+

DATA

R:

CH# + TR# + ACK + SR

Read DAC

register

0x
F4

C:

CH#

+

TR#

+

CMD

R:

CH# + TR# + ACK + DR

SCA Reset




0xAA

C
: CH#=
0
xAA + TR# + CMD=
0
xAA

R
:

none


Reset the NC and all the front
-
end ports

Figure
38

DAC

channel Commands

NB. Here the DAC

Reset and SCA Reset

commands force the ADC

internal channel to be reset for
20 clock cycles.




Rev 5.0

Preliminary


37

11.

SPI CHANNEL

11.1.

General


The Serial Peripheral Interface (SPI
) bus is a synchronous
byte
-
oriented
serial
data link standard
that operates in full duplex mode
. Devices communicate only in master
-
to
-
slave mode where the
master device initiates the data frame.

The SPI master generates the three signals

Serial Clock

(
SCK
)
,
Slave Select (
SSb
)

and
Master Output Slave Input (
MOSI
)
.
SCK

is the clock,
SSb

the mode
control bit for the SPI slave state machines and
MOSI

is the serial data sent to the port. Data is
returned on the

Master Input Slave Output (
MISO
)

line. The t
ransitions on
all the signals take place

on the positive edge of
S
CK
.

Each command can

be
composed of
8
/16/32
MOSI

bits. It takes 1

to 2

clock cycles to load the
command into the port
BUFFER

-

32

bytes
-

as the Wish
-
Bone bus is 16
-
bit wide.
The control
register
CRA

contains an

ENREAD

bit that, if set at 1 via a
SPI

CMD WRITE CRA

command,
indicates that the
MISO

bit must be

sent back along with the reply packet. Hence, there are two
possible replies, one is the normal reply packet to acknowledge the command and the other one
contains also the
MISO

d
ata which is sampled to fill
the same
BUFFER
.

Thus, any SPI

command
must
be f
ragmented into frames of
8/16/
32

MOSI

bits

from the SCA
, plus the 3 common bytes CH#,
TR#, CMD,
t
o the front end and into frames of
8/16/
32

MISO

bits

from the front end to the SCA. In
other words, a command of any length can be composed into fragments for
MOSI

and
MISO

and the
last fragment must be completed with idle bits.









Figure
39

32
-
bit
SPI

SPDAT buffer


The following registers control the operation of each
SPI

channel:

Name

Function

SPCR

Control

R
egister

SPSR

Status Register

SPDAT

32
-
byte Register

Figure
40

Registers in
SPI

bus

MASTER


SPDAT

8
-
256
-
bit MOSI

16
-
bit WB bus

MOSI

SSb

SCK

MISO

SLAVE


SPDAT

8
-
256
-
bit MISO


Rev 5.0

Preliminary


38

The SPI

Control register is defined as follows:

Bit

Name

Function

1
-
0

SPEED

Denotes the width of the strobe signals on the
port

00


1000ns

01


500ns

10


200ns

11


100ns.

Initialised to “00” after power up and reset.

2

CPHA

Fixed to 0

3

CPOL

Fixed to 1

4

MSTR


5

DWOM


6

SPE


7

ENREAD

Enable read

Figure
41

Control Register in SPI

channel

The SPI

Status register is defined as follows:

Bit

Name

Function

0

INVCOM

Invalid
Command

1

NOACK

No acknowledge

2

GE

Global Error

3

-----

Reserved

4

MODF


5

-----

Reserved

6

WCOL


7

SPIF


Figure
42

Staus Register in SPI

channel



Rev 5.0

Preliminary


39

11.1.1.

SPI

command

The following table summarizes all the commands accepted by the
SPI

channel.

Below CH# is 0x02
except for “SCA Reset
”.


Action

CMD

[Hex]

Command Packet Format

SPI

CMD WRITE
SPCR

0xF0

C:

CH# + TR# + CMD + DW

R:

CH# + TR# + ACK + SRA

SPI

CMD READ
SPCR

0xF1

C:

CH# + TR# + CMD

R:

CH# + TR# + ACK + CRA

SPI

CMD READ
SPSR

0xF2

C:

CH# + TR# + CMD

R:

CH# + TR# + ACK + SRA

SPI

CMD RW

1 byte

0xF3

C:

CH# + TR# + CMD +
DW (MOSI
)

R:
CH# + TR# + ACK + DR (MISO
)

SPI

CMD RW

8 bytes

0xF4

C:

CH# + TR# + CMD +
8
*
DW (MOSI
)

R:
CH# + TR# + ACK + DR (MISO
)

if ENREAD
=0

R:
CH
# + TR# + ACK +
8*
DR (MISO
)


if ENREAD
=1

SPI

CMD RW

32 bytes

0xF5

C:

CH# + TR# + CMD +
3
2
*
DW (MOSI
)


R:
CH# + TR# + ACK + DR (MISO
)

if ENREAD
=0

R:
CH
# + TR# + ACK +
32*
DR (MISO
)

if ENREAD
=1

SPI

CMD RESET

0xFF

C:

CH# + TR# + CMD

R:

none

SCA Reset




0xAA

C
: CH#=0xAA

+ TR# + CMD=0xAA

R
:

none


Reset the NC and all the front
-
end ports


Figure
43

Commands in SPI

port

11.1.2.

SPI

Timing


Figure
44

SPI Timing Windows

Rev 5.0

Preliminary


40

12.

INT
ERRUPTS

Four asynchronous interrupts
,
active low,

are handled
.

The 4 channels cannot
be addressed but they can reply.

These interrupts

are polled
via

the Net
work Controller

that can provide
dedicated packet
s

backwards
to the GBT
. The interrupts packets are handled like the other rep
ly packets coming from the other
ports and hence there is no priority on the ports.


The
0xFF
transaction IDs

are
Reserved

for the
External and PIA

interrupts

s
o cannot be used
as normal

TR#


Name

Active

Coded Channel

Reply

Interrupt 0

Low

0x
F
C

0x
FC
-
F
F
-
00
-
F
C

Interrupt 1

Low

0x
F
D

0x FD
-
FF
-
0
-
0
F
D

Interrupt 2

Low

0x
F
E

0x

F
E
-
FF
-
00
-
F
E

Interrupt 3

Low

0xFF

0x

FF
-
FF
-
00
-
FF

Figure
45

Interrupts encoding

Rev 5.0

Preliminary


41

13.

PINOUT



150

PINS








Table
14
.
GBT
-
SCA pinout table





Left Side

PIN Name


Notes


Bottom Side

PIN Name


Notes


Right Side

PIN Name


Notes


Top Side

PIN Name


Notes

1

Pery VDD

PWR

SDA_o<15>

I
2
C
-
IO

MEM_PIA_o<39>

Shared
-
IO

ADC<31>

Analog
-
I

2

Pery GND

GND

SDA_o<14>

I
2
C
-
IO

MEM_PIA_o<38>

Shared
-
IO

ADC<30>

Analog
-
I

3

Dig VDD

PWR

SDA_o<13>

I
2
C
-
IO

MEM_PIA_o<37>

Shared
-
IO

ADC<29>

Analog
-
I

4

Dig GND

GND

SDA_o<12>

I
2
C
-
IO

MEM_PIA_o<36>

Shared
-
IO

ADC<28>

Analog
-
I

5

Ana VDD

PWR

SDA_o<11>

I
2
C
-
IO

MEM_PIA_o<35>

Shared
-
IO

ADC<27>

Analog
-
I

6

Ana GND

GND

SDA_o<10>

I
2
C
-
IO

MEM_PIA_o<34>

Shared
-
IO

ADC<26>

Analog
-
I

7

Link_clk_0+

ELINK
-
I

SDA_o<9>

I
2
C
-
IO

MEM_PIA_o<33>

Shared
-
IO

ADC<25>

Analog
-
I

8

Link_clk_0
-

ELINK
-
I

SDA_o<8>

I
2
C
-
IO

MEM_PIA_o<32>

Shared
-
IO

ADC<24>

Analog
-
I

9

Rx_sd_0+

ELINK
-
I

SDA_o<7>

I
2
C
-
IO

MEM_PIA_o<31>

Shared
-
IO

ADC<23>

Analog
-
I

0

Rx_sd_0
-

ELINK
-
I

SDA_o<6>

I
2
C
-
IO

MEM_PIA_o<30>

Shared
-
IO

ADC<22>

Analog
-
I

11

Tx_sd_0+

ELINK
-
O

SDA_o<5>

I
2
C
-
IO

MEM_PIA_o<29>

Shared
-
IO

ADC<21>

Analog
-
I

12

Tx_sd_0
-

ELINK
-
O

SDA_o<4>

I
2
C
-
IO

MEM_PIA_o<28>

Shared
-
IO

ADC<20>

Analog
-
I

13

Link_clk_1+

ELINK
-
I

SDA_o<3>

I
2
C
-
IO

MEM_PIA_o<27>

Shared
-
IO

ADC<19>

Analog
-
I

14

Link_clk_1
-

ELINK
-
I

SDA_o<2>

I
2
C
-
IO

MEM_PIA_o<26>

Shared
-
IO

ADC<18>

Analog
-
I

15

Rx_sd_1+

ELINK
-
I

SDA_o<1>

I
2
C
-
IO

MEM_PIA_o<25>

Shared
-
IO

ADC<17>

Analog
-
I

16

Rx_sd_1
-

ELINK
-
I

SDA_o<0>

I
2
C
-
IO

MEM_PIA_o<24>

Shared
-
IO

ADC<16>

Analog
-
I

17

Tx_sd_1+

ELINK
-
O

MISO

SPI
-
I

MEM_PIA_o<23>

Shared
-
IO

ADC<15>

Analog
-
I

18

Tx_sd_1
-

ELINK
-
O

MOSI

SPI
-
O

MEM_PIA_o<22>

Shared
-
IO

ADC<14>

Analog
-
I

19

SCL_o<15>

I
2
C
-
O

SCK

SPI
-
O

MEM_PIA_o<21>

Shared
-
IO

ADC<13>

Analog
-
I

20

SCL_o<14>

I
2
C
-
O

SSb

SPI
-
O

MEM_PIA_o<20>

Shared
-
IO

ADC<12>

Analog
-
I

21

SCL_o<13>

I
2
C
-
O

MEM_PIA_o<13>

Shared
-
IO

MEM_PIA_o<19>

Shared
-
IO

ADC<11>

Analog
-
I

22

SCL_o<12>

I
2
C
-
O

MEM_PIA_o<12>

Shared
-
IO

MEM_PIA_o<18>

Shared
-
IO

ADC<10>

Analog
-
I

23

SCL_o<11>

I
2
C
-
O

MEM_PIA_o<11>

Shared
-
IO

MEM_PIA_o<17>

Shared
-
IO

ADC<9>

Analog
-
I

24

SCL_o<10>

I
2
C
-
O

MEM_PIA_o<10>

Shared
-
IO

MEM_PIA_o<16>

Shared
-
IO

ADC<8>

Analog
-
I

25

SCL_o<9>

I
2
C
-
O

MEM_PIA_o<9>

Shared
-
IO

MEM_PIA_o<15>

Shared
-
IO

ADC<7>

Analog
-
I

26

SCL_o<
8>

I
2
C
-
O

MEM_PIA_o<8>

Shared
-
IO

MEM_PIA_o<14>

Shared
-
IO

ADC<6>

Analog
-
I

27

SCL_o<7>

I
2
C
-
O

MEM_PIA_o<7>

Shared
-
IO

TDI

JTAG
-
I

ADC<5>

Analog
-
I

28

SCL_o<6>

I
2
C
-
O

MEM_PIA_o<6>

Shared
-
IO

TMS

JTAG
-
I

ADC<4>

Analog
-
I

29

SCL_o<5>

I
2
C
-
O

MEM_PIA_o<5>

Shared
-
IO

TCK

JTAG
-
I

ADC<3>

Analog
-
I

30

SCL_o<4>

I
2
C
-
O

MEM_PIA_o<4>

Shared
-
IO

TDO

JTAG
-
O

ADC<2>

Analog
-
I

31

SCL_o<3>

I
2
C
-
O

MEM_PIA_o<3>

Shared
-
IO

RES_OUT

JTAG
-
O

ADC<1>

Analog
-
I

32

SCL_o<2>

I
2
C
-
O

MEM_PIA_o<2>

Shared
-
IO

Eth
-
Sel

Output Info

ADC<0>

Analog
-
I

33

SCL_o<1>

I
2
C
-
O

MEM_PIA_o<1>

Shared
-
IO

Ana VDD

PWR

DAC
-
0

Analog
-
O

34

SCL_o<0>

I
2
C
-
O

MEM_PIA_o<0>

Shared
-
IO

Ana GND

GND

DAC
-
1

Analog
-
O

35

Int0

Interrupt
-
I

Reset_in

RESET
-
I

Dig VDD

PWR

DAC
-
2

Analog
-
O

36

Int1

Interrupt
-
I

Ext_
Reset_Out

RESET
-
O

Dig
GND

GND

DAC
-
3

Analog
-
O

37

Int2

Interrupt
-
I

ADC

ADC

Pery VDD

PWR



38

Int3

Interrupt
-
I

ADC

ADC

Pery GND

GND



Rev 5.0

Preliminary


42

14.

INDEX

14.1.

Index of Paragraphs

1.

Document History

................................
................................
................................
.........................

2

2.

General

................................
................................
................................
................................
..........

3

2.1.

Overview of the GBT System

................................
................................
................................

3

2.2.

Overview of the GBT
-
SCA Architecture
................................
................................
...............

4

2.3.

Radiation toleranc
e features
................................
................................
................................
...

8

3.

SCA PACKET description

................................
................................
................................
...........

9

3.1.

The protocol

................................
................................
................................
...........................

9

3.2.

PAYLOAD Format

................................
................................
................................
..............

10

4.

ChannelS IN GBT
-
SCA
................................
................................
................................
..............

11

4.1.

General

................................
................................
................................
................................
.

11

4.2.

Allocations of channels in the GBT
-
SCA
................................
................................
............

11

4.3.

GBT
-
SCA controller

................................
................................
................................
............

12

5.

i
2
c channel

................................
................................
................................
................................
...

16

5.1.

General

................................
................................
................................
................................
.

16

5.1.2.

I2C Control registers

................................
................................
................................
.....

16

5.1.3.

Logical mask register

................................
................................
................................
....

16

5.1.4.

I2C Status Registers

................................
................................
................................
......

17

5.1.5.

I2C Commands

................................
................................
................................
.............

18

6.

ADC Channel

................................
................................
................................
..............................

20

6.1.

General

................................
................................
................................
................................
.

20

6.1.1.

ADC Commands

................................
................................
................................
...........

20

6.1.2.

ADC Blocks

................................
................................
................................
..................

21

6.1.1.

SCA_ADC Internal Registers

................................
................................
.......................

22

6.1.2.

Supported cycles

................................
................................
................................
...........

25

7.

JTAG Channel
................................
................................
................................
.............................

28

7.1.

General

................................
................................
................................
................................
.

28

7.1.1.

JTAG command

................................
................................
................................
............

30

8.

Memory Channel
................................
................................
................................
.........................

31

8.1.

General

................................
................................
................................
................................
.

31

8.1.1.

Memory Bus Control registers

................................
................................
......................

31

8.1.2.

Memory Bus Status Registers

................................
................................
.......................

31

8.1.3.

Memory Bus Commands

................................
................................
..............................

32

9.

parallel i/o Channel bus (pia)

................................
................................
................................
......

33

9.1.

General

................................
................................
................................
................................
.

33

9.1.1.

Registers in PIA channel
................................
................................
...............................

33

9.1.2.

Commands for PIA channel

................................
................................
..........................

35

10.

DAC Channel

................................
................................
................................
............................

36

10.1.

General

................................
................................
................................
...............................

36

10.1.1.

DAC Commands

................................
................................
................................
.........

36

11.

SPI Channel
................................
................................
................................
...............................

37

11.1.

General

................................
................................
................................
...............................

37

11.1.1.

SPI command

................................
................................
................................
..............

39

11.1.2.

SPI Timing

................................
................................
................................
..................

39

12.

interrupts

................................
................................
................................
................................
...

40

13.

PINOUT


150 pins

................................
................................
................................
..................

41

Rev 5.0

Preliminary


43

14.

INDEX

................................
................................
................................
................................
......

42

14.1.

Index of Paragraphs

................................
................................
................................
...........

42

14.1.

Index of Terms

................................
................................
................................
...................

44

14.2.

Index of Figures

................................
................................
................................
.................

45

14.3.

Index of Tables
................................
................................
................................
...................

45




Rev 5.0

Preliminary


44

14.1.

Index of Terms

ADC, 6, 11, 13, 20, 21, 22, 23, 24, 26, 27, 36

BGHREG
, 22, 23, 24

BGLREG
, 22, 23, 24

Block Read and Write cycle, 26

BUFFER
, 28, 37

Calibration
, 21, 22, 23, 26

CALREG
, 22, 23, 24

Channel Number, 11

Conversion/acquisition
, 27

CRA, 12, 14, 16, 17, 28, 29, 30, 31, 32, 33,
37, 39

CRC, 9, 12, 14

CRD, 12, 14

CRE, 12, 14, 15

CREG
, 22, 23, 26, 27

DAC, 6, 11, 13, 36

DHREG
, 22,
23, 27

DLREG
, 22, 23, 27

DREG_IN
, 33, 34, 35

DREG_OUT
, 33, 35

ENREAD
, 28, 29, 30, 37, 38, 39

Err CHN, 14

Err ERR, 14

Err TR, 14

GBT, 1, 3, 4, 5, 6, 7, 9, 11, 12, 14, 17, 28, 31,
32, 33, 34, 40

GBT
-
SCA, 1, 3, 4, 5, 6, 7, 11, 12, 14, 20, 28,
31, 32, 33, 36,
37

GE, 14, 17, 29, 31, 34, 38

GmCal
, 22, 24

HW reset
, 26

I2C
, 5, 6, 10, 11, 13, 16, 17, 18, 19

ICREG
, 22, 23, 27

Interrupt Channel, 11

interrupts
, 6, 11, 40

INVCOM, 17, 29, 31, 34, 38

JTAG
, 5, 10, 11, 13, 28, 29, 30

memory
, 6, 31, 32

Memory Channel, 5, 11

MISO
, 37, 39

MOSI
, 37, 39

MSK, 16

Network Controller
, 5, 6, 8, 11, 12, 15, 32,
33, 40

NOACK, 17, 29, 38

PIA
, 5, 6, 11, 12, 13, 33, 34, 35, 40

Read Control Register, 20, 32, 36

Read Result
, 27

Read Status Register, 20, 32, 35, 36

RES_OUT
, 28, 29

Reset Tree,

6

Reset_Out
, 12, 41

SCA Reset, 11, 14, 15, 18, 19, 20, 30, 32, 35,
36, 39

SCK
, 37

Set input channel
, 26

SINGLE READ Cycle
, 25

SINGLE WRITE Cycle
, 25

SPI, 6, 10, 11, 13, 37, 38, 39

SRA, 12, 15, 16, 29, 30, 31, 32, 39

SRB, 12, 15, 16

SREG
, 22, 23, 24, 26,
27

SSb
, 37

STRIN
, 33, 34

STROUT
, 33

SW reset
, 26

TCK
, 28

TDI
, 28, 30

TDO
, 28, 30

TMS
, 28, 30

TREG
, 22, 24

Wake up
, 26

Write control register, 20, 32, 36




Rev 5.0

Preliminary


45


14.2.

Index of Figures

Figure 1

Control module, simplified view

................................
................................
............................

4

Figure 2

E
-
port Redundancy

................................
................................
................................
................

5

Figure 3:

block diagram of the GBT
-
SCA:
................................
................................
..........................

7

Figure 4
:
Logic Reset Tree of the GBT
-
SCA

................................
................................
......................

7

Figure 5
:
MAC to
Network Controller interface

................................
................................
.................

8

Figure 6:
SCA Packet

communicat
ion system

................................
................................
...................

9

Figure 7:
SCA
-
to
-
Port Command Packet

example

................................
................................
........

10

Figure 8:
Port
-
to
-
SCA Reply Packet

example

................................
................................
................

10

Figure 9: Channel number allocation
................................
................................
................................
.

11

Figure 10: Control and Status registers in GBT
-
SCA Controller

................................
......................

12

Figure 11 Network

Controller control register A

................................
................................
..............

12

Figure 12 Control register B
-
C
-
D
-
E in Network Controller
................................
..............................

13

Figure 13

Node Controller status register A

................................
................................
......................

14

Figure 14

Commands for the Network Controller

................................
................................
.............

15

Figure 15

Control and Status registers in I2C cha
nnel

................................
................................
......

16

Figure 16 Control register A in I2C interface

................................
................................
....................

16

Figure 17

Sta
tus register A in I2C interface

................................
................................
......................

17

Figure 18

Commands for I2C channel

................................
................................
...............................

19

Figure 19

ADC channel Commands

................................
................................
................................
..

20

Figure 20 SCA_ADC architecture

................................
................................
................................
.....

21

Figure 23 256
-
bit JTAG BUFFER
................................
................................
................................
.....

28

Figure 24 JTAG packets

................................
................................
................................
....................

28

Figure 25

Registers in JTAG bus

................................
................................
................................
.......

29

Figure 26 Control Register in JTAG channel

................................
................................
....................

29

Figure 27 Staus Register in JTAG channel

................................
................................
........................

29

Figure 28

Commands in JTAG port
................................
................................
................................
...

30

Figure 29

Registers in memory b
us channel

................................
................................
......................

31

Figure 30

Control register A in memory channel

................................
................................
..............

31

Figur
e 31

Status register in memory channel

................................
................................
....................

31

Figure 32

Memory Bus channel Commands

................................
................................
.....................

32

Figure 33

Memory Bus Command Windows

................................
................................
....................

32

Figure 34

Registers in Parallel IO bus

................................
................................
...............................

33

Figure 35 General Control Register in PIO channel

................................
................................
..........

34

Figure 36 Status register in PIO channel

................................
................................
...........................

34

Figure 37

Commands for PIO
channel

................................
................................
..............................

35

Figure 38

DAC channel Commands

................................
................................
................................
..

36

Figure 39 32
-
bit SPI SPDAT buffer

................................
................................
................................
..

37

Figure 40

Registers in SPI bus

................................
................................
................................
...........

37

Figure 41 Control Register in SPI channel

................................
................................
........................

38

Figure 42 Staus Register in SPI channel

................................
................................
............................

38

Figure 43

Commands in SPI port
................................
................................
................................
.......

39

Figure 44

SPI Timing Windows

................................
................................
................................
........

39

Figure 45

Interrupts encoding

................................
................................
................................
............

40

14.3.

Index of Tables

Table 1. The SCA_ADC register file

................................
................................
................................
................................
................

22

Table 2. Bit assignment of Status register (SREG).

................................
................................
................................
.......................

22

Table 3. Bit assignment of Control register (CREG).

................................
................................
................................
....................

23

Rev 5.0

Preliminary


46

Table 4. Bit assignment of Input channel re
gister (ICREG).

................................
................................
................................
........

23

Table 5. Bit assignment of Data High and Low registers (DHREG/DLREG).

................................
................................
.........

23

Table 6. Bit assignment of Calibration register (CALREG).
................................
................................
................................
........

23

Table 7. Bit assignment of BandgapCal High and Low registers (BGHREG/BGLREG).
................................
......................

24

Table 8. Bit assi
gnment of GmCal High and Low registers (GMHREG/GMLREG).

................................
.............................

24

Table 9. Bit assignment of IdCal High and Low registers (IDHREG/IDLREG).
................................
................................
.....

24

Table 10. Bit assignment of Test register (TREG).

................................
................................
................................
........................

24

Table 11. Wishbone signals

................................
................................
................................
................................
................................

25

Table 12. WISHBONE DATASHEET for the SCA_ADC

................................
................................
................................
..........

26

Table 13. Input channel addresses.

................................
................................
................................
................................
....................

27

Table 14. GBT
-
SCA pinout table

................................
................................
................................
................................
......................

41