publications

designpadΤεχνίτη Νοημοσύνη και Ρομποτική

1 Δεκ 2013 (πριν από 3 χρόνια και 11 μήνες)

75 εμφανίσεις

Zoznam publikácií



2011

1.

GRAMATOVÁ E., MÁNIK M.: Efficient Diagnostics Algorithms for Regular
Computing Structures.
Proc. of the IEEE DDECS Symposium (Design and
Diagnostics of Digital Circuits and Systems), Computer Society, 2011, str.
87
-
92.

2.

DOBAI, R.
, BALÁ
Ž,

M., TREBATICKÝ, P. MALÍK, P., GRAMATOVÁ, E:
A Low
-
overhead BIST Architecture for Digital Data Processing Circuits,“ In:

International Joint Conferences on Computer, Information, and Systems Sciences,
and Engineering (CISSE 10)
, Springer, 2011. Prijat
é na publikovanie.


2010

3.

DOBAI R., GRAMATOVÁ E.: Deductive Fault Simulation Technique for Asynchronous
Circuits. Computing and
I
nformatics, Bratislava: Institute of Informatics, Slovak
Academy of Sciences, 2010
, vol. 29, str. 1025


1043.

4.

DOBAI R., GRAMATO
VÁ E.
A Novel Automatic Test Pattern Generator for
Asynchronous Sequential Digital Circuits,
MICROELECTRONICS JOURNAL
,

vol.

42


Issue:
3
, str.

501
-
508

5.

BALÁŽ M. DOBAI R., GRAMATOVÁ E.: Delay Faults Testing
(
1,497 AH).
In: R.
Ubar, J. Raik, H. T. Vierhaus. Design and Test Technology for Dependable Systems
-
on
-
Chip. Hershey, Pennsylvania: IGI Global, 2010.

6.

FISCHEROVÁ M., GRAMATOVÁ E.: Memory testing and reco
nfiguration
(1,
63

AH). In: R. Ubar, J. Raik, H. T. Vierhaus. Design and Test Technology for
Dependable Systems
-
on
-
Chip. Hershey, Pennsylvania: IGI Global, 2010.


7.

DOBAI, R., GRAMATOVÁ, E.

“Test Pattern Generation for the Combinational
Representation of Asyn
chronous Circuits,“ In:
13th IEEE International
Symposium on Design and Diagnostics of Electronic Circuits and Systems
, 2010.
str. 323

328
.

8.

BALÁ
Ž, M., BEČKOVÁ, E., GRAMATOVÁ E. Wrapper

Wrapper tool
-

Learning and application of digital system testability to soc cores
.
2010
Proceedings
-

2010 IEEE Region 8 International Conference on Computational
Technologies in Electrical and Electronics Engineer
ing, SIBIRCON
-
2010

, art.
no. 5555111, pp. 384
-
389

2009


9.

R. Dobai, E. Gramatová, “Deductive Fault Simulation for Asynchronous
Sequential Circuits,“ In:
2009

12th EUROMICRO Conference on Digital System
Design, Architectures, Methods and Tools: DSD 2009
, 200
9.
str
. 459

464.

10.

R. Dobai, E. Gramatová, “Deductive fault simulation for asynchronous sequential
circuits,“ In:
MEMICS 2009: Fifth Doctoral Workshop on Mathematical and
Engineering Methods in Computer Science
, 2009.
str
. 229.

11.

MÁNIK M., GRAMATOVÁ, E.
Diagno
sis of faulty units in regular graphs under
the PMC model. In 2009 IEEE Symposium on Design and Diagnostics of
Electronic Circuits and Systems: proceedings. Editor Michel Renovell, Hans
Manhaeve, Jindra Drábková, Martin Rozkovec, Ondřej Novák, Zdeněk Plíva
, Jiří
Jeníček.
-

Piscataway, NJ : Institute of Electrical and Electronic Engineers, Inc.,
2009. ISBN 978
-
1
-
4244
-
3339
-
1, str. 202
-
205.


2008


12.

Gramatová, E., Fischerová, M.: Memory test, BIST and self repair. In Design and
Test Technology for Dependable Har
dware/Software Systems.
-

Cottbus : BTU,
2008, 2008, cD, 84 slides.

13.

Mánik, M., Gramatová, E.: Boolean formalisation of the PMC model for faulty
units diagnosis in regular multi
-
processor systems. In 2008 IEEE Workshop on
Design and Diagnostics of Electroni
c Circuits and Systems : proceedings.
-

Bratislava : The Institute of Electrical and Electronic Engineers, 2008. ISBN 978
-
1
-
4244
-
2276
-
0,
str
. 144
-
145.

2007


14.

Gramatová,

E., Fischerová, M., Smiščík, R.: Software tool for on
-
line testing
techniques application. In ECP´07 : proceedings of the 6th Electronic Circuits and
Systems Conference.
-

Bratislava : Vydavatežstvo STU, 2007. ISBN 978
-
80
-
227
-
2697
-
9,
str
. 133
-
136.

2006

15.

Gr
amatová, E.: Test Generation Experiments for Delay Fault in Digital Circuits,
Proc. of Electronic Devices and Systems Conference (EDS 2006), Brno, Česká
republika, september 2006, ISBN 80
-
214
-
3246
-
2, s
tr
. 74
-
78.

2005


16.

Baláž, M., Fischerová, M., Gramatová,

E., Jutman, A., Kotásek, Z., Novák, O.,
Pikula, T., Raik, J., Strnadel, J., Ubar, R., Záhradka, J.: Testing Tools
forTtrainning and Education. Proceeding of the 12
th

International Conference
MIXDES 2005, ISBN 83
-
919289
-
9
-
3, Krakow, Poland, june 2005,
str
.

671
-
676.

17.

Pikula, T., Giorgio di Natale, Gramatová, E.: Built
-
in Self
-
Test Generation for
Delay Faults
-

A case study. Prceedings of the 5
th

Electronic Circuits and Systems
Conference (ECS'05), Bratislava, Slovak Republic, september 2005,
str
. 11
-

14.

18.

Ba
láž, M., Gramatová, E., Pikula, T., Fischerová;, M.: eTool for Teaching and
Application of Digital System Testability Techniques. In EUROCON 2005,
Belegrade, Serbia and Monte Negro, november 2005,
str
. 831
-
834.

19.

Novák, O., Gramatová, E., Ubar, R.: Handbook

of Testing Electronic Systems.
Vydavatel: CVUT Praha, 2005
.


20.

Gramatová, E.: Handbook of Testing Electronic Systems. Príspevky do kapitol
Defects, Faults, Fault Models, Test Generation Techniques and Algorithms,
Appendix1.Testing Tools. Vydavatel: CVUT Pra
ha, 2005,
str
. 35.

2004


21.

Baláž, M., Gramatová, E.: Wrapper Connection Technique for Embedded Cores.
Proceedings of the 9th Biennial Baltic Electronics Conference (BEC), ISBN
9985
-
59
-
462
-
2, Tallinn, Estonia, október 2004,
str
. 209
-
212, (1,0).

22.

Mánik, M., Gramatová, E.: An Extended
Formalisation in the PMC System
Model for Faulty Units Identification. Proceedings of the 9th Biennial Baltic
Electronics Conference (BEC), ISBN 9985
-
59
-
462
-
2,Tallinn, Estonia, október
2004,
str
. 213
-
216, (0,5).

23.

Gramatová, E., Fischerová, M., Pikula, T.,
Ba
láž, M., Lauko, R., Trebatický, P.:
Training Set for Design Testability and Built
-
in Self
-
test Techniques of Digital
Circuits and Systems.
Proceedings of the49. Internationales Wissenschaftliches
Kolloquium, Ilmenau, Shaker VERLAG, ISBN 3
-
8322
-
2824 septemb
er 2004, pp.
498
-
504, (0,9).

24.

Jutman, A., Gramatová, E., Pikula, T., Ubar, R.: E
-
learning Tools for Teaching
Self
-
Test of Digital Electronics. Proceedings of 15th EAEEIE Conference on
Innovation in Education for Electrical and Information Engineering, Sofi
a,
Bulgaria, máj 2004, pp. 267
-
272, (0,5).

25.

Baláž, M., Pikula, T., Lauko, R., Fischerová, M., Gramatová, E.: eLearning and
eTraining Tools for Testability Techniques of Digital Circuits and Systems.
Proceedings of the 5
th

International Conference Virtual University, Bratislava,
Slovak Republic, dece
mber 2004, pp. 95
-
100, (0,8).

26.

Gramatová, E., Fischerová, M.: Zborník z česko
-

slovenského seminára pre
študentov doktorandského štúdia PAD 2004. ISBN 80
-
969202
-
0
-
0, Moravany
nad Váhom, Slovensko, september 2004, editori zborníka.

2003


27.

Baláž, M., Gramato
vá, E., Fischerová, M.: Test Wrapper Application To
Embedded Cores as a Java Applet. In: Proceedings of the IEEE Design and
Diagnostics of Electronic Circuits and Systems Workshop (DDECS), Poznañ,
Poland, April 2003, ISBN 83
-
7143
-
557
-
6, pp. 33
-
40.

28.

Pikula,

T., Gramatová, E.: BIST Architecture Application for Digital Circuits as a
Java Applet. In: Proceedings of the IEEE Workshop on Design and Diagnostics
of Electronic Circuits and Systems Workshop (DDECS), Poznañ, Poland, April
2003, ISBN 83
-
7143
-
557
-
6, pp.

305
-
306.

29.

Baláž, M., Gramatová, E.: Optimization Techniques for Parallel Interface of Test
Wrapper for Embedded Cores. In: Digest of papers, IEEE European Test
Workshop (ETW), Maastricht, The Netherlands, May 2003, pp. 25
-
26.

30.

Pikula, T., Gramatová, E., F
ischerová, M.: Automatic Design of Cellular
Automata for Generating Deterministic Test Patterns. In: Digest of Papers, IEEE
European Test Workshop (ETW), Maastricht, The Netherlands, May 2003, pp.
285
-
286.

31.

Baláž, M., Gramatová, E., Fischerová, M.: Automat
ic Optimization of Wrapper
Parallel Interface Constructions Applied to Digital Cores. In: Proceedings of the
IEEE Region 8 EUROCON 2003 Conference, Ljubljana, Slovenia, September
2003, pp. 44
-
47.

32.

Pikula, T., Gramatová, E., Fischerová, M.: Deterministic Te
st Generation for
Digital Circuits by Cellular Automata in a Java Applet.In: Proceedings of the
IEEE Region 8 EUROCON 2003 Conference, Ljubljana, Slovenia
, September
2003, pp
. 40
-
43.

2002


33.

Cibáková, T., Fischerová, M., Gramatová, E., Kuzmicz, W., Pleskacz
, W.A.,
Raik, J., Ubar, R.: Hierarchical test generation for combinational circuits with
real defect coverage. In : Microelectronics Reliability 42 (2002), pp. 1141
-
1149.

34.

Schneider, A., Ivask, E., Mikloš, P., Raik, J., Diener, K.H., Ubar, R., Cibáková,
T.
, Gramatová, E.: Internet
-
based Collaborative Test Generation with
MOSCITO. In : Proceedings 2002 Design, Automation and Test in Europe
(DATE), Paris, France, March, 2002,
str
. 221
-
226.

35.

Baláž, M., Pikula, T., Trebatický, P., Gramatová E.: Memory Self
-
Testing Using
a Non
-
Linear Cellular Automaton in the Circuit for Data Encryption. In:
Proceedings of the IEEE Design and Diagnostics of Electronic Circuits and
Systems Workshop (DDECS), ISBN
80
-
214
-
2094
-
4, Brno, Czech Republic,
April 2002,
str
. 352
-
355.

36.

Baláž, M., Gramatová, E., Fischerová, M.: Automatic Synthesis of Testing Ports
for Digital Circuits. In: Proceedings of the eleventh International
Electrotechnical and Computer Science Confere
nce ERK 2002, Portorož,
Slovenia, ISSN 1581
-
4572, September, 2002,
str
. 65
-
68.

37.

Schneider, K., Diener, H., Gramatová, E., Fischerová, M., Ivask, E., Ubar, R.,
Pleskacz, W., Kuzmicz, W.: Defect
-
Oriented Test Generation and Fault
Simulation in the Enviroment

of MOSCITO. In: Proceedings of the 8
th

Biennial
Baltic Electronics Conference (BEC), ISBN 9985
-
59
-
292
-
1 Tallinn, Estonia,
October 2002,
str
. 303
-
305.

38.

Pikula, T., Fischerová, M., Gramatová, E.: Automatic Synthesis BIST Tool for
Digital Circuits In: Procee
dings of the 8th Biennial Baltic Electronics
Conference (BEC), ISBN 9985
-
59
-
292
-
1, Tallinn, Estonia, October 2002,
str
.
261
-
263.

2001


39.

J. Štefanovič, P. Mikloš, E. Gramatová: A New Open Platform for VHDL
Modelling at the Behavioural Level, Proc. of the 4
th

DDECS 2001, Gyor,
Hungary, April 2001, pp. 141
-
144.

40.

T. Cibáková, E. Gramatová, W. Kuzmicz, W. Pleskacz, J. Raik, R. Ubar:
Defect
-
Orie
nted Library Builder and Hierarchical Test Generation, Proc. of the
4
th

DDECS 2001, Gyor, Hungary, April 2001, pp. 163
-
168.

41.

J. Štefanovič, P. Mikloš, E. Gramatová, M. Fischerová: Test Pattern Generation
Using a New Open Platform at the Behavioural Level,
Informal Digest of the
IEEE European Test Workshop, Stockholm, Sweden, May 2001, pp. 211
-
213.

42.

T. Cibáková, M. Fischerová, E. Gramatová, W. Kuzmicz, W. Pleskacz, J. Raik,
R. Ubar: Defect
-
Oriented Test Generation Using Probabilistic Estimation, Proc.
of the

8th International Conference MIXDES, Zakopane, Poland, June 2001, pp.
131
-
136.

43.

T. Cibáková, E. Gramatová, W. Kuzmicz, P. Mikloš, W. Pleskacz: Defect
-
Oriented Test Pattern Generation for Circuits with Complex Gates, Proc. the of
3
rd

ECS Conference, Bratis
lava, Slovakia, September 2001, pp. 3
-
6.

44.

J. Štefanovič, P. Mikloš, E. Gramatová, M. Fischerová: Test Pattern Generation
Using a New Open Platform at the Behavioural Level, Proc. of the 3
rd

ECS
Conference, Bratislava, Slovakia, September 2001, pp. 7
-
10.

2
000


45.

E. Gramatová, J. Gašpar, T. Cibáková: Fault Simulation for Combined and
Voltage Testing of Combinational Circuits, Proc. of the 3
rd

DDECS Workshop,
Smolenice, Slovakia, April 2000, pp. 52
-
58.

46.

M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lob
ur, W. Pleskacz,
J. Raik, R. Ubar: Hierarchical Defect
-
Oriented Fault Simulation for Digital
Circuits, Informal Digest of the IEEE European Test Workshop 2000, Cascais,
Portugal, May 2000, pp. 151
-
156.

47.

M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M
. Lobur, W. Pleskacz,
J. Raik, R. Ubar: Hierarchical Defect
-
Oriented Fault Simulation for Digital
Circuits, Proc. of the IEEE European Test Workshop 2000, Cascais, Portugal,
May 2000, pp. 69
-
74.

48.

M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur
, W. Pleskacz,
J. Raik, R. Ubar: Defect
-
Oriented Fault Coverage of 100% Stuck
-
at Fault Test
Sets, Proc. of the 7th International Conference MIXDES, Szcyrk, Poland, June
2000, pp. 511
-
516.

49.

E. Gramatová, T. Cibáková, J. Gašpar, P. Mikloš: ATPG for I
DDQ

and/
or
Voltage Testing of Combinational Circuits Using an Arbitrary Fault Library for
Basic Gates, Informal Digest of the IEEE European Test Workshop, Cascais,
Portugal, May 2000, pp. 317
-
318.

50.

M. Blyzniuk, T. Cibáková, E. Gramatová, W. Kuzmicz, M. Lobur, W. P
leskacz,
J. Raik, R. Ubar: Hierarchical Defect
-
Oriented Fault Simulation for Digital
Circuits, 2
nd

VILAB USER FORUM, Smolenice, Slovakia, April 2000.

51.

E. Gramatová: Activities of Slovak Research Institutes and Universities in New
Technologies Transfer, Com
pendium of the 3
rd

VILAB USER FORUM,
Tallinn, Estonia, October 2000.

1999


52.

E. Gramatová, J. Bečková, J. Gašpar: defect Oriented TPG for Combinational
IDDQ
-

Voltage Testing for Combinational Circuits, Proc. of EDCC
-
3, Praha,
Czech Republik, 1999, pp. 5
-
6.


53.

E. Gramatová, J. Bečková, J. Gašpar: TPG for Combinard Iddq
-
Voltage Testing
of Combinational Circuits, Proc. of 2nd ECS Conference, Bratislava, Slovakia,
September 1999, pp. 29
-
32.

1998


54.

E.Gramatová, A.Somorovská, J.Gašpar, H.Manhaeve: Random and
Determ
inistic Test Pattern Generation for IDDQ
-
Voltage Testing, Proc. of 5th
Electronic Devices and Systems Conference, Brno, 1998, pp.205
-
208.

55.

E. Gramatová, A.Somorovská, J.Gašpar, H.Manhaeve: Test Pattern Generation
System for IDDQ
-
Voltage Test Experiments, P
roc. of ETW'98, Sitges, Spain,
pp. 193
-
194.

1997


56.

E. Gramatová, J. Bezáková, M. Fischerová: BX
-
TPG Algorithm at the
Behavioural Level Implemented under LEDA VHDL System, Proc. of
European Test Workshop, Cagliari, Italy, 1997, 2 p, poster.

57.

P.Gramata, E.Gr
amatová, A.Somorovská, H. Manhaeve: Built
-
In
Implementation of Pre
-
Computed Deterministic Test Set for IDDQ/Voltage
Testing, Proc. of the 1
st

Electronic Circuits and Systems Conference, Bratislava,
Slovakia, September 1997, pp. 181
-
184.

58.

J. Štefanovič, E.G
ramatová: VLSI Functional Test Generation and Genetic
Algorithms, Proc. of Artificial Intelligence and Information
-

Control Systems
of Robots, Smolenice, Slovakia, 1997, pp. 347
-
355.

1996


59.

E. Gramatová, M. Fischerová: Delay Fault Investigation at the Hig
her
-
Level,
Proc. of abstracts, of the 3
rd

BELSIGN Workshop, 1996, 2 p.

60.

M. Fischerová, E. Gramatová: Delay Fault Investigation at the Register
Transfer Level, Proc. of the Baltic Electronic Conference, Tallinn, Estonia,
1996, pp. 141
-
144.

61.

E. Gramatová, J.

Bezáková, T. Cibáková: Test Pattern Generation at the
Behavioural Level from VHDL Circuit Description Containing Several
Processes, Proc. of the Baltic Electronic Conference, Tallinn, Estonia, 1996, pp.
145
-
148.

62.

K. Kosuk, P. Gramata: BIST Structures for
Digital Circuits for IDDQ Testing,
Proc. of the UBISTA/FUTEG Workshop, Dresden, Germany, 1996, 7 p.

63.

E. Gramatová, J. Bezáková, M. Fischerová: TPG algorithm at the Behavioural
Level (BX
-
Algorithm), Proc. of the UBISTA/FUTEG Workshop, Dresden,
Germany, 1996
, 9 p.

64.

E. Gramatová, A. Somorovská: TPG Algorithm for IDDQ Testing Based on
Critical Path Tracing, Proc. of the UBISTA/FUTEG/Workshop, Dresden,
Germany, 1996, 13 p.

65.

1995


66.

E. Gramatová, T. Cibáková: Test Pattern Generation Algorithm on the
Behavioral Leve
l, 2nd FUTEG Workshop, Kaunas, Lithuania, 1995, 9 p.

67.

M. Duda, J. Bezáková, E. Gramatová: Fault Simulation Algorithm at the
Behavioral Level, 2nd FUTEG Workshop, Kaunas, Lithuania, 1995, 10 p.

68.

J. Štefanovič, E. Gramatová: RTL Level Test Generation Using G
enetic
Algorithm and Simulated Annealing, Proc. of the 2nd Workshop on
Hierarchical Test Generation, Duisburg, Germany, 1995, pp. 30.

69.

M. Duda, J. Bezáková, E. Gramatová: Fault Simulation on Behavioral Level
from VHDL Circuit Description Containing Several

Processes, Proc. of the 2nd
Workshop on Hierarchical Test Generation, Duisburg, Germany, 1995, pp. 39.

70.

E. Gramatová, T. Cibáková: Test Generation Algorithms for Digital Structures
at the Behavioral Level, Proc. of Seminar Design and Diagnostics of Electr
onic
Circuits and Systems '95, Roznov pod Radhostem, Czech Republic, 1995, pp.
29
-
38.

71.

J. Štefanovič, E. Gramatová: Genetic Algorithms in the Test Pattern Generation
for Digital Structures, Proc. of Seminar Design and Diagnostics of Electronic
Circuits and

Systems '95, Roznov pod Radhostem, Czech Republic, 1995, pp.
44
-
47.

72.

J. Štefanovič, E. Gramatová: Genetic Algorithms in the Test Generation on
Register
-
Transfer Level, Proc. of Design Methodologies for Microelectronics,
Smolenice, Slovakia, 1995, pp. 217
-
218.

1994
.

73.

E. Gramatová: Research Activities in the TPG and Fault Simulation Algorithms
at the Institute of Computer Systems, Proc. of 1st EEMCN Workshop,
Bratislava, Slovakia, 1994.

74.

P. Gramata, P. Trebatický, E. Gramatová: The MD5 Message
-
Digest Algori
thm
in the XILINX FPGA, poster, Proc. of Field
-
Programmable Logic, Prague,
Czech Republic, 1994, pp. 126
-
128.

1993


75.

A. Magdolen, J. Bezáková, E. Gramatová, M. Fischerová: REGGEN
-

Test
Pattern Generation on Register Transfer Level, Proc. of EURO
-
DAC'93 wi
th
EURO
-
VHDL'93, Hamburg, Germany, 1993, pp. 259
-
264.

1992

76.

A. Magdolen, J. Bezáková, E. Gramatová: Automatic Test Pattern Generation
on Register Transfer Level, 1st Int. Workshop on System Test and Diagnosis,
Freiburg, Germany, 1992, poster.

1990


77.

E. Gra
matová: Functional Test Pattern Generation Techniques for Complex
Digital Circuits, Proc. of Diagnostics of Microprocessor, Prague, Czech
Republic, 1990, pp.35
-
43.

1989


78.

E. Gramatová: Test Pattern Generation for VLSI Circuits, Proc. of Diagnosis,
Reliabil
ity and Alarm Management in Continuos and Discrete Systems,
Budapest, Hungary, 1989, pp.209
-
221.