Books on Low-Power Design

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Books on Low
-
Power Design




A. Chandrakasan and R. Brodersen,
Low
-
Power Digital
CMOS Design
, Boston: Kluwer Academic Publishers, 1995.



A. Chandrakasan and R. Brodersen,
Low
-
Power CMOS
Design
, New York: IEEE Press, 1998



L. Benini and G. De Micheli,
Dynamic P
ower Management
Design Techniques and CAD Tools
, Boston: Kluwer
Academic Publishers, 1998.



T. D. Burd and R. A. Brodersen,
Energy Efficient
Microprocessor Design
, Boston: Kluwer Academic
Publishers, 2002.



M. S. Elrabaa, I. S. Abu
-
Khater and M. I. Elmasry,
Advanced
Low
-
Power Digital Circuit Techniques
, Boston: Kluwer
Academic Publishers, 1997.



R. Graybill and R. Melhem,
Power Aware Computing
, New
York: Plenum Publishers, 2002.



J. B. Kuo and J.
-
H. Lou,
Low
-
Voltage CMOS VLSI Circuits
,
New York: Wiley
-
Interscie
nce, 1999.



J. Monteiro and S. Devadas,
Computer
-
Aided Design
Techniques for Low Power Sequential Logic Circuits
,
Boston: Kluwer Academic Publishers, 1997.



W. Nebel and J. Mermet,
Low Power Design in Deep
Submicron Electronics
, Boston: Kluwer Academic Publi
shers,
1997.



N. Nicolici and B. M. Al
-
Hashimi,
Power
-
Constrained Testing
of VLSI Circuits
,
Boston: Kluwer Academic Publishers,

2003.



J. M. Rabaey and M. Pedram,
Low Power Design
Methodologies
, Boston: Kluwer Academic Publishers, 1996.



K. Roy and S. C. Pras
ad,
Low
-
Power CMOS VLSI Circuit
Design
, New York: Wiley
-
Interscience, 2000.



E. Sánchez
-
Sinencio and A. G. Andreaou,
Low
-
Voltage/Low
-
Power Integrated Circuits and Systems


Low
-
Voltage
Mixed
-
Signal Circuits
, New York: IEEE Press, 1999.



W. A. Serdijn,
Low
-
Vo
ltage Low
-
Power Analog Integrated
Circuits
, Boston: Kluwer Academic Publishers, 1995.



G. K. Yeap,
Practical Low Power Digital VLSI Design
,
Boston: Kluwer Academic Publishers, 1998.

Books on BIST




P. H. Bardell, W. H. McAhhey and J. Savir,

Built
-
In Test for

VLSI, Pseudorandom Techniques
, New York: John Wiley &
Sons, 1987.



S. W. Golomb,
Shift Register Sequences
, Laguna Hills, CA:
Aegean Park Press, 1982 (Revised Edition).



P. Pal C
h
audhuri, D. Roy Chowdhury, S. Nandi and S.
Chattopadhyay,
Additive Cellular Aut
omata
, Theory and
Applications, Volume 1
,

Los Alamitos, CA: IEEE Computer
Society Press, 1997.



S. Pilarski and T. Kameda,
A Probabilistic Analysis of Test
-
Response Compaction
, Los Alamitos, CA: IEEE Computer
Society Press, 1995.



J. Rajski and J. Tyszer,
Ar
ithmetic Built
-
In Self
-
Test for
Embedded Systems
, Upper Saddle River, NJ: Prentice
-
Hall
PTR, 1998.



C. Ronse,
Feedback Shift Registers
, Berlin: Springer
-
Verlag,
1984.



C. E. Stroud,
A Designer’s Guide to Built
-
In Self
-
Test
,
Boston: Kluwer Academic Publishers
, 2002.



V. N. Yarmolik and S. N. Demidenko,
Generation and
Application of Pseudorandom Sequences for Random
Testing
, Chichester, UK: John Wiley and Sons, 1988.



V. N. Yarmolik and I. V. Kachan,
Self
-
Testing VLSI Design
,
Amsterdam: Elsevier, 1993.