CMP 1101: CHAPTER FOUR

MOS FETS
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CHAPTER FOUR: MOS FIELD EFFECT TRANSISTORS
4.1 Background
In the last chapter, we looked at a diode, a two terminal semiconductor device. We
observed that it is essentially a pn junction. It is assumed that we are now familiar with the
physics of the device

how it is able to regulate carrier and hence current flo
w through it
under different bias conditions. In many electronics applications as will become apparent
shortly, the need for three terminal semiconductor devices arises.
These devices are called
transistors
.
The name
transistor
comes from the phrase “
trans
ferring an electrical signal
across a res
istor
.”
There are two main categories: Bipolar Junction Transistors (BJTs) and
Field Effect Transistors (FETs).
In FETs, the conduction of current is controlled by application of
an electric field, hence the name. A
s such, a FET is a voltage

controlled device.
There are two
common families of FETs, the Junction FET (JFET) and the Metal Oxide Semiconductor FET
(MOS FET), which differ slightly in their physical construction.
In this c
hapter, we
introduce
the
MOS FET
.
The meaning will become apparent shortly.
The objective of this
chapter is to develop a high degree of familiarity with MOS FET physical structure,
operation, terminal characteristics, circuit models and basic circuit applications.
4.2
The MOS FET
The
meta
l
–
oxide
–
semiconductor field

effect transistor
is a device used to amplify or switch
electronic signals
.
It is by far the most common
transistor
in both
digital
and
analog
circuits
because of its easier integrality in ICs. There are two types;
NMOS FET and PMOS FET
depending on
whether the channel is of p or n type (The word ‘channel’ will make more
sense in the next sub

section). We will do most of our theory with the NMOS FET and later
realise that our results are easily adaptable to PMOS
FET
.
Silicon is the mai
n choice of
semiconductor used but
SiGe is used by some chip manufacturers.
4.2.1 Physical Construction
and Operation of the NMOS FET
The three terminals of a FET are called the
Source
,
Drain
,
and
Gate
.
The transistor is
fabricated on a p type substrate. Two heavily doped n
+
regions, the source and the drain
are created in the substrate. A thin layer of silicon dioxide (insulator) is grown on the
surface of the substrate, covering the area betw
een the source and the drain. Metal is
CMP 1101: CHAPTER FOUR

MOS FETS
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deposited on top of the oxide to from the
Gate (G)
electrode to the device, and to the
Source
(S),
the
Drain (D) and
the substrate
,
the
Body (B).
The generic name of the device should
make sense now!
We note that
the substrate forms pn junctions with the source and drain regions. In normal
operation, the source and the substrate are kept at the same potential
(normally ground)
,
so we effectively have three terminals: G, S, and D. Voltage applied to the gate control
s
current flow between the source and the drain, through a region called the
channel
of
length L and width W.
4.2.2 Operation with no Bias Voltage
Since two back to back diodes exist in series between the source and the drain; one
between the source and t
he substrate and the other between the substrate and the drain,
there is no current flow when no bias is applied
to the gate.
4.2.3 Creation of a Channel
When a
potential V
GS
is applied between the source and gate,
free holes are repelled from
the region of the substrate just below the gate, leaving a depletion region

the channel.
Reflection: What type of bound charge is
in this region?
The positive voltage at the gate attracts
free electrons from the source and drain
into the channel created. If a sufficient number of electrons accumulate in this region, we in
effect have an n region below the gate connecting the source and the drain. If
a sufficiently
positive voltage is now applied between the
source and the drain, current flows between
the two by way of electrons in the above induced n region. Now you know why it is called a
channel, because it connects the source and drain and enable
s current flow between them.
The MOSFET we are considering now is aptly called an n

channel MOSFET or simply NMOS
FET. The value of V
GS
at which a sufficient number of electrons accumulate in the channel
region to form a conducting channel is known as the
threshold voltage,
V
t.
It lies between
CMP 1101: CHAPTER FOUR

MOS FETS
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0.5 and 1 V.
The thickness of the channel is proportional to
V
GS

V
t
.
The gate and the channel
form a parallel plate capacitor with the oxide as the dielectric. This vertical electric field
controls the amount of char
ge and hence the conductivity of the channel.
4.2.4 Applying a
Small V
DS
When
a small
V
DS
is applied
(say 50mV)
, electrons travel from the source
to the drain
(names ring a bell?) hence current
i
D
flows from the drain to t
he source (opposite direction
to
electron flow). The magnitude of the current depends on the density of electrons in the
channel, which in turn depends on V
GS
. If V
GS
=V
t,
negligible current flows.
Above V
t
, the
channel behaves like a resistor, hence the i
D

V
DS
relationship is linear, with the slope of the
graph being the conductance.
The conductance of the channel and hence the current
depends on
, also known as the effective voltage.
Since an increase in V
GS
above V
t
enhances channel conductance, y
ou will sometimes find our MOSFET called an
enhancement
type NMOS FET.
Note that i
D
=i
S
so i
G
=0
.
Draw and explain the shape of the
i
D
against
V
DS
cur ves at var i ous val ues of
.
4.2.5 Increasing V
DS
at Constant V
GS
The above current

voltage
variation is valid
for small values of V
DS
such that V
GD
=V
GS

V
DS
and the induced channel is uniform. For a given
V
GS
>
V
t
, if
V
DS
is increased,
V
GD
=V
GS

V
DS
becomes smaller than
V
GS
.
As
such, the size of the channel near the source
becomes smaller compared to that near the source as shown above.
The effect is more
prominent as V
DS
is increased and the channel resistance increases. The
i
D
against
V
DS
curve bends. When V
DS
is increased to
such an extent that V
GS

V
DS
= V
t
at the drain end, the
channel depth is negligible at the drain end, and the channel is said to be
pinched off
.
Increasing V
DS
beyond this value has no effect on
i
D
and the current is said to have
saturated
.
i
D
now depends on only V
GS
.
The MOSFET is said to have entered the saturation
CMP 1101: CHAPTER FOUR

MOS FETS
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region at a value of V
DS
given by
V
DSat
=
V
GS

V
t.
The characteristic region defined by V
DS
<
V
DSat
is known
as the
ohmic/
triode region.
Example
1
Explain the operational
characteristics of the MOSFET shown below.
Solution
The MOSFET can be categorized into three separate modes when in operation.
➢
The
cut

off mode:
V
GS
< V
t
, where V
t
is the threshold voltage.
For the above
characteristic curves,
V
t
= 1V. In this mode the
device is essentially off, and in the
ideal case there is no current flowing through the device.
➢
The
ohmic
/triode
region when V
GS
> V
t
and
V
DS
< V
GS
V
t
such that a channel is formed and it is not pinched off.
T
he MOSFET
operates
as a voltage controlled
resistor in this mode
.
➢
The
Active or
Saturation
mode
which occurs
when V
GS
> V
t
and V
DS
> V
GS
V
t
and
part
of the channel is cut off
.
i
D
is independent of V
DS
.
This mode corresponds to
the region to the right of the dotted line, which is called the pinch

off voltage.
Pinch

off occurs when the MOSFET stops operating in the linear region and saturation
occurs.
Note:
In digital circuits MOSFETS are only operated i
n the linear mode, while the
saturation region is reserved for analogue circuits.
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MOS FETS
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4.2.6 The i
D

V
DS
Relationship
From the physical operation of the device above, we can derive the expression relating i
D
to
V
DS
and V
GS
.
Some parameters will be useful:
W
Channel Width
L
Channel Length
C
ox
capacitance per unit gate area of the dielectric (
silicon dioxide
)
,
where
is the
permittivity
of silicon
dioxide (3.9
) and
is
the thickness of the gate oxide.
Mobility of
electrons in the channel
=
Process transconductance parameter
In the triode region
,
[
(
)
.
Note that
if V
DS
<< V
GS
, the MOSFET acts as a linear
resistor
where the resistor, r
DS
(
)
.
In the saturation region, we substitute V
DS
with
V
GS

V
t
in the expression above yielding
(
)
2
The ratio
is known as the aspect ratio of the MOSFET.
How would you write the above equations if K was defined as
?
As can be seen from the physical structure of the device, the MOSFET is a symmetric device,
thus the source an
d the gate can be interchanged without any change in device properties.
For most applications though, the source is connected to the body, yiel
ding a three terminal
element and the terminals are then no longer interchangeable. The circuit symbol for
NMOS
is shown below, first with the body and then without. By convention, i
D
flows into
the gate.
CMP 1101: CHAPTER FOUR

MOS FETS
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Rather than indicating the direction of current flow, the arrow actually shows
the direction
of the underlying pn junction, inwards for p and outwards for n type.
Example
2
For a MOSFET with
.
,
450
and V
t
=
0.7 V,
a)
Find
and
(
4.32 x 10

3
F/m
2
, 194
A/V
2
)
b)
For a MOSFET with
find the values of V
GS
and V
DS
needed to operate the
transistor in saturation with
i
D
= 100
.
(
1.02V, 0.32 V
)
4.3
Solving NMOS Circuits
To solve the circuits,
we assume that
NMOS is in a particular state, use NMOS model for
that state to solve the
circuit and check the validity of our assumption by checking the
inequalities in the model for that state. A formal procedure is:
i.
Write down a KVL including GS terminals (call it GS

KVL).
ii.
Write down a KVL including DS terminals (call it DS

KVL).
iii.
From GS

KVL, compute
V
GS
(using
i
G
= 0)
a)
If
V
GS
< V
t
, NMOS is in cut

off. Let
i
D
= 0, solve for
V
DS
from DS

KVL. We are done.
b)
If
V
GS
> V
t
, NMOS is not in cut

off. Go to step 4.
iv.
Assume NMOS is in active region. Compute
i
D
from
(
)
2
,
t
hen, use
DS

KVL to compute
V
DS
. If
V
DS
> V
GS

V
t
, we are done. Otherwise go to step 5.
v.
NMOS has to be in ohmic region. Substitute for
i
D
from
[
(
)
in DS

KVL. You will get a quadratic equation in
V
DS
. Find
V
DS
(one of the two
roots of the equation will be unphysical). Check to make sure that
V
DS
< V
GS

V
t
.
Substitute
V
DS
in DS

KVL to find
i
D
.
CMP 1101: CHAPTER FOUR

MOS FETS
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Example 3
For the NMOS circuit shown, with K= 0.25 mA/V
2
and V
t
=2V, find V
o
when V
i
=0, 6, and
V
DD
=
12V.
Solution
GS KVL
:
V
GS
=V
i
DS KVL:
Case 1
When V
i
=0
,
GS KVL
:
V
GS
=
0, Hence
GS KVL
:
V
G
s
< V
t
, NMOS are in cut

off. I
D
=0.
DS KVL,
=12V
Case 2
When
V
i
=6 V, GS
KVL
:
V
GS
=
6V which is greater than V
t
. The NMOS is not in cut

off.
Let us assume the transistor to be in the active region:
(
)
2
.
(
)
2
= 4mA.
DS KVL:
=
(
)
Since V
DS
> V
GS

V
t
,
the transistor is indeed in the active region and I
D
= 4mA and V
o
=V
DS
=
8 V.
S
G
V
i
V
o
I
D
CMP 1101: CHAPTER FOUR

MOS FETS
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Case 3
When
V
i
=12 V, GS
KVL
:
V
GS
=
12V which is greater than V
t
. The NMOS is not in cut

off.
Let us assume the transistor to be in the active region:
(
)
2
.
(
)
2
= 25mA.
DS KVL:
=
(
)
Since V
DS
< V
GS

V
t
,
the transistor is
not in the
active region
. Assume the transistor is in the
linear
region.
[
(
)
= 0.25 X 10

3
[
(
)
Substituting I
D
in
DS

KVL
, we get 12=
10
3
X 0.25 X 10

3
[
(
)
+
+48 =0. Solving these two equations yields
.
and
.
.
The second root is unphysical so
.
. Since 2.2 <
=10V, the
transistor is truly in the linear region.
From DS

KVL,
=
=
.
.
.
Note that
what we have discussed above yields the large signal
MOS FET model. In
saturation, observe that
the MOSFET provides a drain current whose value is independent
of the drain voltage. Thus, the MOSFET behaves as an ideal current source represented by
the model below:
CMP 1101: CHAPTER FOUR

MOS FETS
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4.4 Finite Output Resistance in
Saturation
We assumed above that in saturation, i
D
is independent of V
DS
.
H
owever, it is realised that
as V
DS
is increased further, the pinch off point moves slightly away from the drain, towards
the source. The channel length is in effect reduced, a phenomenon known as
channel length
modulation.
It can be shown that our equation for saturation current changes to
(
)
2
(
)
,
is a parameter for a given MOSFET design. The
characteristic curves now change shape:
From the equation, what is V
DS
when i
DS
=0?
When the curves are extrapolated, they cut the V
DS
axis at a common voltage,

V
A
,
known as
Early Voltage.
We get the finite output resistance in saturation by getting the inverse of the
derivative if i
D
wrt V
DS
. We end up with
[
(
)
]
which can be written as
or simply
where I
D
is the drain current without channel length modulation. The
output resistance is hence inversely proportional to the drain current ands the large signal
equivalent model is modified to become:
CMP 1101: CHAPTER FOUR

MOS FETS
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4.4
The
P Channel Enhancement Type MOSFET
The physical structure is similar to that of NMOS except that the semiconductor type for the
substrate, the source and the channel are interchanged. (The body is now n type while the
source and the drain are of p type). A p type channel results. All the vo
ltages are now
reversed. By convention, drain current flows out of the drain and into the source. Below
are the circuit symbols, first with the body and then the simplified version when the source
is connected to the body.
What are the advantages of N
MOS over PMOS?
The following operation characteristics apply:
Cut off:
V
GS
> V
t
for any V
DS
.
Ohmic/Linear region
:
V
GS
<
V
t
and V
DS
> V
GS

V
t
,
[
(
)
Active/Saturation:
V
GS
<
V
t
and V
DS
< V
GS

V
t
,
(
)
2
Note that the above equations are obtained by multiplying the corresponding NMOS
expressions by a negative sign. V
t
is also negative.
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