2012 IC Design Contest

dehisceforkΗλεκτρονική - Συσκευές

2 Νοε 2013 (πριν από 3 χρόνια και 9 μήνες)

248 εμφανίσεις

V
er.1.0

1


20
1
2

IC Design Contest

Analog Circuit Category

Switched
-
Capacitor
Voltage D
oubler


I.

General
D
escriptions
:


In this contest, the design
is
a

switched
-
capacitor
voltage doubler

(
SCVD
)

,

which
accomplish
es

energy transfer and voltage conversion using

capacitors
.

The switched
-

capacitor voltage converters
include

the
voltage inverter

and the
voltage doubler
circuit
.

In the voltage inverter, the

charge pump capacitor, C
D
, is charged to
the input voltage
during the first half of

the switching cycle. During the second half of the switching cycle,
its voltage is

inverted and applied to capacitor C
O

and the load

R
L
. The switching
frequency impacts the size of the external

capacitors required
, and higher switching
frequencies allow the use of smaller

capacitors. The duty cycle
,

defined as the ratio of
charging time for C
D

to the entire

switching cycle time
,

is usually 50%

for
yield
ing

the
optimal

charge transfer efficiency.

The detail circuits

are shown in Fig
-
1

to Fig
-
5

respectively.



Fig
-
1
:

Switched
-
capacitor
voltage doubler




V
er.1.0

2



Fig
-
2:

Charge pump circuit



Fig
-
3
:

Driver circuit



Fig
-
4
:

Voltage translator circuit


V
er.1.0

3



Fig
-
5
:

Non
-
overlap clock generator


II. Design Specifications:

1.

Please use
CIC

0.18um 1.8V 1P6M CMOS
virtual
process to design
the whole circuit
.

The
final results should include the netlist, layout and all
the
verification files
(DRC and LVS

reports
)
.

2.

Please be noted: Use 3.3
-
V devices for all designs.
Anyone
wh
o

violates this requirement
will be disqualified during

the

grading.

3.

Supply voltage
(V
DD
)
is

1.8V

and n
o n
egative bias source is allowed

in your design.

4.

Input clock signa
l is
50K
Hz

with
50% duty cycle and 1.8V peak voltage

(
please

refer to the
test bench)
.

5.

Charge pump capacitor

C
D

is 1.0uF, o
utput
capacitor
C
O

is
2
.
2u
F and
loading
R
L

is

200Ω
.

6.

Beside the above requirements,
the
post
-
layout
simulation
(
for speeding up the simulation
time,
only do the
C
+C
C

extraction
)
results of this
SCVD

circuit

should
also
meet
the
following
acceptance
specifications under the

typical transistor

parameters

(TT corner)
:



Stable output voltage: larger than 3.0V after
500u
s



Area
:
smaller

than

6
0
,
0
00
um
2

(
including ALL transistors
.

C
D
,

C
O

and
R
L

are external
components)



Efficiency

(defined in the testbench)
:
larger

than

85%


III
. Scoring:

1.

Accept
ance

criteria: Finish layout without any DRC/LVS
error and

the post
-
layout
simulation results of
your

design meet

all specifications

described in
s
ection II

item
6
.

2.

Ranking

method:
S
atisfy
ing

the
acceptance criteria is the basic requirement.
T
he ranking
is base
d on the efficiency
.
Higher

efficiency
means the better ranking.

3.

Please be noted:

I
f any
of the acceptance criteria is
not
satisfied
, the
ranking will be
affected even if his/her
efficiency

is
higher

than other teams who satisfy all

the

specifications but with

lower

efficiency
.

4.

The principle of scoring
is based on
the

complete design

in

the

contest.
However, e
ven
though

your

design cannot be finished in time, CIC allows the designers to upload their
V
er.1.0

4


results

before the deadline of the contest. If the number of teams with

complete design


is less

than the number of awards, the
i
nco
mplete

designs
might

be granted
.

I
V
. The following rules should be followed

EDA Tools:

1.

Simulation: HSPICE

20
10
.
12
-
SP2

2.

Layout: Virtuoso
IC5141
or Laker

L3

3.

Verification: Calibre
20
10
.
4
_
2
6.
16

for

DRC, LVS and PEX.


Other
s:

1.

CIC will provide the unified test

bench
to

consist

the

scoring
criteria
.

2.

Netlist file naming: the subckt name of
the netlist

file
should be


scdb
.sp
i

, the top cell
sho
u
ld be named as “
scdb
”,
an
d outp
ut node
is

V
o
ut
.
Vin
is a 1.8
-
Volt DC input
.
Supply
power is “V
dd
” and ground is “
Vss
”.
P
lease be noted that the
t
otal
seven

nodes
of

scdb


should
be the same as

the
following

naming sequence.
It is important to follow the port order
in your design
files;

otherwise it may affect your ranking.


.subckt

scdb

V
dd
Vss

V
in CLK
Vx Vy
V
out

MM1 net1 net2 Vdd Vdd

P
_
33

L=x W=y

…..

…..

.ends

3.

GDSII
file is named as “
scdb
.gds” and the top

cell name is
scdb

4.

It

s n
o
t

necessary to do the antenna check when doing the DRC but other items should be
clean expect the metal density error

5.

Calibre LVS result is named as
scdb
.lvs.report

6.

Please tar th
e

scdb
.sp
i


and


scdb
.gds

,
name
this tar file
as

grad_analog.tar


and

put

it

to
the
specific directory

which will be listed in
the
other document
.


V
.
Testbench


*2012 IC contest
--
charge pump

*Testbench file


.LIB 'cic018.l' TT

.INC 'scdb.spi'


**************************************************

*CORE

**************************************************

Xscdb Vdd Vss Vin
CLK
Vx Vy
Vout
scdb

**************************************************

*EXTERNAL CAPACITOR & LOAD

**************************************************

V
er.1.0

5


CD Vx Vy 1U

CO Vout Vss 2.2U

RL Vout Vss 200

**************************************************

*BIAS & INPUT

**************************************************

VDD Vdd Vss V_SUPPLY

VSS Vss GND V_GROUND

VIN Vin Vss V_INPUT

VCLK CLK Vss PUL(0 1.8 0
1U 1U
10
U
20
U)

********
******************************************

*PARAMETER

**************************************************

.PARAM V_SUPPLY = 1.8V

.PARAM V_GROUND = 0.0V

.PARAM V_INPUT = 1.8V

**************************************************

*ANALYSIS

**************************************************

.MEASURE TRAN VDD_AVG AVG V(Vdd) FROM=
500u

TO=
1
m

.MEASURE TRAN IDD_AVG AVG I(Vdd)
FROM=
500u

TO=
1
m

.MEASURE TRAN VIN_AVG AVG V(Vin)
FROM=
500u

TO=
1
m

.MEASURE TRAN IIN_AVG AVG I(Vin)
FROM=
500u

TO=
1
m

.MEASURE TRAN VOUT_AVG AVG V(Vout)
FROM=
500u

TO=
1
m

.MEASURE TRAN IO_AVG AVG I(RL)
FROM=
500u

TO=
1
m

.MEASURE AVGVDDP PARAM='ABS(VDD_AVG*IDD_AVG)'

.MEASURE AVGVINP PARAM='ABS(VIN_AVG*IIN_AVG)'

.MEASURE AVGVOUTP PARAM='ABS(VOUT_AVG*IO_AVG)'

.MEAS
URE EFF PARAM='AVGVOUTP/(AVGVDDP+AVGVINP)'


.OP

.OPTION POST

.OPTION PROBE

.TRAN 0.
1U

1
M

.PROBE TRAN V(Vout) I(RL)

.END



V
er.1.0

6


軟體環境

使用者登入後自動會設定好以下軟體環境


Vendor

Tool

Executable

Cadence

Virtuoso

icfb

Composer

icfb

NC
-
Verilog

ncverilog

SOC Encounter

encounter

Synopsys

design vision

dv, dc_shell

VCS

vcs

IC compiler

icc_shell
-
gui

Hspice

hspice

Cosmos Scope

scope

Spice e
xplorer

sx

w

, wv

Mentor

Calibre

calib
re

ModelSim

vsim

Spring Soft

Laker

laker

Verdi

v
erdi
,

nWave
, nLint

Utility

vi

vi, vim, gvim

gedit

gedit

nedit

nedit

pdf reader

acroread

calculate

gnome
-
calculator, bc
-
l

gcc

gcc


EDA
軟體所須使用的
license
皆已
設定完成,不須額外設定,且每

限定
每個軟體
只能使用一套
license





V
er.1.0

7


Full Custom Related F
iles

Files location:
/usr/cad/icc20
12
/
V
P
/


CIC
-
CIS
-

2005
-
TR01_VP1.pdf

Process Layout Rule

CIC
-
CIS
-

2005
-
TR01_VP2.pdf

Process Electrical Design Rule

CIC
-
CIS
-

2005
-
TR01_VP3.pdf

Process Device Formation

cpall.csh

c shell copy all files to home

c
alibre/



.cdsinit

virtuoso initial file for calibre


Calibre_DRC
/



rule.drc

Calibre DRC rule file


Calibre_LVS
/



Rule.lvs

Calibre LVS rule file


Calibre_PEX
/




Rule.rce

Calibre LPE rule file



Rule_08KA.rc

Calibre LPE
rule file



Rule_20KA.rc

Calibre LPE rule file

model
/



cic018.l

SPICE model

l
aker/



laker.tf

Laker technology file

virtuoso
/



cic18.tf

Virtuoso technology file


display.drf

Virtuoso display file

PNP/



PNP_V50X50.gds

BJT Example layout


PND_V100X100.gds

BJT Example layout


若需在
virtuoso
中呼叫
calibre
,請將
calibre/.cdsinit
複製到自己的
home directory


若不知道如何複製檔案,可執行

/usr/cad/icc2012/VP/cpall.csh
,這個
csh
檔會將所
有製程資料複製到您的
home
目錄。