VLSI Design II VLSI Design II VLSI Design II VLSI Design II

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26 Νοε 2013 (πριν από 3 χρόνια και 9 μήνες)

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MicroLab, VLSI-15 (1/36)
JMM v1.4
VLSI Design II
VLSI Design IIVLSI Design II
VLSI Design II
CMOS Layout
CMOS LayoutCMOS Layout
CMOS Layout
Measure twice,
Measure twice,Measure twice,
Measure twice,fab
fabfab
fab once
onceonce
once
Overview
OverviewOverview
Overview

CMOS Layout and Design Rules
CMOS Layout and Design RulesCMOS Layout and Design Rules
CMOS Layout and Design Rules

Analog Layout Design Considerations
Analog Layout Design ConsiderationsAnalog Layout Design Considerations
Analog Layout Design Considerations
Goal:
Goal: Goal:
Goal: You are familiar with the basic layout design
You are familiar with the basic layout design You are familiar with the basic layout design
You are familiar with the basic layout design
rules of the
rules of therules of the
rules of the Alcatel
AlcatelAlcatel
Alcatel 0.5
0.50.5
0.5
µ
µµ
µ
m CMOS process. You
m CMOS process. You m CMOS process. You
m CMOS process. You
know how to layout integrated transistors,
know how to layout integrated transistors, know how to layout integrated transistors,
know how to layout integrated transistors,
capacitors and resistors, and what has to be
capacitors and resistors, and what has to be capacitors and resistors, and what has to be
capacitors and resistors, and what has to be
considered in order to realize quality analog
considered in order to realize quality analog considered in order to realize quality analog
considered in order to realize quality analog
circuits, like matching and shielding.
circuits, like matching and shielding.circuits, like matching and shielding.
circuits, like matching and shielding.
MicroLab, VLSI-15 (2/36)
JMM v1.4
Sources of Error
Sources of ErrorSources of Error
Sources of Error

Line registration errors
Line registration errorsLine registration errors
Line registration errors
resist exposure and development
resist exposure and developmentresist exposure and development
resist exposure and development
over/under etching, lateral diffusion
over/under etching, lateral diffusionover/under etching, lateral diffusion
over/under etching, lateral diffusion
uneven topography
uneven topographyuneven topography
uneven topography

systematic errors corrected by bloating/
systematic errors corrected by bloating/systematic errors corrected by bloating/
systematic errors corrected by bloating/
shrinking mask
shrinking maskshrinking mask
shrinking mask

random errors increase minimum widths
random errors increase minimum widthsrandom errors increase minimum widths
random errors increase minimum widths
and spacing
and spacingand spacing
and spacing

Mask misalignment
Mask misalignmentMask misalignment
Mask misalignment

random errors increase extensions and
random errors increase extensions andrandom errors increase extensions and
random errors increase extensions and
surrounds
surroundssurrounds
surrounds

Other
OtherOther
Other fab
fabfab
fab difficulties
difficultiesdifficulties
difficulties

contacts and
contacts andcontacts and
contacts and vias
viasvias
vias only on “flat” surfaces
only on “flat” surfacesonly on “flat” surfaces
only on “flat” surfaces

no devices near boundaries of well
no devices near boundaries of well no devices near boundaries of well
no devices near boundaries of well

no poly contacts over diffusion
no poly contacts over diffusionno poly contacts over diffusion
no poly contacts over diffusion

“gate” metal must connect to diffusion
“gate” metal must connect to diffusion“gate” metal must connect to diffusion
“gate” metal must connect to diffusion

minimum metal coverage requirements
minimum metal coverage requirements minimum metal coverage requirements
minimum metal coverage requirements

Electrical properties
Electrical propertiesElectrical properties
Electrical properties

current density limitations
current density limitationscurrent density limitations
current density limitations

latch
latchlatch
latch-
--
-up prevention
up prevention up prevention
up prevention

Process instabilities
Process instabilitiesProcess instabilities
Process instabilities
mobility variations (why?)
mobility variations (why?)mobility variations (why?)
mobility variations (why?)
thin
thinthin
thin-
--
-oxide thickness variations
oxide thickness variationsoxide thickness variations
oxide thickness variations
sheet resistances
sheet resistancessheet resistances
sheet resistances

use of “process corners” in analysis
use of “process corners” in analysis use of “process corners” in analysis
use of “process corners” in analysis
MicroLab, VLSI-15 (3/36)
JMM v1.4
Design vs. Actual IC
Design vs. Actual ICDesign vs. Actual IC
Design vs. Actual IC
MicroLab, VLSI-15 (4/36)
JMM v1.4
Line Registration Errors
Line Registration ErrorsLine Registration Errors
Line Registration Errors
MicroLab, VLSI-15 (5/36)
JMM v1.4
Mask Alignment Errors (I)
Mask Alignment Errors (I)Mask Alignment Errors (I)
Mask Alignment Errors (I)
MicroLab, VLSI-15 (6/36)
JMM v1.4
Mask Alignment Errors (II)
Mask Alignment Errors (II)Mask Alignment Errors (II)
Mask Alignment Errors (II)
Maly
MalyMaly
Maly,
,,
,Figure
FigureFigure
Figure 2
22
2-
--
-9
99
9
MicroLab, VLSI-15 (7/36)
JMM v1.4
Design Rules
Design RulesDesign Rules
Design Rules
extension rules
extension rulesextension rules
extension rules
(overlapping)
(overlapping)(overlapping)
(overlapping)
width rules
width ruleswidth rules
width rules
Exclusion rule
Exclusion ruleExclusion rule
Exclusion rule
enclosure rules
enclosure rulesenclosure rules
enclosure rules
spacing rules
spacing rulesspacing rules
spacing rules

We can specify the design rules using some convenient
We can specify the design rules using some convenient We can specify the design rules using some convenient
We can specify the design rules using some convenient
units, e.g., microns but what happens if we want to
units, e.g., microns but what happens if we want to units, e.g., microns but what happens if we want to
units, e.g., microns but what happens if we want to
manufacture the chip using different manufacturers?
manufacture the chip using different manufacturers?manufacture the chip using different manufacturers?
manufacture the chip using different manufacturers?

One suggestion: use an abstract unit, the
One suggestion: use an abstract unit, the One suggestion: use an abstract unit, the
One suggestion: use an abstract unit, the lambda,
lambda, lambda,
lambda, and scale
and scale and scale
and scale
the design to the appropriate actual dimensions when the
the design to the appropriate actual dimensions when the the design to the appropriate actual dimensions when the
the design to the appropriate actual dimensions when the
chip is to be manufactured.
chip is to be manufactured. chip is to be manufactured.
chip is to be manufactured.

Usually all edges must be “on grid”, e.g., in the MOSIS
Usually all edges must be “on grid”, e.g., in the MOSIS Usually all edges must be “on grid”, e.g., in the MOSIS
Usually all edges must be “on grid”, e.g., in the MOSIS
scalable rules, all edges must be on a half lambda grid, on
scalable rules, all edges must be on a half lambda grid, on scalable rules, all edges must be on a half lambda grid, on
scalable rules, all edges must be on a half lambda grid, on
the 0.5
the 0.5the 0.5
the 0.5
µ
µµ
µ
m
mm
m Alcatel
AlcatelAlcatel
Alcatel all edges must be on 0.05
all edges must be on 0.05all edges must be on 0.05
all edges must be on 0.05
µ
µµ
µ
m grid.
m grid.m grid.
m grid.
MicroLab, VLSI-15 (8/36)
JMM v1.4
Lambda
LambdaLambda
Lambda-
--
-based Rules
based Rulesbased Rules
based Rules
For 0.5
For 0.5For 0.5
For 0.5
µ
µµ
µ
m
mm
mAlcatel
AlcatelAlcatel
Alcatelprocess:
process: process:
process:
λ
λλ
λ
= 0.25
= 0.25= 0.25
= 0.25
µ
µµ
µ
m
mm
m
1
11
1
λ
λλ
λ
2
22
2
λ
λλ
λ
3
33
3
λ
λλ
λ
3
33
3
λ
λλ
λ
1
11
1
λ
λλ
λ
2
22
2
λ
λλ
λ
2
22
2
λ
λλ
λ
6
66
6
λ
λλ
λ
3
33
3
λ
λλ
λ
x3
x3x3
x3
λ
λλ
λ
3
33
3
λ
λλ
λ
4
44
4
λ
λλ
λ
poly
polypoly
poly
metal1
metal1metal1
metal1
diffusion (active)
diffusion (active)diffusion (active)
diffusion (active)
contact
contactcontact
contact
2
22
2
λ
λλ
λ
1
11
1
λ
λλ
λ
5
55
5
λ
λλ
λ
4
44
4
λ
λλ
λ
One lambda (
One lambda (One lambda (
One lambda (
λ
λλ
λ
)= one half of the “minimum” mask
)= one half of the “minimum” mask )= one half of the “minimum” mask
)= one half of the “minimum” mask
dimension, typically the length of a transistor channel.
dimension, typically the length of a transistor channel.dimension, typically the length of a transistor channel.
dimension, typically the length of a transistor channel.
Under the assumption that the worst case alignment is
Under the assumption that the worst case alignment is Under the assumption that the worst case alignment is
Under the assumption that the worst case alignment is
better than 0.75
better than 0.75better than 0.75
better than 0.75
λ
λλ
λ
, the maximum relative misalignment
, the maximum relative misalignment , the maximum relative misalignment
, the maximum relative misalignment
between any two masks is better than 1.5
between any two masks is better than 1.5between any two masks is better than 1.5
between any two masks is better than 1.5
λ
λλ
λ
. This can be
. This can be . This can be
. This can be
used to derive design rules and to estimate minimum
used to derive design rules and to estimate minimum used to derive design rules and to estimate minimum
used to derive design rules and to estimate minimum
dimensions of a junction area and perimeter before a
dimensions of a junction area and perimeter before a dimensions of a junction area and perimeter before a
dimensions of a junction area and perimeter before a
transistor has to be laid out.
transistor has to be laid out.transistor has to be laid out.
transistor has to be laid out.
MicroLab, VLSI-15 (9/36)
JMM v1.4
Lambda vs. Micron Rules
Lambda vs. Micron RulesLambda vs. Micron Rules
Lambda vs. Micron Rules
Lambda
LambdaLambda
Lambda-
--
-based design rules are based on the assumption
based design rules are based on the assumption based design rules are based on the assumption
based design rules are based on the assumption
that one can scale a design to the appropriate size before
that one can scale a design to the appropriate size before that one can scale a design to the appropriate size before
that one can scale a design to the appropriate size before
manufacture. The assumption is that
manufacture. The assumption is thatmanufacture. The assumption is that
manufacture. The assumption is that all manufacturing
all manufacturing all manufacturing
all manufacturing
dimensions scale equally
dimensions scale equallydimensions scale equally
dimensions scale equally, an assumption that “works” only
, an assumption that “works” only , an assumption that “works” only
, an assumption that “works” only
over some modest span of time. For example: if a design
over some modest span of time. For example: if a design over some modest span of time. For example: if a design
over some modest span of time. For example: if a design
is completed with a poly width of 2
is completed with a poly width of 2is completed with a poly width of 2
is completed with a poly width of 2
λ
λ λ
λ
and a metal width of
and a metal width of and a metal width of
and a metal width of
3
33
3
λ
λ λ
λ
then minimum width metal wires will always be 50%
then minimum width metal wires will always be 50% then minimum width metal wires will always be 50%
then minimum width metal wires will always be 50%
wider than minimum width of poly wires.
wider than minimum width of poly wires.wider than minimum width of poly wires.
wider than minimum width of poly wires.
Consider the following data from
Consider the following data fromConsider the following data from
Consider the following data from Alcatel
AlcatelAlcatel
Alcatel 0.5
0.50.5
0.5
µ
µµ
µ
m process
m process m process
m process
(compare with
(compare with(compare with
(compare with Weste
WesteWeste
Weste, Table 3.2 pp145):
, Table 3.2 pp145):, Table 3.2 pp145):
, Table 3.2 pp145):
contacted metal pitch
contacted metal pitchcontacted metal pitch
contacted metal pitch
1/2 * contact size
1/2 * contact size1/2 * contact size
1/2 * contact size
contact surround
contact surroundcontact surround
contact surround
metal
metalmetal
metal-
--
-to
toto
to-
--
-metal spacing
metal spacingmetal spacing
metal spacing
contact surround
contact surroundcontact surround
contact surround
1/2 * contact size
1/2 * contact size1/2 * contact size
1/2 * contact size
lambda
lambdalambda
lambda
rule
rulerule
rule
1.5
1.51.5
1.5
λ
λλ
λ
1
11
1
λ
λλ
λ
4
44
4
λ
λλ
λ
1
11
1
λ
λλ
λ
1.5
1.51.5
1.5
λ
λλ
λ
9
99
9
λ
λλ
λ
lambda
lambdalambda
lambda
= 0.25u
= 0.25u= 0.25u
= 0.25u
0.375
0.3750.375
0.375
µ
µµ
µ
0.25
0.250.25
0.25
µ
µµ
µ
1.0
1.01.0
1.0
µ
µµ
µ
0.25
0.250.25
0.25
µ
µµ
µ
0.375
0.3750.375
0.375
µ
µµ
µ
2.25
2.252.25
2.25
µ
µµ
µ
micron
micronmicron
micron
rule
rulerule
rule
0.3
0.30.3
0.3
µ
µµ
µ
0.25
0.250.25
0.25
µ
µµ
µ
0.8
0.80.8
0.8
µ
µµ
µ
0.25
0.250.25
0.25
µ
µµ
µ
0.3
0.30.3
0.3
µ
µµ
µ
1.9
1.91.9
1.9
µ
µµ
µ
Scaled design is legal
Scaled design is legalScaled design is legal
Scaled design is legal
but much larger than
but much larger thanbut much larger than
but much larger than
it needs to be!
it needs to be!it needs to be!
it needs to be!
+40% in area
+40% in area+40% in area
+40% in area
MicroLab, VLSI-15 (10/36)
JMM v1.4
Retargetable
RetargetableRetargetable
RetargetableLayouts?
Layouts?Layouts?
Layouts?
So, should one use lambda rules, or not?
So, should one use lambda rules, or not?So, should one use lambda rules, or not?
So, should one use lambda rules, or not?

probably okay for retargeting between “similar”
probably okay for retargeting between “similar” probably okay for retargeting between “similar”
probably okay for retargeting between “similar”
processes, e.g., when later process is a simple
processes, e.g., when later process is a simple processes, e.g., when later process is a simple
processes, e.g., when later process is a simple
“shrink” of the earlier process. This often happens
“shrink” of the earlier process. This often happens “shrink” of the earlier process. This often happens
“shrink” of the earlier process. This often happens
between generations as a mid
between generations as a midbetween generations as a mid
between generations as a mid-
--
-life kicker for a
life kicker for a life kicker for a
life kicker for a
process. Some 0.35
process. Some 0.35process. Some 0.35
process. Some 0.35
µ
µµ
µ
m processes are shrinks of
m processes are shrinks of m processes are shrinks of
m processes are shrinks of
an earlier 0.5
an earlier 0.5an earlier 0.5
an earlier 0.5
µ
µµ
µ
m process. Can be useful for
m process. Can be useful for m process. Can be useful for
m process. Can be useful for

““
“fabless
fablessfabless
fabless” semiconductor companies.
” semiconductor companies.” semiconductor companies.
” semiconductor companies.

most industrial designs use micron rules to get the
most industrial designs use micron rules to get the most industrial designs use micron rules to get the
most industrial designs use micron rules to get the
extra space efficiency. Cost of retargeting by hand
extra space efficiency. Cost of retargeting by hand extra space efficiency. Cost of retargeting by hand
extra space efficiency. Cost of retargeting by hand
is acceptable for a successful product, but usually
is acceptable for a successful product, but usually is acceptable for a successful product, but usually
is acceptable for a successful product, but usually
it’s time for a redesign anyway.
it’s time for a redesign anyway.it’s time for a redesign anyway.
it’s time for a redesign anyway.

invent some way of entering a design symbolically
invent some way of entering a design symbolically invent some way of entering a design symbolically
invent some way of entering a design symbolically
but use a more sophisticated technique for
but use a more sophisticated technique for but use a more sophisticated technique for
but use a more sophisticated technique for
producing the masks for a particular process.
producing the masks for a particular process. producing the masks for a particular process.
producing the masks for a particular process.
Insight:
Insight: Insight:
Insight: relative sizes may change but topological
relative sizes may change but topological relative sizes may change but topological
relative sizes may change but topological
relationship between components does not
relationship between components does notrelationship between components does not
relationship between components does not. So,
. So, . So,
. So,
instead of shrinking a design,
instead of shrinking a design, instead of shrinking a design,
instead of shrinking a design, compact
compactcompact
compactit!
it! it!
it!
MicroLab, VLSI-15 (11/36)
JMM v1.4
0.5
0.50.5
0.5
µ
µµ
µ
m CMOS
m CMOSm CMOS
m CMOSAlcatel Mietec
Alcatel MietecAlcatel Mietec
Alcatel MietecProcess
ProcessProcess
Process
Layers and mask definition: C05M
Layers and mask definition: C05MLayers and mask definition: C05M
Layers and mask definition: C05M-
--
-D
DD
D
layer name
layer namelayer name
layer name drawn
drawndrawn
drawn mask name
mask namemask name
mask name
active
activeactive
active yes
yesyes
yes active
activeactive
active
nwell
nwellnwell
nwell yes
yesyes
yes n
nn
n-
--
-well
wellwell
well
pwell
pwellpwell
pwell no
nono
no (p
(p(p
(p-
--
-well)
well)well)
well)
poly
polypoly
poly yes
yesyes
yes poly
polypoly
poly
nplus
nplusnplus
nplus no
nono
no (n
(n(n
(n
+
++
+
implant)
implant)implant)
implant)
pplus
ppluspplus
pplus yes
yesyes
yes p
pp
p
+
++
+
implant
implantimplant
implant
contact
contactcontact
contact yes
yesyes
yes contact
contactcontact
contact
metal_1
metal_1metal_1
metal_1 yes
yesyes
yes metal 1
metal 1metal 1
metal 1
via_1
via_1via_1
via_1 yes
yesyes
yes via 1
via 1via 1
via 1
metal_2
metal_2metal_2
metal_2 yes
yesyes
yes metal 2
metal 2metal 2
metal 2
via_2
via_2via_2
via_2 yes
yesyes
yes via 2
via 2via 2
via 2
metal_3
metal_3metal_3
metal_3 yes
yesyes
yes metal 3
metal 3metal 3
metal 3
nitride
nitridenitride
nitride yes
yesyes
yes nitride
nitridenitride
nitride
dractext
dractextdractext
dractext yes
yesyes
yes -
--
-
nldd
nlddnldd
nldd no
no no
no (no low doped drain,
(no low doped drain,(no low doped drain,
(no low doped drain,Zener
ZenerZener
Zener)
))
)
nlddprot
nlddprotnlddprot
nlddprot yes
yesyes
yes -
--
-
nplusprot
nplusprotnplusprot
nplusprot yes
yesyes
yes -
--
-
MicroLab, VLSI-15 (12/36)
JMM v1.4
nwell
nwellnwell
nwell
C05M
C05MC05M
C05M-
--
-D: some logical descriptions
D: some logical descriptionsD: some logical descriptions
D: some logical descriptions
logical name
logical namelogical name
logical name used masks
used masksused masks
used masks
nwell
nwellnwell
nwell =
==
= nwell
nwellnwell
nwell
pwell
pwellpwell
pwell =
==
= nwell
nwellnwell
nwell
n
nn
n
+
++
+
diffusion
diffusiondiffusion
diffusion =
==
= active and
active and active and
active and pplus
ppluspplus
pplus and poly
and polyand poly
and poly
p
pp
p
+
++
+
diffusion
diffusiondiffusion
diffusion =
==
= active and
active and active and
active and pplus
ppluspplus
pplus and poly
and polyand poly
and poly
n
nn
n
+
++
+
source/drain
source/drainsource/drain
source/drain =
==
= active and
active and active and
active and pplus
ppluspplus
pplus and poly and
and poly and and poly and
and poly and nwell
nwellnwell
nwell
p
pp
p
+
++
+
source/drain
source/drainsource/drain
source/drain =
==
= active and
active and active and
active and pplus
ppluspplus
pplus and poly and
and poly and and poly and
and poly and nwell
nwellnwell
nwell
gate
gategate
gate =
==
= active and poly
active and polyactive and poly
active and poly
locical
locicallocical
locical masks
masksmasks
masks
n
nn
n
+
++
+
diffusion
diffusiondiffusion
diffusion
p
pp
p
+
++
+
diffusion
diffusiondiffusion
diffusion
poly
polypoly
poly
nwell
nwellnwell
nwell
active
activeactive
active
pplus
ppluspplus
pplus
pfet
pfetpfet
pfet
nfet
nfetnfet
nfet
MicroLab, VLSI-15 (13/36)
JMM v1.4
Layout Rules (C05M
Layout Rules (C05MLayout Rules (C05M
Layout Rules (C05M-
--
-D) #1
D) #1D) #1
D) #1

n
nn
n-
--
-well, active
well, activewell, active
well, active
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
2.4
2.42.4
2.4
µ
µµ
µ
m
mm
m
2
22
2
µ
µµ
µ
m (3
m (3m (3
m (3
µ
µµ
µ
m)
m)m)
m)
1.7
1.71.7
1.7
µ
µµ
µ
m
mm
m
0.7
0.70.7
0.7
µ
µµ
µ
m
mm
m
p strap
p strapp strap
p strap
n
nn
n-
--
-well
wellwell
well
on same
on sameon same
on same
(different)
(different) (different)
(different)
potential
potentialpotential
potential
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
1
11
1
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
1
11
1
µ
µµ
µ
m
mm
m
n strap
n strapn strap
n strap
1
11
1
µ
µµ
µ
m
mm
m
0.5
0.50.5
0.5
µ
µµ
µ
m
mm
m
0.5
0.50.5
0.5
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
n strap
n strapn strap
n strap
MicroLab, VLSI-15 (14/36)
JMM v1.4
Layout Rules (C05M
Layout Rules (C05MLayout Rules (C05M
Layout Rules (C05M-
--
-D) #2
D) #2D) #2
D) #2

poly,
poly,poly,
poly,fets
fetsfets
fets
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.7
0.70.7
0.7
µ
µµ
µ
m
mm
m
0.5
0.50.5
0.5
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.35
0.350.35
0.35
µ
µµ
µ
m
mm
m
MicroLab, VLSI-15 (15/36)
JMM v1.4
Layout Rules (C05M
Layout Rules (C05MLayout Rules (C05M
Layout Rules (C05M-
--
-D) #3
D) #3D) #3
D) #3

abutting straps
abutting strapsabutting straps
abutting straps
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
abutting
abuttingabutting
abutting
strap
strapstrap
strap
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
1.15
1.151.15
1.15
µ
µµ
µ
m
mm
m
1.15
1.151.15
1.15
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
abutting
abuttingabutting
abutting
strap
strapstrap
strap
1.15
1.151.15
1.15
µ
µµ
µ
m
mm
m
1
11
1
µ
µµ
µ
m
mm
m
1.6
1.61.6
1.6
µ
µµ
µ
m
mm
m
abutting
abuttingabutting
abutting
strap
strapstrap
strap
MicroLab, VLSI-15 (16/36)
JMM v1.4
Layout Rules (C05M
Layout Rules (C05MLayout Rules (C05M
Layout Rules (C05M-
--
-D) #4
D) #4D) #4
D) #4

metal, contacts, via1, via2
metal, contacts, via1, via2metal, contacts, via1, via2
metal, contacts, via1, via2
0.7
0.70.7
0.7
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
0.9
0.90.9
0.9
µ
µµ
µ
m
mm
m
0.9
0.90.9
0.9
µ
µµ
µ
m
mm
m
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
1.1
1.11.1
1.1
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
0.2
0.20.2
0.2
µ
µµ
µ
m
mm
m
0.25
0.250.25
0.25
µ
µµ
µ
m
mm
m
0.25
0.250.25
0.25
µ
µµ
µ
m
mm
m
0.9
0.90.9
0.9
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
0.5
0.50.5
0.5
µ
µµ
µ
m
mm
m
0.25
0.250.25
0.25
µ
µµ
µ
m
mm
m
0.25
0.250.25
0.25
µ
µµ
µ
m
mm
m
0.35
0.350.35
0.35
µ
µµ
µ
m
mm
m
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
1
11
1
µ
µµ
µ
m
mm
m
0.7
0.70.7
0.7
µ
µµ
µ
m
mm
m
0.2
0.20.2
0.2
µ
µµ
µ
m
mm
m
via1 need to be
via1 need to bevia1 need to be
via1 need to be
covered by metal2
covered by metal2covered by metal2
covered by metal2
contacts need to be
contacts need to becontacts need to be
contacts need to be
covered by metal1
covered by metal1covered by metal1
covered by metal1
contact
contactcontact
contact
via1
via1via1
via1
via2
via2via2
via2
contact
contactcontact
contact
via1
via1via1
via1
via2
via2via2
via2
0.6
0.60.6
0.6
µ
µµ
µ
m
mm
m
0.8
0.80.8
0.8
µ
µµ
µ
m
mm
m
MicroLab, VLSI-15 (17/36)
JMM v1.4
Sticks and Compaction
Sticks and CompactionSticks and Compaction
Sticks and Compaction
Stick diagram
Stick diagramStick diagram
Stick diagram Horizontal constraints
Horizontal constraintsHorizontal constraints
Horizontal constraints
for compaction in X
for compaction in Xfor compaction in X
for compaction in X
Compact X then Y
Compact X then YCompact X then Y
Compact X then Y
Compact Y then X
Compact Y then XCompact Y then X
Compact Y then X
Compact X with jog
Compact X with jogCompact X with jog
Compact X with jog
insertion, then Y
insertion, then Yinsertion, then Y
insertion, then Y
MicroLab, VLSI-15 (18/36)
JMM v1.4
Digital Layout: Choosing a “style”
Digital Layout: Choosing a “style”Digital Layout: Choosing a “style”
Digital Layout: Choosing a “style”
Vertical Gates
Vertical GatesVertical Gates
Vertical Gates
Good for circuits where
Good for circuits whereGood for circuits where
Good for circuits where fets
fetsfets
fets sizes are
sizes are sizes are
sizes are
similar and each gate has limited
similar and each gate has limitedsimilar and each gate has limited
similar and each gate has limited
fanout
fanoutfanout
fanout. Best choice for multiple
. Best choice for multiple . Best choice for multiple
. Best choice for multiple
input static gates and for
input static gates and forinput static gates and for
input static gates and for datapaths
datapathsdatapaths
datapaths.
..
.
Horizontal Gates
Horizontal GatesHorizontal Gates
Horizontal Gates
Good for circuits where long and
Good for circuits where long and Good for circuits where long and
Good for circuits where long and
short
shortshort
short fets
fetsfets
fets are needed or where nodes
are needed or where nodes are needed or where nodes
are needed or where nodes
must control many
must control manymust control many
must control many fets
fetsfets
fets. Often used
. Often used . Often used
. Often used
in multiple
in multiplein multiple
in multiple-
--
-output complex gates
output complex gates output complex gates
output complex gates
(e.g, sum/carry circuits).
(e.g, sum/carry circuits).(e.g, sum/carry circuits).
(e.g, sum/carry circuits).
What about routing signals between gates? Note that both layout
What about routing signals between gates? Note that both layoutWhat about routing signals between gates? Note that both layout
What about routing signals between gates? Note that both layouts block
s block s block
s block
metal/poly routing inside the cell. Choices: metal2 routing ove
metal/poly routing inside the cell. Choices: metal2 routing ovemetal/poly routing inside the cell. Choices: metal2 routing ove
metal/poly routing inside the cell. Choices: metal2 routing over the cell or
r the cell or r the cell or
r the cell or
routing above/below the cell.
routing above/below the cell.routing above/below the cell.
routing above/below the cell.



avoid long (> 50 squares) poly runs
avoid long (> 50 squares) poly runsavoid long (> 50 squares) poly runs
avoid long (> 50 squares) poly runs



don’t “capture” white space in a cell
don’t “capture” white space in a celldon’t “capture” white space in a cell
don’t “capture” white space in a cell



don’t obsess over the layout, instead make a
don’t obsess over the layout, instead make adon’t obsess over the layout, instead make a
don’t obsess over the layout, instead make a
second pass,
second pass, second pass,
second pass, optimizing
optimizingoptimizing
optimizing where it counts
where it countswhere it counts
where it counts
MicroLab, VLSI-15 (19/36)
JMM v1.4
Digital Layout:
Digital Layout:Digital Layout:
Digital Layout:
Optimising
OptimisingOptimising
OptimisingConnections
ConnectionsConnections
Connections
Which is the better gate layout?
Which is the better gate layout?Which is the better gate layout?
Which is the better gate layout?



considering node capacitances?
considering node capacitances?considering node capacitances?
considering node capacitances?



considering “
considering “considering “
considering “composibility
composibilitycomposibility
composibility” with
” with” with
” with
neighbouring
neighbouringneighbouring
neighbouring gates?
gates?gates?
gates?
MicroLab, VLSI-15 (20/36)
JMM v1.4
Digital Layout: Big vs. Parallel
Digital Layout: Big vs. ParallelDigital Layout: Big vs. Parallel
Digital Layout: Big vs. Parallel
Which is the better gate layout?
Which is the better gate layout?Which is the better gate layout?
Which is the better gate layout?



considering node capacitances?
considering node capacitances?considering node capacitances?
considering node capacitances?



considering “
considering “considering “
considering “composibility
composibilitycomposibility
composibility” with
” with” with
” with
neighbouring
neighbouringneighbouring
neighbouring gates?
gates?gates?
gates?
area = 133
area = 133area = 133
area = 133
µ
µµ
µ
m
mm
m
2
22
2
area = 94
area = 94area = 94
area = 94
µ
µµ
µ
m
mm
m
2
22
2
area = 73
area = 73area = 73
area = 73
µ
µµ
µ
m
mm
m
2
22
2
can’t make gates too
can’t make gates toocan’t make gates too
can’t make gates too
long because of poly
long because of polylong because of poly
long because of poly
resistance! Eventually
resistance! Eventuallyresistance! Eventually
resistance! Eventually
really large transistors
really large transistorsreally large transistors
really large transistors
have to broken into
have to broken into have to broken into
have to broken into
smaller transistors in
smaller transistors insmaller transistors in
smaller transistors in
wired in parallel.
wired in parallel.wired in parallel.
wired in parallel.
MicroLab, VLSI-15 (21/36)
JMM v1.4
Digital Layout: Eliminating Gaps
Digital Layout: Eliminating GapsDigital Layout: Eliminating Gaps
Digital Layout: Eliminating Gaps
D
DD
D
A
AA
A
E
EE
E
B
BB
B
C
CC
C
B
BB
B
C
CC
C
D
DD
D
E
EE
E
A
AA
A
A
AA
AB
BB
BC
CC
C D
DD
DE
EE
E
A
AA
A B
BB
B C
CC
C D
DD
D E
EE
E
A
AA
A
D
DD
D
E
EE
E
B
BB
B
C
CC
C
B
BB
B
C
CC
C
D
DD
D
E
EE
E
A
AA
A
MicroLab, VLSI-15 (22/36)
JMM v1.4
Analog Layout: Large Transistors
Analog Layout: Large TransistorsAnalog Layout: Large Transistors
Analog Layout: Large Transistors

W/L can be very large in analog circuits
W/L can be very large in analog circuitsW/L can be very large in analog circuits
W/L can be very large in analog circuits

due to asymmetric layout, node1 has a smaller
due to asymmetric layout, node1 has a smaller due to asymmetric layout, node1 has a smaller
due to asymmetric layout, node1 has a smaller
capacitor which should be used for the most critical
capacitor which should be used for the most critical capacitor which should be used for the most critical
capacitor which should be used for the most critical
node (high impedance)
node (high impedance)node (high impedance)
node (high impedance)
Q
QQ
Q
1
11
1
Q
QQ
Q
2
22
2
Q
QQ
Q
3
33
3
Q
QQ
Q
4
44
4
node 2
node 2node 2
node 2
node 1
node 1node 1
node 1
node 1
node 1node 1
node 1
node 2
node 2node 2
node 2 gates
gatesgates
gates
Q
QQ
Q
1
11
1
Q
QQ
Q
2
22
2
Q
QQ
Q
3
33
3
Q
QQ
Q
4
44
4
J
JJ
J
1
11
1
J
JJ
J
2
22
2
J
JJ
J
3
33
3
J
JJ
J
4
44
4
J
JJ
J
5
55
5
MicroLab, VLSI-15 (23/36)
JMM v1.4
Analog Layout: Matching
Analog Layout: MatchingAnalog Layout: Matching
Analog Layout: Matching

Using lithography techniques a variety of two
Using lithography techniques a variety of twoUsing lithography techniques a variety of two
Using lithography techniques a variety of two-
--
-
dimensional effects can cause effective sizes of
dimensional effects can cause effective sizes of dimensional effects can cause effective sizes of
dimensional effects can cause effective sizes of
components to differ from the sizes of the glass
components to differ from the sizes of the glass components to differ from the sizes of the glass
components to differ from the sizes of the glass
layout masks.
layout masks.layout masks.
layout masks.

lateral diffusion
lateral diffusionlateral diffusion
lateral diffusion

overetching
overetchingoveretching
overetching

mask misalignment ...
mask misalignment ...mask misalignment ...
mask misalignment ...
Goal:
Goal:Goal:
Goal:Matching second
Matching secondMatching second
Matching second-
--
-order size error effects is done
order size error effects is done order size error effects is done
order size error effects is done
mainly by making larger objects out of several unit
mainly by making larger objects out of several unitmainly by making larger objects out of several unit
mainly by making larger objects out of several unit-
--
-
sized components connected together. For best
sized components connected together. For best sized components connected together. For best
sized components connected together. For best
accuracy, the bounding conditions around all objects
accuracy, the bounding conditions around all objects accuracy, the bounding conditions around all objects
accuracy, the bounding conditions around all objects
should be matched, even when this means adding
should be matched, even when this means adding should be matched, even when this means adding
should be matched, even when this means adding
extra unused components.
extra unused components.extra unused components.
extra unused components.
well
wellwell
well
SiO
SiOSiO
SiO
2
22
2
protection
protectionprotection
protection
lateral diffusion
lateral diffusionlateral diffusion
lateral diffusion
under SiO
under SiOunder SiO
under SiO
2
22
2
mask
maskmask
mask
SiO
SiOSiO
SiO
2
22
2
protection
protectionprotection
protection
poly gate
poly gatepoly gate
poly gate
overetching
overetchingoveretching
overetching
MicroLab, VLSI-15 (24/36)
JMM v1.4
Matching Transistor Layouts:
Matching Transistor Layouts:Matching Transistor Layouts:
Matching Transistor Layouts:
Common
CommonCommon
Common-
--
-Centroid
CentroidCentroid
CentroidLayout
LayoutLayout
Layout

use
useuse
use interdigitated
interdigitatedinterdigitated
interdigitated
finger structures
finger structures finger structures
finger structures
for keeping the
for keeping the for keeping the
for keeping the
effect of temp
effect of temp effect of temp
effect of temp
and oxide
and oxide and oxide
and oxide
thickness
thickness thickness
thickness
gradients low
gradients lowgradients low
gradients low

use one outside
use one outside use one outside
use one outside
finger for M1, one
finger for M1, one finger for M1, one
finger for M1, one
for M2
for M2for M2
for M2

symmetry in x & y
symmetry in x & ysymmetry in x & y
symmetry in x & y

fets
fetsfets
fets in analog
in analog in analog
in analog
circuitry are
circuitry are circuitry are
circuitry are
typically much
typically much typically much
typically much
wider than in
wider than in wider than in
wider than in
digital circuits
digital circuitsdigital circuits
digital circuits
D
DD
D
M1
M1M1
M1
D
DD
D
M2
M2M2
M2
G
GG
G
M1
M1M1
M1
G
GG
G
M2
M2M2
M2
S
SS
S
M1,M2
M1,M2M1,M2
M1,M2
M1
M1M1
M1
M1
M1M1
M1
M1
M1M1
M1
M1
M1M1
M1
M1
M1M1
M1
M2
M2M2
M2
M2
M2M2
M2
M2
M2M2
M2
M2
M2M2
M2
M2
M2M2
M2
D
DD
D
M1
M1M1
M1
D
DD
D
M2
M2M2
M2
S
SS
S
M1,M2
M1,M2M1,M2
M1,M2
G
GG
G
M1
M1M1
M1
G
GG
G
M1
M1M1
M1
MicroLab, VLSI-15 (25/36)
JMM v1.4
Capacitor Matching #1
Capacitor Matching #1Capacitor Matching #1
Capacitor Matching #1

material
materialmaterial
material

preferable poly1
preferable poly1 preferable poly1
preferable poly1 -
--
- poly2 structures (only C05M
poly2 structures (only C05Mpoly2 structures (only C05M
poly2 structures (only C05M-
--
-A)
A)A)
A)

if not available: poly1
if not available: poly1 if not available: poly1
if not available: poly1 -
--
- diffusion (C05M
diffusion (C05Mdiffusion (C05M
diffusion (C05M-
--
-D), but
D), but D), but
D), but
nonlinear due to voltage dependency
nonlinear due to voltage dependencynonlinear due to voltage dependency
nonlinear due to voltage dependency

sandwich structures with poly
sandwich structures with poly sandwich structures with poly
sandwich structures with poly -
--
- metal1
metal1metal1
metal1

in analog design very often precise ratios of
in analog design very often precise ratios of in analog design very often precise ratios of
in analog design very often precise ratios of
capacitors are used
capacitors are usedcapacitors are used
capacitors are used

major sources of errors in realized capacitors are
major sources of errors in realized capacitors are major sources of errors in realized capacitors are
major sources of errors in realized capacitors are
due to
due todue to
due to overetching
overetchingoveretching
overetching and something less relevant is
and something less relevant is and something less relevant is
and something less relevant is
an oxide thickness gradient across the surface.
an oxide thickness gradient across the surface.an oxide thickness gradient across the surface.
an oxide thickness gradient across the surface.
Goal:
Goal:Goal:
Goal:Larger capacitors are realized by a parallel
Larger capacitors are realized by a parallel Larger capacitors are realized by a parallel
Larger capacitors are realized by a parallel
combination of smaller unit
combination of smaller unitcombination of smaller unit
combination of smaller unit-
--
-sized capacitors
sized capacitors sized capacitors
sized capacitors
(
((
(overetching
overetchingoveretching
overetching). If unit
). If unit). If unit
). If unit-
--
-size capacitors are not
size capacitors are not size capacitors are not
size capacitors are not
realizable,
realizable,realizable,
realizable,overetching
overetchingoveretching
overetchingcan still be minimized by
can still be minimized by can still be minimized by
can still be minimized by
realizing a
realizing arealizing a
realizing anonunit
nonunitnonunit
nonunit-
--
-sized capacitor with a specific
sized capacitor with a specific sized capacitor with a specific
sized capacitor with a specific
perimeter
perimeterperimeter
perimeter-
--
-to area ratio. For very accurate ratios
to area ratio. For very accurate ratios to area ratio. For very accurate ratios
to area ratio. For very accurate ratios
additionally common
additionally commonadditionally common
additionally common-
--
-centroid
centroidcentroid
centroidlayout is used (oxide
layout is used (oxide layout is used (oxide
layout is used (oxide
thickness gradient).
thickness gradient). thickness gradient).
thickness gradient).
MicroLab, VLSI-15 (26/36)
JMM v1.4
Capacitor Matching #2
Capacitor Matching #2Capacitor Matching #2
Capacitor Matching #2
exx
a
∆−=
2
xyCA
t
C
ox
ox
ox
==
ε
eyy
a
∆−=
2
( )( )
eyexCyxCC
oxaaoxa
∆−∆−==
22
xyCyxCC
oxaaoxt
−=∆
( )
oxt
CyxeC
+∆−≅∆
2
x
xx
x
y
yy
y
ex
∆−
2
ey
∆−
2
e

e

( )
( )
11
22
1
2
1
1
ε
ε
+
+
=
C
C
C
C
a
a
21
εε =
C
CC
C
a
aa
a
ideally
ideallyideally
ideally
(
)
( )
n
C
nC
C
nC
C
C
a
a
a
a
=
+
+
==
ε
ε
1
1
1
1
1
1
1
2
C
CC
C
1
11
1
C
CC
C
2
22
2
C
CC
C
2
22
2
C
CC
C
1
11
1
poly bottom plate
poly bottom platepoly bottom plate
poly bottom plate
poly top plate
poly top platepoly top plate
poly top plate
poly etch matching
poly etch matchingpoly etch matching
poly etch matching
well region
well regionwell region
well region
well contacts
well contactswell contacts
well contacts
( )
xy
y
xe
C
C
t
+∆−
=

=
2
ε
MicroLab, VLSI-15 (27/36)
JMM v1.4
Capacitor Matching #3
Capacitor Matching #3Capacitor Matching #3
Capacitor Matching #3
2
1
22
1
2
1
2
x
yx
A
A
C
C
K
===

unit sized capacitors C
unit sized capacitors Cunit sized capacitors C
unit sized capacitors C
1
11
1
are squared
are squaredare squared
are squared

nonunit
nonunitnonunit
nonunit-
--
-sized capacitors C
sized capacitors Csized capacitors C
sized capacitors C
2
22
2
are rectangular and
are rectangular and are rectangular and
are rectangular and
usually between 1 and 2 times unit
usually between 1 and 2 times unitusually between 1 and 2 times unit
usually between 1 and 2 times unit-
--
-sized capacitors
sized capacitors sized capacitors
sized capacitors
(K>1)
(K>1)(K>1)
(K>1)

perimeter
perimeterperimeter
perimeter-
--
-to
toto
to-
--
-area ratio should be kept identical
area ratio should be kept identicalarea ratio should be kept identical
area ratio should be kept identical
1
1
2
2
A
P
A
P
=
K
A
A
P
P
==
1
2
1
2
1
22
2x
yx
K
+
=
(
)
KKKxy
−±=
2
12
4 units
4 units4 units
4 units
K=1 ... 2
K=1 ... 2K=1 ... 2
K=1 ... 2
MicroLab, VLSI-15 (28/36)
JMM v1.4
Analog Layout: Resistor #1
Analog Layout: Resistor #1Analog Layout: Resistor #1
Analog Layout: Resistor #1

resistor value:
resistor value:resistor value:
resistor value:

material: many different materials can be used.
material: many different materials can be used. material: many different materials can be used.
material: many different materials can be used.
They have different non
They have different nonThey have different non
They have different non-
--
-ideal effects. Absolute
ideal effects. Absolute ideal effects. Absolute
ideal effects. Absolute
accuracy is low (+
accuracy is low (+accuracy is low (+
accuracy is low (+-
--
-20% or less), matching can be
20% or less), matching can be 20% or less), matching can be
20% or less), matching can be
made to be in the order of 1% at most.
made to be in the order of 1% at most.made to be in the order of 1% at most.
made to be in the order of 1% at most.

polysilicon (
polysilicon (polysilicon (
polysilicon (salicided
salicidedsalicided
salicided and non
and nonand non
and non salicided
salicidedsalicided
salicided in C05M
in C05Min C05M
in C05M-
--
-A and
A and A and
A and
C05M
C05MC05M
C05M-
--
-D process)
D process)D process)
D process)

diffusions or ion
diffusions or iondiffusions or ion
diffusions or ion-
--
-implanted regions (n/p
implanted regions (n/pimplanted regions (n/p
implanted regions (n/p-
--
-diff, n
diff, ndiff, n
diff, n-
--
-well)
well)well)
well)
sq
R
W
L
R
=
t
R
sq
ρ
=
material
materialmaterial
material typ Rsq
typ Rsqtyp Rsq
typ Rsq temp
temptemp
temp coeff
coeffcoeff
coeff nonideality
nonidealitynonideality
nonideality
metal1
metal1metal1
metal1 72m
72m72m
72m

ΩΩ

0
00
0 not used
not usednot used
not used
metal2
metal2metal2
metal2 55m
55m55m
55m

ΩΩ

0
00
0 not used
not usednot used
not used
metal3
metal3metal3
metal3 34m
34m34m
34m

ΩΩ

0
00
0 not used
not usednot used
not used
salicid
salicidsalicid
salicid poly
polypoly
poly 2.3
2.32.3
2.3

ΩΩ

4300ppm/C
4300ppm/C4300ppm/C
4300ppm/C parasitic cap
parasitic capparasitic cap
parasitic cap
n
nn
n
+
++
+
diff
diffdiff
diff sal
salsal
sal 2.3
2.32.3
2.3

ΩΩ

4300ppm/C
4300ppm/C4300ppm/C
4300ppm/C v
vv
v dep
depdep
dep, non
, non, non
, non lin
linlin
lin
p
pp
p
+
++
+
diff
diffdiff
diff sal
salsal
sal 2.1
2.12.1
2.1

ΩΩ

4300ppm/C
4300ppm/C4300ppm/C
4300ppm/C v
vv
v dep
depdep
dep,
,,
,nonlin
nonlinnonlin
nonlin
unsal
unsalunsal
unsal n
nn
n
+
++
+
poly
polypoly
poly 325
325325
325

ΩΩ
Ω −
−−
−2000
20002000
2000
ppm/C
ppm/Cppm/C
ppm/C parasitic cap
parasitic capparasitic cap
parasitic cap
n
nn
n
+
++
+
diff
diffdiff
diff unsal
unsalunsal
unsal 50
5050
50

ΩΩ

1600ppm/C
1600ppm/C1600ppm/C
1600ppm/C v
vv
v dep
depdep
dep, non
, non, non
, non lin
linlin
lin
p
pp
p
+
++
+
diff
diffdiff
diff unsal
unsalunsal
unsal 70
7070
70

ΩΩ

1600ppm/C
1600ppm/C1600ppm/C
1600ppm/C v
vv
v dep
depdep
dep,
,,
,nonlin
nonlinnonlin
nonlin
n
nn
n-
--
-well
wellwell
well 1.3k
1.3k1.3k
1.3k

ΩΩ

4300ppm/C
4300ppm/C4300ppm/C
4300ppm/C v dependent
v dependentv dependent
v dependent
most common used
most common usedmost common used
most common used
MicroLab, VLSI-15 (29/36)
JMM v1.4
Analog Layout: Resistor #2
Analog Layout: Resistor #2Analog Layout: Resistor #2
Analog Layout: Resistor #2
Examples of possible resistor layout
Examples of possible resistor layoutExamples of possible resistor layout
Examples of possible resistor layout
2.11
2.11 2.11
2.11 R
RR
R
sq
sqsq
sq
0.14
0.14 0.14
0.14 R
RR
R
sq
sqsq
sq
matched resistors
matched resistorsmatched resistors
matched resistors
MicroLab, VLSI-15 (30/36)
JMM v1.4
Analog Layout:
Analog Layout: Analog Layout:
Analog Layout:
Noise Considerations #1
Noise Considerations #1Noise Considerations #1
Noise Considerations #1
Where does noise coupling occur
Where does noise coupling occurWhere does noise coupling occur
Where does noise coupling occur

every time a digital gate changes its state a glitch
every time a digital gate changes its state a glitch every time a digital gate changes its state a glitch
every time a digital gate changes its state a glitch
is injected on the digital power supply and in the
is injected on the digital power supply and in the is injected on the digital power supply and in the
is injected on the digital power supply and in the
surrounding substrate
surrounding substratesurrounding substrate
surrounding substrate

direct
directdirect
direct ohmic
ohmicohmic
ohmic connections (power supply line)
connections (power supply line)connections (power supply line)
connections (power supply line)

via electromagnetic fields (e.g. capacitive coupling
via electromagnetic fields (e.g. capacitive coupling via electromagnetic fields (e.g. capacitive coupling
via electromagnetic fields (e.g. capacitive coupling
in and from substrate)
in and from substrate)in and from substrate)
in and from substrate)
How can noise be reduced
How can noise be reducedHow can noise be reduced
How can noise be reduced

use of different power supply lines
use of different power supply linesuse of different power supply lines
use of different power supply lines

layout analog and digital circuitry in different
layout analog and digital circuitry in different layout analog and digital circuitry in different
layout analog and digital circuitry in different
sections of the chip
sections of the chipsections of the chip
sections of the chip

protect analog layout by guard rings
protect analog layout by guard ringsprotect analog layout by guard rings
protect analog layout by guard rings

use shields connected to power and ground
use shields connected to power and grounduse shields connected to power and ground
use shields connected to power and ground
analog part
analog partanalog part
analog part
digital part
digital partdigital part
digital part
pad
padpad
pad
pin
pinpin
pin
power supply
power supplypower supply
power supply
analog part
analog partanalog part
analog part
digital part
digital partdigital part
digital part
pad
padpad
pad
pin
pinpin
pin
power supply
power supplypower supply
power supply
analog part
analog partanalog part
analog part
digital part
digital partdigital part
digital part
power supply
power supplypower supply
power supply
pad
padpad
pad
pad
padpad
pad
pin
pinpin
pin
pad
padpad
pad
pin
pinpin
pin
MicroLab, VLSI-15 (31/36)
JMM v1.4
Analog Layout:
Analog Layout: Analog Layout:
Analog Layout:
Noise Considerations #2
Noise Considerations #2Noise Considerations #2
Noise Considerations #2

Use of shields
Use of shieldsUse of shields
Use of shields
p
pp
p
-
--
-
substrate
substratesubstrate
substrate
n
nn
n-
--
-well
wellwell
well
n
nn
n
+
++
+
n
nn
n
+
++
+
n
nn
n
+
++
+
analog interconnect
analog interconnectanalog interconnect
analog interconnect digital interconnect
digital interconnectdigital interconnect
digital interconnect
ground shield
ground shieldground shield
ground shield

Separate analog and digital parts with guard rings
Separate analog and digital parts with guard ringsSeparate analog and digital parts with guard rings
Separate analog and digital parts with guard rings
p
pp
p
-
--
-
substrate
substratesubstrate
substrate
n
nn
n-
--
-well
wellwell
well
p
pp
p
+
++
+
n
nn
n
+
++
+
p
pp
p
+
++
+
analog region
analog regionanalog region
analog region digital region
digital regiondigital region
digital region
VDD
VDDVDD
VDDVSS
VSSVSS
VSS VSS
VSSVSS
VSS
depletion region
depletion regiondepletion region
depletion region
as bypass capacitor
as bypass capacitoras bypass capacitor
as bypass capacitor
MicroLab, VLSI-15 (32/36)
JMM v1.4
Summary of Analog Layout Rules
Summary of Analog Layout RulesSummary of Analog Layout Rules
Summary of Analog Layout Rules
When drawing layout for analog circuits, one has to
When drawing layout for analog circuits, one has to When drawing layout for analog circuits, one has to
When drawing layout for analog circuits, one has to
consider many details
consider many detailsconsider many details
consider many details

layout design rules, in order to get correct circuits
layout design rules, in order to get correct circuits layout design rules, in order to get correct circuits
layout design rules, in order to get correct circuits
without shortcuts between layers, or open circuits
without shortcuts between layers, or open circuits without shortcuts between layers, or open circuits
without shortcuts between layers, or open circuits
due to misaligned layers
due to misaligned layersdue to misaligned layers
due to misaligned layers

avoid parasitic components
avoid parasitic componentsavoid parasitic components
avoid parasitic components

resistors: take care of length of interconnect wires and
resistors: take care of length of interconnect wires and resistors: take care of length of interconnect wires and
resistors: take care of length of interconnect wires and
material used for interconnects Add enough contacts.
material used for interconnects Add enough contacts.material used for interconnects Add enough contacts.
material used for interconnects Add enough contacts.

Capacitors: There is a parasitic capacitor between any
Capacitors: There is a parasitic capacitor between any Capacitors: There is a parasitic capacitor between any
Capacitors: There is a parasitic capacitor between any
two isolation layers. Minimize size of all areas that do
two isolation layers. Minimize size of all areas that do two isolation layers. Minimize size of all areas that do
two isolation layers. Minimize size of all areas that do
not need to have a specific size for their functionality.
not need to have a specific size for their functionality.not need to have a specific size for their functionality.
not need to have a specific size for their functionality.

Increase matching accuracy by
Increase matching accuracy byIncrease matching accuracy by
Increase matching accuracy by

using common
using commonusing common
using common centroid
centroidcentroid
centroid layout
layoutlayout
layout

using non minimum sized components
using non minimum sized componentsusing non minimum sized components
using non minimum sized components

using capacitors with constant area to perimeter ratio
using capacitors with constant area to perimeter ratiousing capacitors with constant area to perimeter ratio
using capacitors with constant area to perimeter ratio

reduce noise coupling by
reduce noise coupling byreduce noise coupling by
reduce noise coupling by

separating analog and digital parts
separating analog and digital partsseparating analog and digital parts
separating analog and digital parts

using separate power supplies
using separate power suppliesusing separate power supplies
using separate power supplies

using shielding techniques
using shielding techniquesusing shielding techniques
using shielding techniques
MicroLab, VLSI-15 (33/36)
JMM v1.4
Checking Layouts
Checking LayoutsChecking Layouts
Checking Layouts
Design Rule Checker
Design Rule CheckerDesign Rule Checker
Design Rule Checker (DRC). This is a program that checks each
(DRC). This is a program that checks each (DRC). This is a program that checks each
(DRC). This is a program that checks each
piece of the layout against the process design rules. This is a
piece of the layout against the process design rules. This is apiece of the layout against the process design rules. This is a
piece of the layout against the process design rules. This is a
slow process:
slow process:slow process:
slow process:

canonicalize
canonicalizecanonicalize
canonicalize layout into a set of leading and
layout into a set of leading andlayout into a set of leading and
layout into a set of leading and

trailing non
trailing nontrailing non
trailing non-
--
-overlapping mask edges. Some Boolean mask
overlapping mask edges. Some Boolean mask overlapping mask edges. Some Boolean mask
overlapping mask edges. Some Boolean mask
operations may be needed. determine electrical connectivity
operations may be needed. determine electrical connectivity operations may be needed. determine electrical connectivity
operations may be needed. determine electrical connectivity
and label each edge with the node it belongs to.
and label each edge with the node it belongs to.and label each edge with the node it belongs to.
and label each edge with the node it belongs to.

test each edge end point against neighboring
test each edge end point against neighboringtest each edge end point against neighboring
test each edge end point against neighboring
edges to check for spacing (leading edges) and width
edges to check for spacing (leading edges) and width edges to check for spacing (leading edges) and width
edges to check for spacing (leading edges) and width
(trailing edges) violations.
(trailing edges) violations.(trailing edges) violations.
(trailing edges) violations.
Layout vs. Schematic
Layout vs. SchematicLayout vs. Schematic
Layout vs. Schematic (LVS). First a netlist is
(LVS). First a netlist is (LVS). First a netlist is
(LVS). First a netlist is extracted
extracted extracted
extracted from the
from the from the
from the
layout. Use the electrical info generated by the DRC and then
layout. Use the electrical info generated by the DRC and then layout. Use the electrical info generated by the DRC and then
layout. Use the electrical info generated by the DRC and then
recognize transistors are juxtapositions of channel with
recognize transistors are juxtapositions of channel with recognize transistors are juxtapositions of channel with
recognize transistors are juxtapositions of channel with
diffusion. Then see if extracted netlist is
diffusion. Then see if extracted netlist is diffusion. Then see if extracted netlist is
diffusion. Then see if extracted netlist is isomorphic
isomorphicisomorphic
isomorphic to the
to the to the
to the
schematic netlist. This is done by a coloring algorithm:
schematic netlist. This is done by a coloring algorithm:schematic netlist. This is done by a coloring algorithm:
schematic netlist. This is done by a coloring algorithm:

initialize all nodes to the same color
initialize all nodes to the same colorinitialize all nodes to the same color
initialize all nodes to the same color

compute a new color for each node as some hashing
compute a new color for each node as some hashing compute a new color for each node as some hashing
compute a new color for each node as some hashing
function involving the colors of connected (
function involving the colors of connected (function involving the colors of connected (
function involving the colors of connected (ie
ieie
ie, thru a
, thru a, thru a
, thru a fet
fetfet
fet)
) )
)
nodes.
nodes.nodes.
nodes.

nodes that have a unique color are isomorphic to similarly
nodes that have a unique color are isomorphic to similarly nodes that have a unique color are isomorphic to similarly
nodes that have a unique color are isomorphic to similarly
colored node in other network
colored node in other networkcolored node in other network
colored node in other network

worry about parallel
worry about parallelworry about parallel
worry about parallel fets
fetsfets
fets, ambiguous nodes
, ambiguous nodes, ambiguous nodes
, ambiguous nodes
MicroLab, VLSI-15 (34/36)
JMM v1.4
Coming Up...
Coming Up...Coming Up...
Coming Up...
Next topic:
Next topic:Next topic:
Next topic:
Small signal
Small signalSmall signal
Small signal fet
fetfet
fet model
modelmodel
model
Readings for next time…
Readings for next time…Readings for next time…
Readings for next time…
Weste
WesteWeste
Weste:
: :
:

3.4 through 3.4.7
3.4 through 3.4.73.4 through 3.4.7
3.4 through 3.4.7
Johns&Martin
Johns&MartinJohns&Martin
Johns&Martin:
: :
:

2.3 (CMOS layout design rules)
2.3 (CMOS layout design rules)2.3 (CMOS layout design rules)
2.3 (CMOS layout design rules)

2.4 (analog layout design considerations)
2.4 (analog layout design considerations)2.4 (analog layout design considerations)
2.4 (analog layout design considerations)
Optional
OptionalOptional
Optional

have a look at
have a look athave a look at
have a look at Alcatel
AlcatelAlcatel
Alcatel CMOS C05M
CMOS C05MCMOS C05M
CMOS C05M-
--
-D design rules
D design rules D design rules
D design rules
manual
manualmanual
manual
MicroLab, VLSI-15 (35/36)
JMM v1.4
Exercises: VLSI
Exercises: VLSIExercises: VLSI
Exercises: VLSI-
--
-15 #1
15 #115 #1
15 #1
Ex vlsi15.1 (difficulty: easy):
Ex vlsi15.1 (difficulty: easy):Ex vlsi15.1 (difficulty: easy):
Ex vlsi15.1 (difficulty: easy):Assume the 0.5
Assume the 0.5Assume the 0.5
Assume the 0.5
µ
µµ
µ
m
mm
m
Alcatel Mietec
Alcatel MietecAlcatel Mietec
Alcatel Mietec process. Use the
process. Use the process. Use the
process. Use the
λ
rules to
rules to rules to
rules to
calculate the minimal area and perimeter of the
calculate the minimal area and perimeter of the calculate the minimal area and perimeter of the
calculate the minimal area and perimeter of the
following layout structure.
following layout structure. following layout structure.
following layout structure.
Result: a) A
Result: a) AResult: a) A
Result: a) A
J1
J1J1
J1
=4.5
=4.5=4.5
=4.5
µ
µµ
µ
m
mm
m
2
22
2
, A
, A, A
, A
J2
J2J2
J2
=3.188
=3.188=3.188
=3.188
µ
µµ
µ
m
mm
m
2
22
2
,
, ,
,
A
AA
A
J3
J3J3
J3
=2.25
=2.25=2.25
=2.25
µ
µµ
µ
m
mm
m
2
22
2
, P
, P, P
, P
J1
J1J1
J1
=6
=6=6
=6
µ
µµ
µ
m, P
m, Pm, P
m, P
J2
J2J2
J2
=6
=6=6
=6
µ
µµ
µ
m,
m, m,
m,
P
PP
P
J3
J3J3
J3
=1.5
=1.5=1.5
=1.5
µ
µµ
µ
m (see Johns&Martin pp99)
m (see Johns&Martin pp99)m (see Johns&Martin pp99)
m (see Johns&Martin pp99)
Q
QQ
Q
1
11
1
Q
QQ
Q
2
22
2
J
JJ
J
1
11
1
J
JJ
J
3
33
3
J
JJ
J
2
22
2
MicroLab, VLSI-15 (36/36)
JMM v1.4
Exercises: VLSI
Exercises: VLSIExercises: VLSI
Exercises: VLSI-
--
-15 #2
15 #215 #2
15 #2
John&Martin pp110: 2.3 (difficulty: easy):
John&Martin pp110: 2.3 (difficulty: easy):John&Martin pp110: 2.3 (difficulty: easy):
John&Martin pp110: 2.3 (difficulty: easy):Show a
Show a Show a
Show a
layout that might be used to match two capacitors
layout that might be used to match two capacitors layout that might be used to match two capacitors
layout that might be used to match two capacitors
of size 4 and 2.314 units, where a unit
of size 4 and 2.314 units, where a unitof size 4 and 2.314 units, where a unit
of size 4 and 2.314 units, where a unit-
--
-sized
sized sized
sized
capacitor is 10
capacitor is 10capacitor is 10
capacitor is 10
µ
µµ
µ
m x 10
m x 10m x 10
m x 10
µ
µµ
µ
m.
m. m.
m.
Result: y
Result: yResult: y
Result: y
2
22
2
=19.56
=19.56=19.56
=19.56
µ
µµ
µ
m, x
m, xm, x
m, x
2
22
2
=6.717
=6.717=6.717
=6.717
µ
µµ
µ
m
mm
m
John&Martin pp123ff: 2.14, 2.15, 2.16, 2.17
John&Martin pp123ff: 2.14, 2.15, 2.16, 2.17John&Martin pp123ff: 2.14, 2.15, 2.16, 2.17
John&Martin pp123ff: 2.14, 2.15, 2.16, 2.17
4 units
4 units4 units
4 units
2.314 units
2.314 units2.314 units
2.314 units