Overview Why VLSI? VLSI and you Moore's Law

connectionbuttsΗλεκτρονική - Συσκευές

26 Νοε 2013 (πριν από 3 χρόνια και 7 μήνες)

158 εμφανίσεις

Modern VLSI Design 3e: Chapter 1
Page 1
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Overview

Why VLSI?

Moore’s Law.

The VLSI design process.
Modern VLSI Design 3e: Chapter 1
Page 2
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Why VLSI?

Integration improves the design:
–lower parasitics = higher speed;
–lower power;
–physically smaller.

Integration reduces manufacturing cost:
(almost) no manual assembly.
Modern VLSI Design 3e: Chapter 1
Page 3
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
VLSI and you

Microprocessors:
–personal computers;
–microcontrollers.

DRAM/SRAM.

Special-purpose processors.

System-on-a-chip
: all the above and analog
circuitry on one die.
Modern VLSI Design 3e: Chapter 1
Page 4
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Moore’s
Law

Gordon Moore: co-founder of Intel.

Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
Modern VLSI Design 3e: Chapter 1
Page 5
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Moore’s
Law plot
year
# transistors
100
101
100
102
100
103
104
105
106
107
108
memory
CPU
1970
196019801990
integrated
circuit
invented
2000
109
2010
Modern VLSI Design 3e: Chapter 1
Page 6
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
The VLSI design process

May be part of larger product design.

Major steps:
–specification;
–architecture;
–logic design;
–circuit design;
–layout.
Modern VLSI Design 3e: Chapter 1
Page 7
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
The steps

Specification: function, cost, etc.

Architecture: large blocks.

Logic: gates + registers.

Circuits: transistor sizes for speed, power.

Layout: determines parasitics.

Test vectors for testing.

(Application software).
Modern VLSI Design 3e: Chapter 1
Page 8
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Challenges in VLSI design

Multiple levels of abstraction: transistors to
CPUs.

Multiple and conflicting constraints: low
cost and high performance are often at odds.

Short design time: Late products are often
irrelevant.
Modern VLSI Design 3e: Chapter 1
Page 9
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Dealing with complexity

Divide-and-conquer: limit the number of
components you deal with at any one time.

Group several components into larger
components:
–transistors form gates;
–gates form functional units;
–functional units form processing elements;
–etc.
Modern VLSI Design 3e: Chapter 1
Page 10
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Hierarchical
absraction

Interior view of a component:
–components and wires that make it up.

Exterior view of a component = type:
–body;
–pins.
Full
adder
a
b
cin
sum
cout
Modern VLSI Design 3e: Chapter 1
Page 11
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Instantiating component types

Each instance has its own name:
–add1 (type full adder)
–add2 (type full adder).

Each instance is a separate copy of the type:
Add1(Full
adder)
a
b
cin
sum
cout
Add2(Full
adder)
a
b
cin
sum
Add1.a
Add2.a
Modern VLSI Design 3e: Chapter 1
Page 12
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Signal abstraction

Analog and time-continuous currents and
voltages become binary and time-discrete;

Bits
become
words
;

Groups of words (e.g. address & data)
become a
transaction
(e.g. read action on a
bus).
Modern VLSI Design 3e: Chapter 1
Page 13
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Timing abstraction

At
circuit
level: clock is just an ordinary
signal;

At
register-transfer
level (RTL) : a clock
only connects to flipflops;

At
algorithmic
level: no explicit clock,
number of clock cycles not yet known.
Modern VLSI Design 3e: Chapter 1
Page 14
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Top-down
vs
. bottom-up design

Top-down
design adds functional detail.
–Create lower levels of abstraction from upper
levels.

Bottom-up
design creates abstractions from
low-level behavior; it
reuses
subblocks with
proven characteristics.

Good design needs both top-down and
bottom-up efforts.
Modern VLSI Design 3e: Chapter 1
Page 15
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Design validation

Must check at every step that errors haven’t
been introduced–the longer an error
remains, the more expensive it becomes to
remove it.

Forward checking: compare results of less-
and more-abstract stages.

Back annotation: copy performance
numbers to earlier stages.
Modern VLSI Design 3e: Chapter 1
Page 16
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Manufacturing test

Not the same as design validation: just
because the design is right doesn’t mean
that every chip coming off the line will be
right.

Must quickly check whether manufacturing
defects destroy function of chip.

Must also speed-grade.
Modern VLSI Design 3e: Chapter 1
Page 17
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
The cost of fabrication

Current cost: about $2-3 billion.

Typical fab line occupies about 1 city block,
employs a few hundred people.

Most profitable period is first 18 months-2
years.
Modern VLSI Design 3e: Chapter 1
Page 18
Copyright  1998, 2002 Prentice Hall PTR
Revised by SG: December 1, 2002
Cost factors in ICs

Recurrent costs:
–silicon area (about 0.07
$/mm
2)
–packaging (0.1 upto
several dollars)
–testing (about 0.05
$/sec)

Typical IC: 10 to 100
mm2, 1 to 10 seconds
of test time.

Non-recurrent costs:
–design time (about 100
$/hour)
–mask sets (in the order
of 100 k$ per set)

It often happens that
silicon is not “first
time right”

new
mask sets per
redesign.