Low Power Digital VLSI Design

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26 Νοε 2013 (πριν από 3 χρόνια και 6 μήνες)

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Organized by
Dr .T.Vigneswaran
Prof .S.M. Sakthivel
School of Electronics Engineering
(SENSE)
VIT Chennai
National Level One Day Workshop
on
Low Power Digital VLSI Design
18th Oct 2013
VIT Chennai
VIT University for the past 25 years has made a mark in
the field of higher education in India imparting quality
education in a cross cultural ambience, intertwined with
extensive application oriented research. Established by
well-known educationalist and former parliamentarian,


Dr. G. Viswanathan, Founder and Chancellor

is
a visionary who transformed VIT into a center of
excellence in higher technical education. His dream
has taken the shape of
VIT Chennai.

Dr. V. Raju,
Former Professor of State University of New
York, USA, currently the Vice Chancellor,

strives
to internalize the world class educational standards.

Dr. Anand A. Samuel, Pro-Vice Chancellor

leads the
team in Chennai with the following objectives:
To maximize the Industrial Connectivity

To Create Centers of Excellence in niche areas of

research
To enrich technological and Managerial Human

Capital nurtured in a multicultural ambience
To provide a common platform for the agglomeration

of ideas of personnel from various walks of life for
learning enrichment
To create opportunities and exploit the available

resources to benefit industry/society
To encourage participation in the National Agenda of

knowledge building
To foster International collaborations for mutual

benefits in areas of research.
VIT
- A place to learn; A chance to grow
REGISTRATION DETAILS
Industry Personnel/Academicians : 800/-
Research Scholars & PG /UG Students : 750/-
Registration charges include course materials, working
lunch and high tea. Participants are requested to send
their filled in registration form (photocopy is also
acceptable) to the organizing secretary on or before 10th
Oct 2013 along with the Demand Draft drawn in favor
of
VIT Chennai
payable at
Chennai.

Travel & Accommodation
Participants are requested to make their own arrangement
for travel and accommodation.
Dates to Remember
Last date for receipt of registration

form with DD : 10-10-2013
Confirmation of Participation : 11-10-2013
Address for Communication
Organizing Secretaries
Dr.T.Vigneswaran Prof.S.M.Sakthivel
Mobile No: 9884222629 Mobile No: 9894754934
vigneswaran.t@vit.ac.in sakthivel.sm@vit.ac.in

V Floor, Academic Block,
Dept of Eletronics & Communication Engg,
School of Electronics Engineering (SENSE)
Vandalur-Kelambakkam Road,
VIT Chennai, Chennai - 600127.
Phone No: +91 44 3993 1177 / 3993 1151
Fax No : +91 44 39932555
REGISTRATION FORM
Name :
.............................................................................
Designation :
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Organization :
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Address for Correspondence :
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PIN Code :
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Phone :
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E-mail :
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PAYMENT DETAILS :
Amount :
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DD No. :
.............................................................................
Date :
.............................................................................
(In favour of VIT Chennai payable at Chennai)
Name of Bank & Branch :
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Date : Signature
About SENSE
The School of Electronics Engineering at VIT was
established for imparting state-of-the-art education,
training and research in the field Electronics &
Communication Engineering and allied areas. It
offers B.Tech,M.Tech, MS (By Research) & Ph.D
in the domains of ECE, VLSI Design & Embedded
Systems .The expertise of faculty members includes
VLSI, Communication, Embedded Systems & Signal
Processing.
About the workshop

The objective of the workshop is to bring people
engaged in teaching, research, industries and education
together to enhance their knowledge level in the fields
of Digital VLSI Design Using Cadence Tools
(Front
End Flow).
Eminent resource persons from academia and industries
will share and disseminate scientific knowledge and
design methodologies, which will help the participants
to set new milestones in the above mentioned fields of
research for their pursuit.
The hands-on training session includes the RTL
Simulation using NC-Launch followed by RTL-
Synthesis using RTL - Compiler ( Total- Power, Area
& Timing), then the layout Generation using SOC-
Encounter ( Place & Route). Mainly this hands -on
training covers ASIC design flow with Static Timing
Analysis.
CADENCE EDA TOOLS

Cadence is committed to helping its customers by
providing them with a pool of engineers experienced
in EDA tool use and methodologies. Realizing the
challenge of finding “design aware” engineers who
must be trained specifically in VLSI design and who
can ramp up quickly, Cadence strives to fill the quality
gap with regard to talent.
Topics to discuss
• Low Power VLSI Design Stratigies.
• RTL Simulation(Cadence-NC-Launch)
• RTL Synthesis (Cadence-RTL Compiler)
• Layout Generation (Cadence-Encounter)
Who shall attend?
The workshop is aimed at the multi-faceted audience
from Industries, Academics, Researchers and PG /UG
Students from Engineering Colleges and Universities.
Route Map
National Level One Day Workshop
on
Low Power Digital VLSI Design
18th Oct 2013