Introduction to Low-Level VLSI Design

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1
Introduction to Low-Level
VLSI Design
Andreas Schwarzbacher
1. Introduction into Low-Level Design
 IC Users (Professional):
 IC Producers:
2
Push or Pull?
IC
Technology
push
applications
pull
VLSI (V
ery L
arge S
cale I
ntegration)
3
Design Hierarchy
CMOS Technology
4
Other Technologies
Gallium Arsenide
Bipolar ECL
Optical
BICMOS
Some History
 23
rd
December 1947
William Shockley, Walther Brattain and John
Bardeen successfully tested their point-contact
 1958
 1958
Jack Kilby creates the first integrated circuit
atTexas Instrument and shows that resistors,
capacitances and transistors can exist on the same
semiconductor (Germanium)
5
And more History
 1959
Fairchild produces the first planar Silicon chip.
 1961
Camera and Instrument Corporation invents the
resistor transfer logic (RTL). And build with a RS
Flip Flop the first integrated circuit available as a
monolithic chip.
 15
th
November 1971
2. The MOS Transistor
2.1 Basic Structure
N+
N+
+
+
+
+
P
L
W
Source
Gate
Drain
Substrate/Bulk
Polysilicon
Silicon Dioxide
6
Source and Drain
The Gate
 On top of the structure is a thin layer (> 2nm) of S ilicon
Oxide as an insulator. On top of this SiO
2
layer is the
gate. The gate is used to control the current flow
between source and drain. Earlier devices used a
metal layer to form the gate. This is the reason why t his
device is called Metal Oxide Semiconductor. Because
of better electrical properties todays transistors use
polycrystalline silicon (polysilicon). This is usually n-
typed doped to form a highly conducting layer.
7
Bulk Terminal
2.2 Channel Formation
VDS
P
ID
N
+
N
+
VGS
Metal (polysilicon) gate
Silicon dioxide
Depletion region
Substrate / Bulk / Body
8
0<Vgs<Vt
 Vds = 0V and an increasing voltage is applied to Vgs.
0<Vgs<Vt
P
N
+
N
+
Depletion region
Vgs=Vt
Vgs=Vt
N
+
N
+
9
Vgs>Vt
Vgs>Vt
P
N
+
N
+
Inversion Layer
(conducting chanel)
2.3 Voltage Current Qualitatively
 The drain is now positive in comparison to the source.
Therefore a horizontal electric field is applied to th e
channel charge. This field causes an average electron dr ift
velocity from source to drain. (Hence the names drain a nd
source.)
=>
 When Id flows the potential along the channel changes. At
the source it is 0V and the drain is equal to the drai n
voltage applied. The voltage responsible for this is
described as:
10
Linear Region
P
N
+
N
+
Linear Region
Vds<(Vgs-Vt)
(Vgs-Vt)
Pinch-Off Point
P
N
+
N
+
Pinch-off
Vds=(Vgs-Vt)
(Vgs-Vt)
11
Saturated Region
P
N
+
N
+
Device Saturated
Vds>(Vgs-Vt)
(Vgs-Vt)
V
DS
vs. I
D
Saturation
Linear
ID
VDS
Pinch-off
12
2.4 Regions of Operation
Vgs < Vt
Vgs > Vt and 0 < Vds < (Vgs-Vt)
Vgs > Vt and Vds = (Vgs-Vt)
Vgs > Vt and 0 < (Vgs-Vt) < Vds
Further Regions of Operation
0 < Vgs < Vt
Vgs < 0
13
2.5 Transistor Classification
D
G
S
Vgs
Vds
D
G
S
P-Channel
 The p-channel structure also exists. Here the
substrate is n-type and the gate and source are highly
p doped. Therefore, the potentials have to be reverse d
in order to generate a mobile positive charge.

S
G
D
Vsg
Vsd
14
2.6 Voltage Current Equation
There are two reasons why it is important to accurately
describe the current voltage relationship.
Linear Region
 Linear Region (0<Vds<Vgs-Vt):
 n is the conductance parameter
ID
VDS
VGS - VT
15
here
This equation describes the increase in Ids as an
inverse parabola:
n
n
oxnn
L
W
C

=
ID
VDS
VGS - VT
Pinch-off Point
( )
2
2
tgs
n
d
VVI =

16
I
D
vs. V
DS
 Note that here Id is independent of Vds. It only
depends on the square of the effective gate voltage.
Saturation
Linear
ID
VGS-VT
VDS
Gate Overdrive
 Gates are operated at Voltages of
to obtain reasonable saturation currents. [Infinion 04 ]
17
Exercise
State how to build a fast switching device, which
delivers a large current.
Device Sizes
 Chaning the feature sizes of a MOS transitor effects
the perfromes
I
dsat
~ W
Ron ~ L/W in the linear V
DS
region
18
2.8 Summarising the Voltage
Current Equations
LINEAR
Sat.
D
S
VGS
VDS
ID
P-Channel
LINEAR
Sat.
G
D
S
VSD
VSG
ID
19
Revision of Chapter 2
 Question 1:Predict the operation of an n-MOS
transistor with a threshold voltage of 0.5V. Draw Id v s.
Vds indicating the appropriate voltages.
Verify you results in the laboratory using MSK.
Vgs Vds Operation
Region
Reasons Id vs. Vds
0 0
2 0.5
3 4
5 5
-1 4
Revision of Chapter 2 cont.
 Question 2:If the capacitance of the oxide is 3.4 10
-
3
F/m
2
and the mobility of the carriers in the channel is
470cm
2
/V*sec, calculate the gain factor (  n) and give
units for the MOS transistor with a width of 1.0  m and
length of 0.5  m.
 Question 3:If Vt=0.5V,Vgs=3V,Vds=0.7V and using
the above gain value, calculate the drain current
through the transistor.
20
3. Inverter
3.1 The Static Inverter
3.1.1 Introduction
Exercise: Derive the relationship between the circuit
and transistor voltages.
VDD (5V)
S
G
D
I
DN
D
S
G
Vi
Vo
OV
TP
[
VTP
,

P
]
TN
[
VTN
,

N
]
IDP
Solution
VDD (5V)
S
G
D
IDN
D
S
G
Vi
Vo
OV
T
P
TN
IDP
21
3.1.2 Basic Operation
For a LOW input signal:
 If Vi is low so that Tn is OFF.
VDD
S
G
D
IDN
D
S
G
Vi
Vo
OV
ON
OFF
IDN
0
V
- V )V-(V I
2
2
SD
SDTPSGPDP =






=

22
Exercise
 Show how the drain current can be 0 using only the
circuit voltages and the threshold voltages. Then solve
this equation for Vdd=5V, Vi=0V and Vtp=1V.
Solution
23
For a HIGH Input Signal
0
V
- V )V-(V I
2
2
DS
DSTnGSnDn =






=

=> Vds=0 as the only possible solution
=> Vi>(Vdd-Vtp)
=> Vo=0V
24
Voltage Transfer Function
Vo
VDD
VTN
VDD - VTP
VDD
Vi
normal operating
points
region not
yet discussed
Noisy Input Signals
+
Disturbance
Low
VDD VDD - VTP
High
OV
V
TN
OV
VDD
25
Exercise
As has been shown one of the transistors is always
OFF. Therefore, the drain current is 0.
Make a statement about the power consumption,
based on the results of this chapter.
Solution
26
3.1.3 Voltage Transfer Characteristics
The regions between 0 and Vtn as well as (Vdd-Vtp)
and Vdd were already defined in the last section. So
we focus here on defining the region between these
points.
Exercise:
Describe the output voltage behaviour at this
point using  r= n/ p.
27
Vi*
 The absence of Vo in this equation implies that Vo
drops abruptly at this point (Vi*).
If Vi is further increased:
Now Vo drops quadratic until
As has been seen the voltage Vi* is the point at which the
CMOS device switches state.
28
Voltage Transfer Graph
VDD
VDD
OV
Vi*
Vo
Vi
TN sat
TP lin
TN sat
TP sat
TN lin
TP sat
3.1.4 Design Comments
The general characteristics of a device depend on Vi*.
n
n
oxn
p
p
oxp
L
W
C
L
W
C

=
29
Therefore we get:
2
1
=
p
n
n
p
W
W


Effects of  r on the Transfer Graph
Vo
Vi

R
< 1

R
> 1

R = 1
Vi
V
2
* DD
=
30
Example
A CMOS inverter has the following voltages:Vdd=5V,
Vtn=1.2V,Vtp=0.8V. Assumed that Wn/Ln =2,
calculate Wp/Lp for Vi* to be half of the supply voltage.
Note: n/ p=2.5
3.1.5 Design Rules
 Design Rules are the limits set by a fabrication
process and vendor. They include various parameters
such as minimal width of layers or minimal distance
between two regions. The designer has to verify his
design against these rules to check whether it is
possible to implement the circuit.

31
Transitor Scaling
 For a constant Electric field:
Eh = Vdd/l = constant
 Also for smal channel devices
Ev = Vdd/T
ox
= constant
Parameters Changes
3.2 Dynamic Performance
3.2.1 Introduction
Cout
Cinter
Cin
Cout = CD(TN) + CD(TP) drive
Cint = capacitance of interconnect
Cin = CG(TN) + CG(TP) load
32
Summary
V
DD
Vi
OV
Vo
Cnode
3.2.2 Switching Times of IP
(step input function)
VDD
ON OFF
ov
OFF ON
VDD
VDD
33

VDD
VDD - VT

ov
ov
VDD
OFF

ON

OFF

S LIN
Vi
VO
TN
TP
Now the current can be described as:
(
)
(
)
[
]
[ ]
[ ]
t
Vo
CL - = I
V - V
0 + (sat)I
final i + initial i I
D
2
TNDD
N
D
2
1
DD
2
1
D
4


=

=
=
34
Propagation Delay
The propagation delay is defined as
Vi
Vo
VDD
0.5 VDD
}

t = tp

Vo = - 0.5 V
DD
 For  t=tp,  Vo=-0.5Vdd
[ ]
TNDD
DD
V
V
VV
CL
V
TNDD
N

·

=

2
tp
( )
CL
VV
tp
TNDD
N



2
35
3.2.3 Switching Times
(finite input rise time)
Vi
V
DD
VDD-VT
VT
￿
t
t
￿
i
DP
DPDNDIS
iii =
i
DN
(
)
rise
dd
tdd
rise
dd
dddd
ex
T
V
VV
T
V
VVtV
t
×

=
×
×


=
5.0
5.0)(
36
Using typical values of Vdd=5V,Vt=1V we get
Tex = 0.3T
rise
V
DD
V
DD -
V
T
VDD
.5 VDD
tex
.5 VDD
ov
ov
tp
Vi
Vo
Total Propagation Delay
( )
rise
TNDD
N
T
CL
VV
tp 3.0
2
+



37
3.2.4 Power Dissipation
causes energy loss Ep in Tp
causes energy
loss EN in TN
i
DIS
i
CH
Vi
T
i
DIS
i
CH
Ep
EN
38
Energy Taken from the Supply
 Only for a LOW to HIGH (or 0 to V
dd
) transition a
current is drawn from the supply. Such an event is
described in the equation below.
 The current is a function of the node capacitance.
∫∫
·==
T
supplydd
T
dtiVdttPE
00
)1,0(
)(

·==
dd
V
ddLoutLdd
VCdVCVE
0
2
)1,0(
39
Energy Stored in the
Node Capacitance
2
0 0 0
2
1
)(
dd
T T Vdd
LoutoutLoutcapcapcap
VCdVVCdtVidttPE
∫ ∫ ∫
·=·=·==
Power Consumption
C
active
is the sum of the active node capacitance of a
system with mnodes. It is the physical node capacitance
C
node
multiplied by the number this node switches from
LOW to HIGH per cycle n
(0,1)
.
clkddactivedynamic
fVCP
2
=

=
=
m
k
nodeactive
CnC
1
)1,0(
40
3.3 Revision of Chapter 3
 Question 1: Explain the transition of an inverter if the
input changes from HIGH to LOW. Illustrate your
description using diagrams and formulas.
 Question 2: Explain why only half of the energy taken
out of the power supply is stored in the capacitive lo ad
of the circuit. Illustrate your answer using a diagram.
3.3 Revision of Chapter 3 (cont.)
 Question 3: Derive the switching time for the output of
an inverter having the following specifications.If the
capacitance of the oxide is 3.4mF/m
2
and the mobility
of the carriers in the channel is 470cm
2
/V*sec,
calculate the gain factor (  n) and give units for the
MOS transistor with a width of 1.0  m and length of
0.5 m. and a rise time of 1ns. The supply voltage is
5V and both transistors have a threshold voltage of
1V. The node Capacitance is 1fF.