Memory - [x] Remove frame - The College of Saint Rose

clippersdogheartedΛογισμικό & κατασκευή λογ/κού

14 Δεκ 2013 (πριν από 3 χρόνια και 6 μήνες)

73 εμφανίσεις

Operating

Systems

David Goldschmidt, Ph.D.

Computer Science

The College of Saint Rose

CSCI
-
4210

Rensselaer Polytechnic Institute

Hierarchical Storage Architecture

very fast

very slow

very small

very large

non
-
volatile

volatile

Main Memory


Based on the
von Neumann
architecture,

data and program

instructions exist in

shared memory space



Repeatedly perform

fetch
-
decode
-
execute

cycles


The
execute

part

often results in data
fetch

and
store

operations

Main Memory


Locations in memory are

identified by
memory addresses



When compiled, programs

typically consist of

relocatable code




Other compiled modules

also typically consist of

relocatable code

Main Memory


At
load time
, additional

libraries also consist of

relocatable code

Main Memory


At
run time
, memory

addresses of all object

files are mapped to a

single memory space

Dynamic Loading and Linking


Using
dynamic loading
, external libraries

are not loaded when a process starts


Libraries are stored on disk in relocatable form


Libraries loaded into memory only when needed



Using
dynamic linking
, external libraries

can be preloaded into (shared) memory


When a process calls a library function, the

corresponding physical address is determined

Dynamic Linking

Swapping


Processes in the

ready queue have

memory images

waiting on disk


Processes swapped

in and out of memory

as necessary


Suffers from slow
data transfer times

Contiguous Memory Allocation


Main memory

is partitioned

and allocated

to resident

operating system

and user processes

Contiguous Memory Allocation


Main memory is partitioned

and allocated to resident

operating system and

user processes



A pair of
base

and
limit

registers define the

logical address space


also known as the

relocation registers

Contiguous Memory Allocation


CPU generates logical memory addresses


A
Memory
-
Management Unit (MMU)

maps logical memory addresses

to the
physical address space







User programs never see

physical memory addresses

also known as

a
virtual address

Contiguous Memory Allocation


Hardware protects against memory access outside
of a process’s valid memory space

Dynamic Partitions


Variable
-
length or
dynamic partitions
:


When a new process enters the system, the process
is allocated to a
contiguous

block of memory large
enough to accommodate its memory requirement

OS

Process 5

Process 8

Process 2

OS

Process 5

Process 2

OS

Process 5

Process 2

Process 9

OS

Process 5

Process 9

Process 2

Process 10

Contiguous Allocation


How best can we place new process P
i

in memory?


First
-
fit algorithm
: allocate the
first

free block

that’s large enough to accommodate P
i



Best
-
fit algorithm
: allocate the

smallest

free block that’s large

enough to accommodate P
i



Next
-
fit algorithm
: allocate the

next

free block, searching from previously allocated


Worst
-
fit algorithm
: allocate the
largest

free block

that’s large enough to accommodate P
i


Fragmentation


Memory is wasted due to
fragmentation
,

which can cause performance problems


Internal fragmentation

is wasted memory

within

a single process memory space


External fragmentation

can reduce

the number of
runnable

processes


Total memory space exists to satisfy a request,

but memory is
not

contiguous

OS

Process 5

Process 8

Process 2

unused

Process 3

Process 6

Process 12

Process 7

Process 9

Fragmentation


Reduce external fragmentation by

compaction

or
defragmentation



Rearrange memory contents to organize

all free memory blocks together in

one large block



Compaction is possible only if

relocation is dynamic and is

done at execution time


OS

Process 5

Process 8

Process 2

Process 3

Process 6

Process 12

Process 7

Process 9

Process 3

Process 6

Process 12

Process 7

Process 9

defragmentation is expensive

Noncontiguous Allocation


A
noncontiguous allocation

scheme circumvents
the external fragmentation problem


Slice up physical memory into
fixed
-
sized blocks

called
frames

(size typically ranges from 2
9

to 2
14
)


Slice up logical memory into fixed
-
sized blocks

called
pages



Allocate pages into frames (frame size equals page size)



Operating system keeps track of all free frames

Noncontiguous Allocation


When a process of size
n

pages is ready to execute,

operating system finds
n

free frames



Operating system

keeps track of pages

via a
page table


main memory

process P
i

==

in use

==

free

Paging via a Page Table


A
page table

maps

logical memory

addresses to

physical memory

addresses

Paging via a Page Table


Example process P
i


requires 16 megabytes

of logical memory



Logical memory is

mapped via a page table

to a 32
-
megabyte

memory with pages

of size 4 megabytes


binary


0 ==> 000000


4 ==> 000100


8 ==> 001000

12 ==> 001100

16 ==> 010000

20 ==> 010100

24 ==> 011000

28 ==> 011100

Allocating a New Process

Address Translation Scheme


Every address generated by

the CPU is sliced into

two distinct parts:



Page number,
p

:

used as index to page table

to obtain base physical memory address



Page offset,
d

:

combined with base address

to identify the physical memory address

page number

page offset

p

d

Address Translation Scheme


Covers a logical address

space of size 2
m

with

page size 2
n


m
-

n

n

page number

page offset

p

d

Address Translation Scheme

Address Translation Scheme


The
page table

is typically kept in main memory


Every memory access request requires

two memory accesses:

1

2

Translation Look
-
Aside Buffer


Use page table
caching

at the hardware level

to speed address

translation



Hardware
-
level

translation

look
-
aside

buffer (TLB)


Effective Memory
-
Access Time


Given:


Memory access time is 100 nanoseconds


TLB access time is 20 nanoseconds


TLB hit ratio

is 80%



The
effective memory
-
access time

is


0.80
x

120 ns + 0.20
x

220 ns = 140 ns



What is the effective memory
-
access time

given a hit ratio of 99%? 50%?

Two
-
Level Page Tables


For large page tables, consider

multiple page table levels


Slice up the logical address

into multiple page indicators