Memory management units

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14 Δεκ 2013 (πριν από 3 χρόνια και 6 μήνες)

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CPUs

Memory management

Caches


The Memory System


Embedded systems and applications


The memory system requirements: vary
considerably


Simple blocks


Multiple types of memory


Caches


Write buffers


Virtual memory


Memory management units


Memory management unit (MMU) translates addresses:


Protection checks

CPU

main

memory

memory

management

unit

logical

address

physical

address

Memory management tasks


Allows programs to move in physical
memory during execution


Allows
virtual memory
:


memory images kept in secondary storage;


images returned to main memory on demand
during execution


Page fault
: request for location not resident
in memory

Address translation


Requires some sort of register/table to allow
arbitrary mappings of logical to physical
addresses


Two basic schemes:


segmented


paged


Segmentation and paging can be combined
(x86)

Segments and pages

memory

segment 1

segment 2

page 1

page 2

Segment address
translation

segment base address

logical address

range

check

physical address

+

range

error

segment lower bound

segment upper bound

Page address translation

page

offset

page

offset

page i base

concatenate

Page table organizations

flat

page descriptor

tree

page

descriptor

Caching address
translations


Large translation tables require main
memory access


TLB
: cache for address translation


Typically small

ARM Memory Management
Unit

ARM Memory Management


System control coprocessor(CP15)


Memory


Write Buffers


Caches


Registers


Up to 16 primary registers


Physical registers in CP15 more than 16


Register access instructions


MCR (ARM to CP15)


MRC (CP15 to ARM)

Cached MMU memory
system

ARM Memory Management


MMU can be enabled and disabled


Memory region types:


section: 1 Mbytes block


large page: 64 Kbytes


small page: 4 Kbytes


tiny Page: 1 Kbytes


Two
-
level translation scheme (why?)


First
-
level table


Second
-
level table

Page table size for 4
-
KB pages : 2
20

X 4
bytes = 4 MB

ARM address translation

offset

1st index

2nd index

physical address

Translation table

base register

1st level table

descriptor

2nd level table

descriptor

concatenate

First
-
level descriptors


AP: access permission


C,B: cachability and bufferability

Section descriptor and
translating section references

CP reg 2:

16 KB
boundary

4K Entries

1 MB block (section)

Max: 16KB

Coarse Page table
descriptor

4 K entries

Max: 16KB

256 entries

Max: 1KB

Fine page table descriptor

1 K entries

Max: 4 KB

Second
-
level descriptor

Translating large page
references

Access permissions


System (S) and ROM (R) in CP15 register 1

TLB functions


Invalidate instruction TLB


Invalidate instruction single entry


Invalidate entire data TLB


Invalidate data single entry



TLB lockdown

MPC 850 MMU

MPC850 MMU


Does not support some PowerPC MMU
features


4
-
, 16
-
, 512
-

Kbyte, or 8
-
Mbyte pages


1
-
KB subpages for 4
-
Kbyte pages


Separate instruction and data MMUs


Can be disabled separately


Supports up to 16 virtual address spaces


Supports 16 access protection groups



MPC 850 MMU, cont’d


Separate 8
-
entry, fully
-
associative data
translation lookaside buffer (DTLB) and
instruction TLB (ITLB)


High performance and low power
consumption


TLB locking, invalidation

Address Translation


Translation disabled


MSR[DR], MSR[IR]


Effective address = physical address


Translation enabled


TLB


SW handles the table lookup and TLB reload

with
little HW assistance in the MPC 850


MMU supports a multiple virtual address space


Address space ID (ASID)

Address Translation, cont’d

Not
implemented
in the DTLB

TLB operation

Current Address ID

Privilege level

8?

Translation Table (4 KB pages)

Translation Tables (1 KB pages)

Level
-
One descriptor

Level
-
Two Descriptor

1KB protection

4KB page HW
assist

4KB page

1KB subpage

Page Size

Programming Model

Programming Model (cont’d)

TLB operations


tlbia
: translation lookaside buffer invalidate
all


tlbie
: translation lookaside buffer invalidate
entry


Locking TLB entries

Locking TLB Entries

IMMU control register

(MI_CTR bit 4)

DMMU control register

(MD_CTR bit 4)

DTLB reload