Microcontroller 8051 - ICGST

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Ashraf

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Contact: (
)

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-
amc.com

editor@icgst.com

Tel.: 0020
-
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-
1804952

Fax.: 0020
-
2
-
24115475

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Introduction


CPU for Computers


No RAM, ROM, I/O on CPU chip itself


Example

Intel’s x86, Motorola’s 680x0

CPU

General
-
Purpose
Micro
-
processor

RAM

ROM

I/O
Port

Timer

Serial
COM
Port

Data Bus

Address Bus

General
-
Purpose Microprocessor System

Many chips on mother’s board

General
-
purpose microprocessor

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A smaller computer


On
-
chip RAM, ROM, I/O ports...


Example

Motorola’s
6811
, Intel’s
8051
, Zilog’s Z
8
and PIC
16
X


RAM


ROM

I/O
Port

Timer

Serial
COM
Port

Microcontroller

CPU

A single chip

Introduction

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Microprocessor



CPU is stand
-
alone, RAM,
ROM, I/O, timer are separate


designer can decide on the
amount of ROM, RAM and
I/O ports.


expansive


versatility


general
-
purpose


Microcontroller


CPU, RAM, ROM, I/O and
timer are all on a single chip


fix amount of on
-
chip ROM,
RAM, I/O ports


for applications in which cost,
power and space are critical


single
-
purpose

Microprocessor vs. Microcontroller

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Embedded system means the processor is
embedded

into

that
application.


An embedded product uses a microprocessor or
microcontroller to
do one task

only.


In an embedded system, there is only one application
software that is typically
burned into ROM
.


Example

printer, keyboard, video game player

Embedded System

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1.
meeting the computing needs of the task efficiently and cost
effectively


speed, the amount of ROM and RAM, the number of I/O
ports and timers, size, packaging, power consumption


easy to upgrade


cost per unit

2.
availability of software development tools


assemblers, debuggers, C compilers, emulator, simulator,
technical support

3.
wide availability and reliable sources of the
microcontrollers.

Three criteria in Choosing a
Microcontroller

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Block Diagram

CPU

On
-
chip
RAM

On
-
chip
ROM for
program
code

4
I/O Ports

Timer
0

Serial
Port

OSC

Interrupt
Control

External interrupts

Timer
1

Timer/Counter

Bus
Control

TxD RxD

P
0
P
1
P
2
P
3

Address/Data

Counter
Inputs

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Feature

8051 8052 8031

ROM (program space in bytes) 4K 8K 0K

RAM (bytes) 128 256 128

Timers 2 3 2

I/O pins 32 32 32

Serial port 1 1 1

Interrupt sources 6 8 6


Comparison of the
8051
Family
Members

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Pin Description of the
8051

PDIP/Cerdip

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

P
1.0

P
1.1

P
1.2

P
1.3

P
1.4

P
1.5

P
1.6

P
1.7

RST

(RXD)P
3.0

(TXD)P
3.1

(T
0
)P
3.4

(T
1
)P
3.5

XTAL
2

XTAL
1

GND

(INT
0
)P
3.2

(INT
1
)P
3.3

(RD)P
3.7

(WR)P
3.6

Vcc

P
0.0
(AD
0
)

P
0.1
(AD
1
)

P
0.2
(AD
2
)

P
0.3
(AD
3
)

P
0.4
(AD
4
)

P
0.5
(AD
5
)

P
0.6
(AD
6
)

P
0.7
(AD
7
)

EA/VPP

ALE/PROG

PSEN

P
2.7
(A
15
)

P
2.6
(A
14
)

P
2.5
(A
13
)

P
2.4
(A
12
)

P
2.3
(A
11
)

P
2.2
(A
10
)

P
2.1
(A
9
)

P
2.0
(A
8
)


8051

(
8031
)

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Vcc

pin
40
):

o
Vcc provides supply voltage to the chip.

o
The voltage source is +
5
V.


GND

pin
20
):
ground


XTAL
1
and XTAL
2

pins
19
,
18
):

o
These
2
pins provide external clock.

o
Way
1

using a quartz crystal oscillator


o
Way
2

using a TTL oscillator

o
Example
4
-
1
shows the relationship between XTAL and the
machine cycle.

Pin Description of the
8051

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RST

pin
9
):
reset

o
It is an input pin and is active high

normally low

.


The high pulse must be high at least
2
machine cycles.

o
It is a power
-
on reset.


Upon applying a high pulse to RST, the microcontroller will
reset and all values in registers will be lost.


Reset values of some
8051
registers

o
Way
1

Power
-
on reset circuit

o
Way
2

Power
-
on reset with debounce

Pin Description of the
8051

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/EA

pin
31
):
external access

o
There is no on
-
chip ROM in
8031
and
8032
.

o
The /EA pin is connected to GND to indicate the code is
stored externally.

o
/PSEN


ALE are used for external ROM.

o
For
8051
, /EA pin is connected to Vcc.

o
“/” means active low.


/PSEN

pin
29
):
program store enable

o
This is an output pin and is connected to the OE pin of the
ROM.

o
See Chapter
14
.

Pin Description of the
8051

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ALE

pin
30
):
address latch enable

o
It is an output pin and is active high.

o
8051
port
0
provides both address and data.

o
The ALE pin is used for de
-
multiplexing the address and
data by connecting to the G pin of the
74
LS
373
latch.


I/O port pins

o
The four ports P
0
, P
1
, P
2
, and P
3
.

o
Each port uses
8
pins.

o
All I/O pins are bi
-
directional.

Pin Description of the
8051

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XTAL Connection to
Microcontroller


Using a quartz crystal oscillator


We can observe the frequency on the
XTAL
2
pin.

C
2

30
pF

C
1

30
pF

XTAL
2

XTAL
1

GND

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XTAL Connection to an External
Clock Source





Using a TTL oscillator


XTAL
2
is unconnected.

N
C

EXTERNAL

OSCILLATOR

SIGNAL

XTAL
2

XTAL
1

GND

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Example : XTAL Connection

Find the machine cycle for

(a) XTAL =
11.0592
MHz

(b) XTAL =
16
MHz.


Solution:


(a)
11.0592
MHz /
12
=
921.6
kHz;


machine cycle =
1
/
921.6
kHz =
1.085

s

(b)
16
MHz /
12
=
1.333
MHz;


machine cycle =
1
/
1.333
MHz =
0.75

s

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RESET Value of Some
8051
Registers

0000

DPTR

0007

SP

0000

PSW

0000

B

0000

ACC

0000

PC

Reset Value

Register

RAM are all zero.

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Power
-
On RESET Circuit

30
pF

30
pF

8.2
K

10
uF

+

Vcc

11.0592
MHz

EA/VPP

X
1

X
2

RST

31

19

18

9

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Power
-
On
RESET with
Debounce

EA/VPP

X
1

X
2

RST

Vcc

10
uF

8.2
K

30
pF

9

31

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Pins of I/O Port


The
8051
has four I/O ports

o
Port
0

pins
32
-
39
):
P
0

P
0.0

P
0.7


o
Port
1

pins
1
-
8



P
1

P
1.0

P
1.7


o
Port
2

pins
21
-
28
):
P
2

P
2.0

P
2.7


o
Port
3

pins
10
-
17
):
P
3

P
3.0

P
3.7


o
Each port has
8
pins
.


Named P
0
.X

X=
0
,
1
,...,
7

, P
1
.X, P
2
.X, P
3
.X


Ex

P
0.0
is the bit
0

LSB

of P
0


Ex

P
0.7
is the bit
7

MSB

of P
0


These
8
bits form a byte.


Each port can be used as input or output (bi
-
direction).

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Registers

A

B

R
0

R
1

R
3

R
4

R
2

R
5

R
7

R
6

DPH

DPL

PC

DPTR

PC

Some
8051 16
-
bit Register

Some
8
-
bitt Registers of
the
8051

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Memory mapping in
8051



ROM memory map in
8051
family

0000
H

0
FFFH

0000
H

1
FFFH

0000
H

7
FFFH

8751

AT
89
C
51

8752

AT
89
C
52

4
k

DS
5000
-
32

8
k

32
k

from Atmel Corporation

from Dallas Semiconductor

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RAM memory space allocation in the
8051

7
FH

30
H

2
FH

20
H

1
FH

17
H

10
H

0
FH

07
H

08
H

18
H

00
H

Register Bank
0

(Stack) Register Bank
1

Register Bank
2

Register Bank
3

Bit
-
Addressable RAM

Scratch pad RAM

Memory mapping in
8051


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8051
Flag bits and the PSW register



PSW Register


CY

AC

F
0

RS
1

OV

RS
0

P

--

CY

PSW.
7


Carry flag

AC

PSW.
6


Auxiliary carry flag

--

PSW.
5


Available to the user for general purpose

RS
1

PSW.
4


Register Bank selector bit
1

RS
0

PSW.
3


Register Bank selector bit
0

OV

PSW.
2


Overflow flag

--

PSW.
1


User define bit

P

PSW.
0


Parity flag Set/Reset odd/even parity

RS
1

RS
0


Register Bank


Address

0


0



0





00
H
-
07
H

0


1



1





08
H
-
0
FH

1


0



2





10
H
-
17
H

1


1



3





18
H
-
1
FH

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Instructions that Affect Flag Bits

Note: X can be
0
or
1

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Addressing Modes


Immediate


Register


Direct


Register Indirect


Indexed

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Immediate Addressing Mode

MOV

A,#
65
H

MOV

A,#’A’

MOV

R
6
,#
65
H

MOV

DPTR,#
2343
H

MOV

P
1
,#
65
H


Example :



Num


EQU

30





MOV


R
0
,Num


MOV


DPTR,#data
1





ORG


100
H


data
1
:


db

“IRAN”

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Register Addressing Mode

MOV

Rn, A


;n=
0
,..,
7

ADD


A, Rn

MOV

DPL, R
6


MOV

DPTR, A

MOV

Rm, Rn

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Direct Addressing Mode


Although the entire of
128
bytes of RAM can be accessed using
direct addressing mode, it is most often used to access RAM loc.
30


7
FH.


MOV

R
0
,
40
H

MOV

56
H,

A

MOV

A,
4


; ≡ MOV A, R
4

MOV

6
,
2


; copy R
2
to R
6





;
MOV R
6
,R
2
is invalid !


SFR register and their address


MOV

0
E
0
H, #
66
H

; ≡ MOV A,#
66
H

MOV

0
F
0
H, R
2

; ≡ MOV B, R
2

MOV

80
H,A


; ≡ MOV P
1
,A



Bit Addressable


Page
359
,
360

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Register Indirect Addressing Mode


In this mode, register is used as a pointer to the data.


MOV


A,@Ri

; move content of RAM loc.Where address is held by Ri into A





( i=
0
or
1
)

MOV


@R
1
,B



In other word, the content of register R
0
or R
1
is sources or target in MOV, ADD and SUBB
insructions.

Example:


Write a program to copy a block of
10
bytes from RAM location sterting at
37
h to RAM
location starting at
59
h.


Solution:


MOV R
0
,
37
h


; source pointer


MOV R
1
,
59
h


; dest pointer


MOV R
2
,
10


; counter


L
1
: MOV A,@R
0


MOV @R
1
,A


INC R
0


INC R
1


DJNZ R
2
,L
1

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Indexed Addressing Mode And
On
-
Chip ROM Access


This mode is widely used in accessing data
elements of look
-
up table entries located in the
program (code) space ROM at the
8051


MOVC

A,@A+DPTR

A= content of address A +DPTR from ROM

Note:


Because the data elements are stored in the
program (code ) space ROM of the
8051
, it uses
the instruction MOVC instead of MOV. The
“C” means code.


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Stack in the
8051


The register used to access
the stack is called
SP
(stack
pointer) register.



The stack pointer in the
8051
is only
8
bits wide,
which means that it can take
value
00
to FFH.
When
8051
powered up, the SP
register contains value
07
.

7
FH

30
H

2
FH

20
H

1
FH

17
H

10
H

0
FH

07
H

08
H

18
H

00
H

Register Bank
0

(Stack) Register Bank
1

Register Bank
2

Register Bank
3

Bit
-
Addressable RAM

Scratch pad RAM

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MOV

R
6
,#
25
H


MOV

R
1
,#
12
H


MOV

R
4
,#
0
F
3
H


PUSH

6


PUSH

1


PUSH

4


0
BH

0
AH

09
H

08
H

Start SP=
07
H

25

0
BH

0
AH

09
H

08
H

SP=
08
H

F
3

12

25

0
BH

0
AH

09
H

08
H

SP=
08
H

12

25

0
BH

0
AH

09
H

08
H

SP=
09
H

Example

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I/O Port Programming


Port
1
is denoted by P
1
.

o
P
1.0
~ P
1.7


We use P
1
as examples to show the operations on ports.

o
P
1
as an output port (i.e., write CPU data to the external pin)

o
P
1
as an input port (i.e., read pin data into CPU bus)

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A Pin of Port
1

8051
IC

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU
bus

M
1

P
1
.X
pin

P
1
.X

TB
1

TB
2

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Hardware Structure of I/O Pin


Each pin of I/O ports

o
Internal CPU bus

communicate with CPU

o
A D latch store the value of this pin


D latch is controlled by “Write to latch”


Write to latch

1

write data into the D latch

o
2
Tri
-
state buffer



TB
1
: controlled by “Read pin”


Read pin

1

really read the data present at the pin


TB
2
: controlled by “Read latch”


Read latch

1

read value from internal latch

o
A transistor M
1
gate


Gate=
0
: open


Gate=
1
: close

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Tri
-
state Buffer

Output

Input

Tri
-
state control
(active high)

L

H

Low

Highimpedance
(open
-
circuit)

H

H

L

H

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Writing “
1
” to Output Pin P
1
.X

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU
bus

M
1

P
1
.X
pin

P
1
.X

8051
IC

2
. output pin is
Vcc

1
. write a
1
to the pin

1

0

output
1

TB
1

TB
2

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Writing “
0
” to Output Pin P
1
.X

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU
bus

M
1

P
1
.X
pin

P
1
.X

8051
IC

2
. output pin is
ground

1
. write a
0
to the pin

0

1

output
0

TB
1

TB
2

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Port
1
as Output

Wri瑥 瑯 a Port



Send data to Port
1







MOV

A,#
55
H

BACK:


MOV

P
1
,A




ACALL

DELAY




CPL A




SJMP BACK


o
Let P
1
toggle.

o
You can write to P
1
directly.

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Reading Input
v.s
. Port Latch


When reading ports, there are two possibilities


o
Read the status of the input pin.

from
external pin value



MOV A, PX


JNB P
2.1
, TARGET ; jump if P
2.1
is not set


JB P
2.1
, TARGET ; jump if P
2.1
is set


Figures C
-
11
, C
-
12

o
Read the

internal latch
of the output port.


ANL P
1
, A ; P
1
← P
1
AND A


ORL P
1
, A ; P
1
← P
1
OR A


INC P
1
; increase P
1


Figure C
-
17


Table C
-
6
Read
-
Modify
-
Write Instruction (or Table
8
-
5
)


See Section
8.3

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Reading “High” at Input Pin

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU bus

M
1

P
1
.X pin

P
1
.X

8051
IC

2
. MOV A,P
1

external pin=High

1.
write a
1
to the pin MOV
P
1
,#
0
FFH

1

0

3
. Read pin=
1
Read latch=
0
Write to latch=
1

1

TB
1

TB
2

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Reading “Low” at Input Pin

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU bus

M
1

P
1
.X pin

P
1
.X

8051
IC

2
. MOV A,P
1

external pin=Low

1.
write a
1
to the pin

MOV P
1
,#
0
FFH

1

0

3
. Read pin=
1
Read latch=
0
Write to latch=
1

0

TB
1

TB
2

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Port
1
as Input

Read 晲om 偯rt



In order to make P
1
an input, the port must be programmed by
writing
1
to all the bit.





MOV

A,#
0
FFH

;A=
11111111
B




MOV

P
1
,A


;make P
1
an input port

BACK:

MOV A,P
1


;get data from P
0




MOV P
2
,A


;send data to P
2




SJMP BACK


o
To be an input port, P
0
, P
1
, P
2
and P
3
have similar methods.

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Instructions For Reading an Input
Port

Mnemonics

Examples

Description

MOV A,PX

MOV A,P2

Bring into A the data at P2
pins

JNB PX.Y,..

JNB P2.1,TARGET

Jump if pin P2.1 is low

JB PX.Y,..

JB P1.3,TARGET

Jump if pin P1.3 is high

MOV C,PX.Y

MOV C,P2.4

Copy status of pin P2.4 to CY


Following are instructions for reading external pins of ports:

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Reading Latch


Exclusive
-
or the Port
1


MOV P
1
,#
55
H ;P
1
=
01010101

ORL P
1
,#
0
F
0
H ;P
1
=
11110101


1
. The
read

latch activates TB
2
and bring the data from the Q latch
into CPU.


Read P
1.0
=
0

2
. CPU performs an operation.


This data is ORed with bit
1
of register A. Get
1
.

3
. The latch is
modified
.


D latch of P
1.0
has value
1
.

4
. The result is
written

to the external pin.


External pin (pin
1
: P
1.0
) has value
1
.

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Reading the Latch

D

Q


Clk

Q

Vcc


Load(L
1
)

Read latch

Read pin

Write to latch

Internal CPU bus

M
1

P
1
.X pin

P
1
.X

8051
IC

4
. P
1
.X=
1

2
. CPU compute P
1
.X OR
1

0

0

1
. Read pin=
0
Read latch=
1
Write to
latch=
0
(Assume P
1
.X=
0
initially)

1

TB
1

TB
2

3
. write result to latch Read
pin=
0
Read latch=
0
Write to latch=
1

1

0

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Read
-
modify
-
write Feature


Read
-
modify
-
write Instructions

o
Table C
-
6


This features combines
3
actions in a single
instruction


1
. CPU reads the latch of the port

2
. CPU perform the operation

3
. Modifying the latch

4
. Writing to the pin

o
Note that
8
pins of P
1
work independently.

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Port
1
as Input

Read 晲om la瑣h



Exclusive
-
or the Port
1






MOV P
1
,#
55
H ;P
1
=
01010101

AGAIN:

XOR P
1
,#
0
FFH ;complement




ACALL DELAY




SJMP AGAIN


o
Note that the XOR of
55
H and FFH gives AAH.

o
XOR of AAH and FFH gives
55
H.

o
The instruction read the data in the latch (not from the pin).

o
The instruction result will put into the latch and the pin.

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A Pin of Port
0

8051
IC

D

Q


Clk

Q

Read latch

Read pin

Write to latch

Internal CPU
bus

M
1

P
0
.X
pin

P
1
.X

TB
1

TB
2

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Port
0

pins

-




P
0
is an open drain.

o
Open drain is a term used for MOS chips in the same
way that open collector is used for TTL chips.


When P
0
is used for simple data I/O we must connect it
to external pull
-
up resistors.

o
Each pin of P
0
must be connected externally to a
10
K
ohm pull
-
up resistor.

o
With external pull
-
up resistors connected upon reset,
port
0
is configured as an output port.

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Port
0
with Pull
-
Up Resistors

P
0.0

P
0.1

P
0.2

P
0.3

P
0.4

P
0.5

P
0.6

P
0.7

DS
5000

8751

8951

Vcc

10
K

Port
0

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Dual Role of Port
0


When connecting an
8051
/
8031
to an external memory, the
8051
uses ports to send addresses and read instructions.

o
8031
is capable of accessing
64
K bytes of external memory.

o
16
-
bit address

P
0
provides both address A
0
-
A
7
, P
2
provides address A
8
-
A
15
.

o
Also, P
0
provides data lines D
0
-
D
7
.


When P
0
is used for address/data multiplexing, it is
connected to the
74
LS
373
to latch the address.

o
There is no need for external pull
-
up resistors as shown in
Chapter
14
.

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74
LS
373

D

74
LS
373

ALE

P
0.0

P
0.7

PSEN

A
0

A
7

D
0

D
7

P
2.0


P
2.7

A
8

A
15

OE

OC

EA

G

8051

ROM

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Reading ROM (
1
/
2
)

D

74
LS
373

ALE

P
0.0

P
0.7

PSEN

A
0

A
7

D
0

D
7

P
2.0


P
2.7

A
8

A
12

OE

OC

EA

G

8051

ROM

1
. Send address to
ROM

2
.
74373
latches the
address and send to
ROM

Address

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Reading ROM (
2
/
2
)

D

74
LS
373

ALE

P
0.0

P
0.7

PSEN

A
0

A
7

D
0

D
7

P
2.0


P
2.7

A
8

A
12

OE

OC

EA

G

8051

ROM

2
.
74373
latches the
address and send to
ROM

Address

3
. ROM send the
instruction back

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ALE Pin


The ALE pin is used for de
-
multiplexing the
address and data by connecting to the G pin of
the
74
LS
373
latch.

o
When ALE=
0
, P
0
provides data D
0
-
D
7
.

o
When ALE=
1
, P
0
provides address A
0
-
A
7
.

o
The reason is to allow P
0
to multiplex address and
data.

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Port
2

pins

-




Port
2
does not need any pull
-
up resistors since
it already has pull
-
up resistors internally.


In an
8031
-
based system, P
2
are used to provide
address A
8
-
A
15
.

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Port
3

pins

-




Port
3
does not need any pull
-
up resistors since it already
has pull
-
up resistors internally.


Although port
3
is configured as an output port upon reset,
this is not the way it is most commonly used.


Port
3
has the additional function of providing signals.

o
Serial communications signal

RxD, TxD

Chapter
10


o
External interrupt

/INT
0
, /INT
1

Chapter
11


o
Timer/counter

T
0
, T
1

Chapter
9


o
External memory accesses in
8031
-
based system

/WR,
/RD

Chapter
14


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Port
3
Alternate Functions

17

RD

P
3.7

16

WR

P
3.6

15

T
1

P
3.5

14

T
0

P
3.4

13

INT
1

P
3.3

12

INT
0

P
3.2

11

TxD

P
3.1

10

RxD

P
3.0

Pin

Function

P
3
Bit

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