EE Graduate Seminar, Track 1 Friday, November 19, 2010 Room ...

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EE Graduate Seminar
, Track 1

Friday, November 19, 2010

Room E345

10:30 to 18:40


MSEE Project Presentation



Title
:
“Design of a 0.85V On
-
chip Analog Front
-
end for Ultrasound Signals in 45nm CMOS
Process Technology”


Presenter:

Arun Kumar Vikram
Karthikeyan, Melvin Thomas

Time:

10:30
-
10:55 AM

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Th i s p a p e r p r e s e nt s a s i n g l e
-
c h i p r e a l i z a t i o n o f a n a na l o g f r o nt
-
e nd c i r c u i t fo r p o r t a b l e
u l t r a s o u nd me d i c a l s ys t e ms. The d e s i g n e d s y s t e m o p e r a t e s a t f r e q ue nc i e s b e t we e n 5 MHz a nd
1 0 MHz us e d f o r s t u d y i n g r e g i o ns ne a r e r t o b o d y s ur fa c e. The f r o n t
-
e nd I C c o ns
i s t s o f a Lo w
No i s e Amp l i f i e r ( LNA), Va r i a b l e Ga i n Amp l i f i e r ( VGA) a nd a Lo w P a s s F i l t e r ( LP F ). Lo w
No i s e
-

Cho p p e r S t a b i l i z e d a mp l i f i e r wi t h o f fs e t c o mp e ns a t i o n wa s d e s i g ne d wi t h <3 6 n V i np ut
r e fe r r e d no i s e a nd 2 4 d B ga i n a t 1 0 MHz f r e q ue nc y. A f u l l y d i f f e r e
nt i a l s i g na l i n g i s us e d i n o r d e r
t o r e d uc e e ve n o r d e r ha r mo n i c s a nd c o mmo n mo d e no i s e. The Ti me Ga i n Co mp e ns a t i o n ( TGA)
c i r c u i t r y i s r e a l i z e d us i n g a d i g i t a l l y c o nt r o l l e d Va r i a b l e Ga i n Amp l i f i e r wh i c h e x h i b i t s l i n e a r
-
in
-
dB gain variation with a range of +
17dB to +44dB. A second order active low pass filter is
designed to realize the anti
-
aliasing function. A high
-
gain, fast settling cmos operational
amplifier suitable for low supply voltages was designed in order to implement the active filter
circuit. The

trade
-
offs involved in selecting the sampling frequency and the filter order and its
impact on the amplifier specifications are considered and reported. The entire circuitry is built in
45nm CMOS process technology with a low supply voltage of 0.85V.



Ti
tle
:
“Sigma Delta Modulator”


Presenter:

Tanjit Singh Gill, Rupinder
Singh Mand

Time:

10:55
-
11:20 AM

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Mo d e l i n g o f S i g ma
-
De l t a mo d u l a t o r wa s d o ne i n Ma t l a b

t o u nd e r s t a nd t he s ys t e m
l e ve l wo r k i n g a nd t o e xt r a c t va r i o us p a r a me t e r s fo r f u nd a me n t a l b l o c k s. Th e s i g ma d e l t a
mo d u l a t o r c o mp r i s e d o f a d i g i t a l f i l t e r a nd a mo d u l a t o r. The mo d u l a t o r wh i c h i s a l s o a no i s e
f i l t e r wi l l s h a p e s t h e no i s e a wa y a nd i nt o h i g h f
r e q ue nc y. Th i s no i s e c o nt a i n s t h e ma j o r i t y o f
i nb a nd no i s e f r o m t h e c i r c u i t. Va l ue s o f no n
-
i d e a l i t i e s a r e e xt r a c t e d f r o m t he c i r c u i t d e s i g n o f
f u nd a me nt a l b l o c k s a nd a d d e d t o t he S i mu l i n k mo d e l. S e c o nd o r d e r Mo d u l a t o r i s mo d e l e d a nd
simulated in Simulink a
nd circuit design of Biasing circuit, Amplifier, Switched capacitor
circuits and integrator was done in TSMC 180nm technology.



Title
:
“A Low Power, Low Noise Mixed
-
signal PLL with Differential Input Charge pump”


Presenter:

Yixiu Chai

Time:

11
:
20
-
11:45

AM

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
P ha s e
-
Lo c k e d Lo o p i s t he c r i t i c a l b l o c k i n t he e l e c t r i c a l s y s t e m t o ge ne r a t e c l o c k,
d i s t r i b ut e c l o c k a nd s y nc hr o n i z e c l o c k. I f a l o w p o we r, l o w no i s e P LL c a n b e i mp l e me n t e d, mo s t
o f t he e l e c t r i c a l s ys t e ms c a n b e ne f i t f r o m i t t o a c h i e ve b e t t e r p e r f o r ma n c e a
nd l e s s p o we r
c o ns u mp t i o n. I n t h i s p r o j e c t, t he a ut ho r wo u l d g i v e t he ma t h e ma t i c s mo d e l o f a P LL i n d e t a i l s,
a nd d e s i g n a l o w p o we r, l o w no i s e P LL us i n g d i f f e r e nt i a l i n p ut c ha r ge p u mp. And a h i g h l y
l i n e a r i t y VCO i s i mp l e me n t e d t o o. Kvc o i s a r o u nd 4 0 Mh z/V;
t he b a nd wi d t h i s l e s s t ha n 1 Mz h,
t uni n g r a nge i s b e t we e n 1.0 0 8 GHz a nd 1.0 4 8 GHz.



Ti t l e
:
“Programmable Transconductance

C cell filters for Low Power System on Chip
Applications and Field programmable Analog Arrays”


Presenter:

Vishal Surakanti

Time:

11:
45
-
12:10

P
M

Advisor:

P r o f. S o t o ud e h Ha me d i
-
Ha gh

Co
-
Advisor:

-



Abs t ra c t:
Co mmu n i c a t i o n a nd Lo g i c S ys t e ms a r e b e c o mi n g mo r e c o mp l e x d a y b y d a y, c i r c u i t s
wh i c h c a n o p e r a t e a t h i g h f r e q ue nc i e s a nd wi d e r r a n ge o f b a nd wi d t h ha v e b e c o me a ne c e s s i t y
.Co nt i n u
o us t i me F i l t e r s a r e t u na b l e fr o m f e w K i l o h e r t z t o Gi ga h e r t z r a n ge o f fr e q ue n c i e s.
Co nt i n u o us t i me f i l t e r s wi t h p r o gr a mma b l e a r c h i t e c t u r e p r o v i d e c a n p r o v i d e mo r e f l e x i b i l i t y t o
d e s i g n wi d e b a nd wi d t h c o mmu n i c a t i o ns s ys t e ms. Co nt i n u o us t i me f i l t e r s ha ve p o t
e nt i a l
a p p l i c a t i o ns i n S ys t e m o f C h i p s a r c h i t e c t u r e s ( S o C) wh i c h wi l l b e us e d mu l t i me d i a d e v i c e s a nd
c o mmun i c a t i o ns ga d ge t s.


S o C

us e d Co mmu n i c a t i o n s y s t e ms a r e d e s i g n e d fo r va r i o u s wi r e l i ne a nd wi r e l e s s
c o mmu n i c a t i o ns s t a nd a r d s s uc h a s 8 0 2.1 1 g/n, Et he r ne t, GP RS, Ed ge, a nd Bl u e t o o t h. The s e
s t a nd a r d s o p e r a t e i n d i f f e r e nt fr e q ue nc y s p e c t r u ms a nd ha ve d i f f e r e n t b a nd wi d t h r e q u i r e me nt s
.
Programmable Continuous filters can be used digitally changing the Filters characteristics of the
filters.

Goal of this project was add programmable feature to Low power High frequency
continuous time filters. Working on this project I was able to desi
gn an 8 bit digitally controlled
Wide band Transconductance cell. Transconductance cell is designed to select
Transconductance values from 80u/A to 1.6m/A (20:1) and can be operated over the frequency
of 100 KHz to 500Mhz. 2nd order, 6th order Biquad filt
er, 1st order integrator, 2nd order
Butterworth Filters were designed. Power Consumption varies from 600uW to 1.5mW.


Title
:
“PROGRAMMABLE SYSTEM ON CHIP”


Presenter:

Anuj Chaudhary

Time:

12
:
20
-
12:45

P
M

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

-



Abs t ra c t:
The p r o gr a mma b l e s ys t e m o n c h i p ( P S o C
) i n t r o d uc e s t he a s p e c t s o f p r o gr a mma b i l i t y
a nd r e
-
c o n f i g u r a b i l i t y i n t he d e s i g n o f a na l o g a nd r a d i o f r e q ue nc y s ys t e ms. The P r o g r a mma b l e
S ys t e m o n C h i p e na b l e s t h e i n t e gr a t i o n o f c o mp l e x f u n c t i o na l i t i e s, us i n g c o n f i g u r a b l e a na l o g
b l o c k s, a t a f a s t e r p a c e a
nd i n s ho r t e r d e s i g n c yc l e s a s c o mp a r e d t o t he i mp l e me n t a t i o n us i n g
c o n ve n t i o na l d e s i g n me t ho d o l o g i e s. Th i s p r o j e c t i n c o r p o r a t e s t he d e s i g n o f a r a d i o f r e q ue nc y
f r o nt e nd, wh i c h c o mp r i s e s o f t he Lo w No i s e Amp l i f i e r, Mi xe r a nd LC t a nk Os c i l l a t o r, c a p a b l e
o f

o p e r a t i n g a t d i f f e r e n t i np u t fr e q u e nc i e s. The i nt e r me d i a t e fr e q ue n c y o ut p u t i s s up p l i e d t o a
f u l l y p r o gr a mma b l e a na l o g f i l t e r b l o c k t ha t i nc l u d e s t he Lo w p a s s f i l t e r, Hi g h p a s s f i l t e r, Ba nd
p a s s f i l t e r a nd Ba nd r e j e c t f i l t e r. The i n p ut a nd o u t p ut f r e q ue nc
y o f t he P S o C c a n b e
p r o g r a mme d a nd t a i l o r e d b y t he d e s i g n e r b a s e d o n t he d e s i g n go a l. The P S o C f r e q ue nc y o f
o p e r a t i o n c a n b e mo d i f i e d a t d i f f e r e n t s t a ge s t ha t i n t r o d uc e s t he fe a t ur e s o f c o n f i g u r a b i l i t y a t
e ve r y s t a ge.



Ti t l e
:
“Variable Gain Amplifier
with Power Management”


Presenter:

Naman Barmecha

Time:

12
:
45
-
01:10

P
M

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Th i s p a p e r d e s c r i b e s a mo d u l a r d e s i g n o f a Va r i a b l e Ga i n Amp l i f i e r wi t h p o we r
ma na ge me n t. The p r o j e c t ha s d i f f e r e nt ga i n c o nt r o l a nd a mp l i f i e r mo d u l e s wh i c h c a n b e
i n t e r c h a n ge d a nd us e d a t t he r e c e i ve r a s we l l a s t r a ns mi t t e r wi t h c o a r s e a nd f i ne t u n i n g o f
t he
ga i n. Al o n g wi t h t he ga i n c o nt r o l a p o we r ma na g e me n t s c he me i s a l s o i mp l e me nt e d. The
d e s c r i b e d wo r k i n c r e a s e s t he e f f i c i e nc y o f RF e q u i p me n t s b y i n c r e a s i n g t he b a t t e r y l i f e a nd
e nha nc i n g us e r e xp e r i e nc e.

A f i xe d ga i n s t a g e o f 3 0 d B wi t h no i s e f i g u r e o f

1.6 d B wi t h p o we r d i s s i p a t i o n o f 6 5 0 uW i s
d e s i g ne d. The a t t e n ua t o r s t a ge a c t s a s t he ga i n c o n t r o l s t a ge. The a t t e n ua t o r s t a ge p r o v i d e s a ga i n
va r i a t i o n o f
-
1 0 d B t o 1.7 8 d B. The f i x e d ga i n s t a g e a l o n g wi t h t he va r i a b l e a t t e n ua t o r s t a g e s a r e
c a s c a d e d t o p r o v i
d e a d y na mi c r a n g e o f 6 0 d B f o r ga i n c o nt r o l. The p o we r ma na ge me nt s c he me
he l p s t o r e d uc e p o we r c o ns ump t i o n b y s wi t c hi n g t he mo d ul e s o ff whe n no t r e q ui r e d.

A fe e d b a c k l o o p i s d e s i g n e d t o l i n e a r i z e t he ga i n c o nt r o l us i n g a p e a k d e t e c t o r, b i a s c o n t r o l a nd
c o m
p a r a t o r.



Ti t l e
:
“RF Receiver front end LNA operating at 2.4 GHz for wireless sensor networks using
CMOS 90nm technology”


Presenter:

Gaganpreet Singh

Time:

0
1:
10
-
01:35

P
M

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Th i s p a p e r p r e s e nt s a s t e p wi s e d e s i g n a p p r o a c h t o a Lo w No i s e Amp l i f i e r wi t h l o w
p o we r a nd e xc e l l e n t i np u t a nd o ut p u t i mp e d a nc e ma t c h i n g us i n g r e a l l i f e i n d uc t o r s. The p r o j e c t
ha s b e e n i mp l e me nt e d us i n g CMOS 9 0 n m t e c h no l o g y f o l l o we d b y a c o mp l e t
e c i r c u i t l a yo ut. An
LNA d e s i g n c a n b e p e r fo r me d us i n g s e ve r a l d i f f e r e n t t o p o l o g i e s s uc h a s r e s i s t i v e t e r mi n a t i o n,
c o mmo n ga t e c o n f i g u r a t i o n e t c. b u t a l l t he s e t o p o l o g i e s ha ve p o o r ga i n a nd no i s e f i g u r e. Ano t he r
ve r y p o p u l a r t o p o l o g y wh i c h i s c a l l e d S o u r c e

De ge ne r a t i o n ha s b e e n us e d wh i c h p r o v i d e d a l o t
b e t t e r i np u t a nd o ut p u t ma t c h i n g, a b e t t e r ga i n, l e s s e r no i s e f i g u r e a nd ve r y l e s s p o we r
c o ns u mp t i o n. The d e s i g ne d c i r c u i t p r o v i d e s g r e a t e r b a t t e r y l i f e a nd ve r y go o d i mp e d a nc e
ma t c h i n g a nd i s b e s t s u i t e d fo
r na r r o wb a nd o p e r a t i o ns i n v a r i o u s wi r e l e s s s e ns o r ne t wo r k
a p p l i c a t i o ns.

The d e s i g ne d LNA c i r c u i t ha s a ga i n va l u e o f g r e a t e r t ha n 1 3 d B wi t h t he i np ut p o r t vo l t a ge
r e f l e c t i o n c o e f f i c i e n t S 1 1 gr e a t e r t ha n
-
5 3 d B, o ut p u t p o r t r e f l e c t i o n c o e f f i c i e nt S 2 2 g r e a t e
r t ha n
-
4 6 d B, a r e ve r s e i s o l a t i o n p a r a me t e r S 1 2 g r e a t e r t ha n
-
2 9 d B a nd a no i s e f i g u r e l e s s t ha n 3 d B. A
ve r y l o w p o we r a r o u nd 1.7 mW i s b e i n g us e d b y t he c i r c u i t wh i c h ha s b e e n i mp l e me nt e d us i n g
r e a l i nd uc t o r s. Al l t he s e va l ue s ha ve b e e n a c hi e ve d a t a n o p e r
a t i ng fr e q ue nc y o f 2.4 GHz.



Ti t l e
:
“DESIGN OF AN ULTRA WIDEBAND LOW NOISE AMPLIFIER”


Presenter:

Bhargav Pandya

Time:

01
:
35
-
02:00

P
M

Advisor:

P r o f. S o t o ud e h Ha me d i Ha gh

Co
-
Advisor:

-



Abs t ra c t:
I n t h i s p r o j e c t, a me t ho d ha s b e e n d e s c r i b e d t o a c h i e ve d e s i g n o f a n Ul t r a wi d e b a nd
Lo w No i s e Amp l i f i e r i n gp d k 0 9 0 CMOS t e c h no l o g y u s i n g Ca d e n c e De s i g n t o o l s. GP DK0 9 0
t e c h no l o g y ha s b e e n c ho s e n t o a c h i e ve i mp e d a n c e ma t c h i n g wi t h r e a l i nd uc t o r s a nd r e a l
cap
acitors instead of conventional ideal passive components from any analog library in Cadence.
Low Noise Amplifier proposed here is designed using Frequency Multiplication concept. Instead
of designing a wideband matching, a method has shown to increase the
bandwidth of the
transistor by employing more than one transistor in parallel in the design as you will see as you
will go through. The design is valid for 3
-
10GHz and Noise Figure has been managed below 5dB
for the entire bandwidth at power dissipation of

just 11.6mW. Gain of the amplifier is very high,
ranges from 30
-
40dB for the entire bandwidth. The input and output matching networks are
provided and <
-
11dB matching have been achieved at both ports. Linearity of the system is
relatively high with proper

design such that the 1
-
dB compression point has been achieved at
-
7dBm. The design has been simulated using Cadence Schematic Capture tools and run with
Spectre Simulator to figure out behavior of various components of the design. Various analysis
have be
en performed on the design like AC analysis to find AC gain of the amplifier, Transient
analysis to find the transient power dissipation, S
-
parameter analysis to find input
-
output
matching and calculating Noise Figure and PSS analysis to obtain linearity o
f the design. The
layouts have been performed using Cadence Virtuoso Layout Editor Tool.



Title
:
“On
-
chip Stimulus generators for Analog
-
to
-
Digital Converter BIST”


Presenter:

Long Long

Time:

02
:
1
0
-
02:
3
5

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Wi t h i nc r e a s i n g c o mp l e x i t y o f i n t e gr a t e d c i r c u i t s ( I Cs ), t he c o s t a nd t i me o f va l i d a t i n g
I Cs ’ f u nc t i o n b y us i n g t r a d i t i o n a l a u t o ma t i c t e s t e q u i p me n t ( ATE) wo u l d r i s e c o r r e s p o nd i n g l y
wh i c h c o u l d b e o ne o f t he mo s t e xp e n s i ve i t e ms i n I C’ s ma n u f a c t u r e t e s t i n g
. The r e f o r e a c o s t
a nd t i me s a v i n g me t ho d fo r I Cs f u nc t i o na l t e s t i n g i s a c r i t i c a l i s s ue i n I C t e s t i n g f i e l d. Bu i l d
-
I n
S e l f
-
Te s t ( BI S T) o n l y r e l i e s i n t e r na l o n
-
c h i p b l o c k s fo r t e s t i n g c h i p f u n c t i o n, d o e s no t ne e d a n y
o t h e r e xp e ns i ve e q u i p me n t s wh i c h wo u l d
s i g n i f i c a nt l y r e d uc e t e s t i n g c o s t a nd s ho r t e n i n g t e s t i n g
t i me. On t he o t he r ha nd, s i nc e no r ma l l y t he r e i s no o u t s i d e c o n ne c t i o n fo r a na l o g/mi x e d s i g n a l
c i r c u i t s i n S OC, i t i s h a r d t o t e s t i t s f u nc t i o n b y us i n g e xt e r n a l e q u i p me n t. S o me a nwh i l e BI S T i s
a l s o
a ve r y p r o mi s i n g t e c hni q ue t o b e i mp l e me n t e d fo r t e s t i ng S OC.

Th i s p r o j e c t i s fo c us e d o n BI S T s c he me. As t he mo s t c o mmo n us e d s c he me, Hi s t o gr a m BI S T
wo u l d b e s t ud i e d a nd d i s c us s e d. Mo r e o ve r, a s a n i mp o r t a n t f u nc t i o na l b l o c k t o e ns u r e t he
a c c u r a c y o f h i s t o g
r a m BI S T, a n o n
-
c h i p t r i a n g l e s t i mu l u s g e ne r a t o r u s i n g TS MC .1 8 u m
t e c h n i q ue i s p r o p o s e d. Ar c h i t e c t ur e i s a d a p t i v e t o a vo i d t he i n f l u e nc e o f p r o c e s s va r i a t i o n i n o n
-
c hi p s t i mu l us ge ne r a t o r.




Ti t l e
:
“Mixed architecture of Carry Look Ahead and Carry Select
adder for High speed


Low Power adder”


Presenter:

Suyash Kelkar

Time:

02
:
35
-
03:00

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
The a i m o f t h e p r o j e c t i s t o b u i l d a 3 2 b i t a d d e r wi t h a mi x e d a p p r o a c h o f Ca r r y Lo o k
-

a he a d a nd Ca r r y S e l e c t. Ca r r y Lo o k Ahe a d ( C LA) b l o c k wi l l g r o up a l l t he b i t s i n t o ge ne r a t e a nd
p r o p a g a t e s a nd t he n i n t o b l o c k c a r r i e s wh i l e Ca r r y S e l e c t ( CS A) a p p r o a c h w
i l l b e us e d t o
ge ne r a t e t he p a r t i a l s u m a s s u mi n g b o t h c a r r y i np u t s ( 0 a nd 1 ). The b l o c k c a r r y ge ne r a t e d i n C LA
t h e n wi l l b e us e d a s s e l e c t l i n e t o s e l e c t t he a p p r o p r i a t e o u t p ut o f CS A. Mi x i n g t wo a r c h i t e c t ur e s
o f a d d e r wi l l r e d uc e t he o ve r a l l l o g i c r e q u i r e
d t o ge t t he s u m a nd wi l l s i g n i f i c a nt l y i mp r o ve t he
l a t e nc y o f a n a d d e r b y e ffe c t i ve ut i l i za t i o n o f p a r a l l e l i s m o f t wo a d d e r a p p r o a c he s.

Lo w Vo l t a g e S c he me t e c h n i q u e ( LVS ), wh i c h i s c u r r e n t l y us e d i n I nt e l p r o c e s s o r s, i s us e d fo r
t h e i mp l e me nt a t i o n. LVS i
mp l e me nt a t i o n c o mp r i s e o f S e ns e Amp l i f i e r ( S A), Di f f u s i o n
Co n ne c t e d Ne t wo r k ( C DN) a nd Cr o s s Co up l e d Do mi n o Lo g i c ( CDL). Th i s t e c h n i q u e i s us e d t o
r e d uc e t he o ve r a l l p o we r c o ns ump t i o n o f a n a d d e r.

S o t h i s mi x e d a r c h i t e c t u r e wi t h LVS wi l l i mp r o ve t he o ve r a l l

p e r fo r ma nc e o f a d d e r i n t e r ms o f
s p e e d, p o we r a nd l a t e nc y.



Title
:
“Phase Noise Reduction in Phase Locked Loops using Asynchronous Logic Model”


Presenter:

Kirthi Kumar Devleker

Time:

03
:
00
-
03:25

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
P ha s e No i s e i n P ha s e Lo c k e d Lo o p s i s a ve r y c r i t i c a l me t r i c wh i c h d e f i n e s t he o ve r a l l
q ua l i t y o f t he P ha s e Lo c k e d Lo o p. Ma n y e l e c t r i c a l d e s i g n e n g i ne e r s a i m a t r e d uc i n g a t t he P ha s e
No i s e a s no i s e i s c o ns i d e r e d t o b e a n u nwa n t e d s i g n a l. Th e e f fe c t o f P ha s
e no i s e i s mo r e
p r o no unc e d a t Hi ghe r F r e q ue nc i e s.

I n t h i s p r o j e c t a P h a s e Lo c k e d Lo o p i s d e s i g n e d t o l o c k a t 1 GHz. The f r e q ue nc y o f t he r e f e r e nc e
i np u t t o t he P ha s e Lo c k e d Lo o p i s 1 0 MHz. De s i g n o f t he P ha s e Lo c k e d Lo o p i n c l ud e s d e s i g n
o f P ha s e F r e q ue nc
y De t e c t o r, Ch a r ge P u mp, Lo o p F i l t e r, Vo l t a ge Co nt r o l l e d Os c i l l a t o r us i n g
4 5 n m Te c h no l o g y p r o c e s s a nd a n As y nc hr o no us Lo g i c Mo d e l. F o r t h i s p r o j e c t, f i ve i ns t a nc e s o f
t h e d e s i g n e d P ha s e Lo c k e d Lo o p s a r e t a k e n a nd t he o u t p ut s a r e c o n ne c t e d t o a n As y nc hr o no u
s
Logic Model whose output follows the input for every third incoming edge amongst the 5
incoming edges. The Asynchronous Logic Block Model has been designed and developed using
Verilog
-
A Hardware Description Logic. From the simulation data, it has been o
bserved that the
energy content of the 1GHz signal at the output of the Asynchronous Logic Model is greater than
overall signal energy at the 5 respective inputs.



Title
:
“Phase Lock Loop valid under PVT corners”


Presenter:

(Ali) Hla Moe Myint

Time:

03
:
25
-
03:50

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Th i s p r o j e c t wi l l fo c us o n d e s i g n i n g a p h a s e l o c k l o o p wh i c h l o c k s t he r e f e r e nc e
f r e q ue nc y t o fe e d b a c k fr e q ue nc y a t 2 4 GHz. To c o mp e ns a t e p r o c e s s, vo l t a ge, a nd t e mp e r a t ur e
va r i a t i o ns, t he d e s i g n i s fo c u s e d o n ge ne r a t i n g wi d e r t u n i n g r a n ge o f LC
-
VCO o ut p u t fr e q ue nc y
us i n g c o mp a r a t o r a nd d i g i t a l c o n t r o l l o g i c t o c o n t r o l LC
-
VCO fr e q ue nc y, wh i c h va r i e s f r o m 2.1 5
GHz t o 2.9 GHz. The p r o j e c t wi l l i n c l u d e t he fo l l o wi n g c o mp o ne nt s:

P ha s e F r e q ue nc y De t e c t o r,
Cha r ge P u mp, Lo w P a s s F i l t e r, LC
-
VCO, a nd c l o c k d i v i d e r c i r c u i t. 2.4 GHz, o u t p ut f r e q ue nc y o f
r o b u s t P VT v a r i a n t P LL, c a n b e us e d i n wi r e l e s s l o c a l a r e a ne t wo r k ( WLAN) a p p l i c a t i o ns. Us i n g
t h e f u l l c u s t o m d e s i g n f l o w, t h e p r o p o s a l

P LL d e s i g n i s s i mu l a t e d a nd ve r i f i e d us i n g Ca d e nc e
t o o l: 0.4 5 nm CMOS p r o c e s s t e c hno l o g y.



Ti t l e
:
“RF Mixer Pipeline ADC Path”


Presenter:

Pritesh Mandaliya, Pushkar
Sabnis

Time:

04
:
00
-
04:2
5

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Li l i He



Abstract:
Digital systems is the key part in today’s’ electronics era. All the real signals in the
world are analog in nature. Hence, to process these signals digitally they first need to be
converted into digital form. Analog to Digital Converter (ADC) c
onverts analog signals into
digital signals. Also, lots of applications in today’s world operate at a Bluetooth frequency of
2.4GHz. Hence, a down converter (Mixer) is required to properly process these signals. Hence,
ADC and Mixer are the 2 key component
s of this project. The project focuses on the design of
the Mixer and pipelined ADC path from the RF Receiver using 90 nm gate channel length
technology in Cadence optimizing the design for low power. This design will have low power
consumption and less ar
ea as compared to the present designs by properly scaling the values of
the capacitors and sharing the operational amplifiers in the ADC. 90 nm channel technology
improves transistor concentration, makes the design smaller and reduces power consumption as
it operates on a lower power supply as compared to higher channel length technologies such as
0.18u. The project will primarily concentrate on creating a schematic design at the transistor
level, debugging the design, doing the layout of the design using C
adence IC design tool kit. RF
Mixer will down convert 2.4 GHz using 2.38 GHz Local Oscillator Frequency to 20 MHz
intermediate frequency (IF). This IF will be the input of the pipelined ADC. This 8
-
bit pipelined
ADC will operate at 60MSPS speed using 1.5bi
ts/stage consuming less than 20 mW of power.





Title
:

Verilog Design of QRD
-
RLS Algorithm for FPGA



Presenter:

Venugopal Kanneboina

Time:

04
:
25
-
04:50

P
M

Advisor:

P r o f.
Cha ng Cho o

Co
-
Advisor:

?



Abstract:
Adaptive FIR filter is used in various DSP applications including Multi
-
input
-
Multi
-
output (MIMO) systems and adaptive beam forming. There are two major algorithms used in
adaptive filters; Normalized Least Mean Squares (NLMS) and Recursive Least Squares (
RLS).
Performance of RLS is often much better that that of NLMS, although the former is much more
expensive in the use of hardware resources.

Objective of this project is to design one of the RLS algorithms, called QR
-
Decomposition RLS,
in Verilog HDL for

FPGA implementation. The RLS algorithm calculates recursively the
coefficients of the filter that minimizes the weighted least squares of the input signal. The QR
-
Decomposition of the matrix is achieved by using Givens rotation algorithm which decomposes
it into an orthogonal matrix and an upper triangular matrix. This is an efficient way of
implementing RLS algorithm, as it avoids the need to compute the inversion of the matrix and
also has efficient hardware architecture for FPGA implementation. The mode
ling has been
validated on Matlab. The algorithm has been designed in Verilog HDL and simulated using
Xilinx ISim simulator. This design can be implemented in Xilinx XC3S200 FPGA boards
.




Title
:
“Design and Implementation of Double Talk and Silence
Detector for Acoustic Echo
Canceller”


Presenter:

Hemant Koka

Time:

04
:
50
-
05:15

P
M

Advisor:

P r o f.
Cha ng Cho o

Co
-
Advisor:

?


Abstract:
Acoustic echo is generated by reflection of speaker sound from ambience during
conference or mobile phone call. Such echo causes disturbance and needs to be cancelled to
improve QoS. The acoustic echo canceller (AEC) is implemented using an adaptive filter
. The
condition when both far
-
end and near
-
end speak simultaneously is referred to as double talk.
When double talk or silence is detected, adaptation of filter coefficients is suspended.

The double talk and silence detection are based on power calculation

and thresholding. In this
project, we designed this detector in Matlab and Verilog. We developed the Verilog model using
Altera Quartus II and verified it using Modelsim. The target hardware was Altera DE
-
2 Board
containing an inexpensive Cyclone II FPGA.

The detector utilizes approximately 400 LEs and 46
embedded multipliers. The design runs at 81MHz. This module is used as a key component for
the ongoing wide
-
band AEC project.



Title
:
“FPGA to ASIC Conversion of Adaptive FIR Filter”


Presenter:

Lawrence Lo

Time:

05
:
15
-
05:40

P
M

Advisor:

P r o f.
Cha ng Cho o

Co
-
Advisor:

?



Abstract:
Adaptive FIR (Finite Impulsive Response) filter is widely used in DSP and digital
communications applications including echo cancellation, channel equalization and noise
cancellation. In line or acoustic cancellation, an adaptive FIR filter with typically
several
thousand taps are required, based on NLMS (Normalized Least Mean Square) algorithm.

In this project, we converted to ASIC the adaptive FIR filter implemented on FPGA for echo
cancellation applications. The conversion enables us to meet higher perf
ormance and lower
power consumption for today’s market needs. The new adaptive FIR filter ASIC was
implemented using the 32nm low
-
power technology which provides a cost
-
effective solution for
improving competitive benefit and added flexibility. The whole c
onversion process is described
in this presentation.



Title
:
“An Efficient Architecture for Multiview Video Coding for 3D TV”


Presenter:

Sungryol Jin

Time:

05
:
50
-
06:15

P
M

Advisor:

P r o f.
Cha ng Cho o

Co
-
Advisor:

?



Abstract:
Multiview

video coding (MVC) is an amendment to the H.264/AVC video coding
standard. The efficient hardware for compressing large multiview video data is essential to make
3D TV application realizable. Multiple views from multiple cameras share the same image with
slightly different viewpoints, resulting in high data redundancy. The images can thus be
predicted from neighbors and adjacent views to improve the coding efficiency.

The objective of this project is to design an efficient multiview video coding architectu
re based
on H.264/AVC. In order to reduce the computational complexity in motion and disparity vector
prediction, the architecture is optimized for 6
-
stage pipeline structure. The proposed architecture
reduces the temporal and inter
-
view redundancy using t
he global disparity vector. The search
range of motion vector is limited to ±32 by ±16 and the proposed method results in 4 % of bit
rate decrease on the average without losing video quality.



Title
:
“Conversion of audio frame format (AES/EBU to ADAT Conv
erter)”


Presenter:

Sowri Rekha Devanaboyina

Time:

06
:
15
-
06:40

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Thuy Le



Abs t ra c t:
Aud i o c o n ve r s i o n i s a n e f f e c t i v e t e c h n i q ue us e d i n s i g n a l p r o c e s s i n g a nd ha s
a p p l i c a t i o n i n va r i o us f i e l d s. Th i s p r o j e c t a i ms a t i d e nt i f y i n g d i f f e r e nt d i g i t a l a ud i o fo r ma t s us e d
i n p r o a ud i o i n d us t r y a nd ho w t o c o n ve r t f r o m o n e d i g i t a l a ud i o fo r ma t t o a no t
he r. The t hr e e
ma i n d i g i t a l a ud i o fo r ma t s c o n s i d e r e d fo r t h i s p r o j e c t i nc l u d e, I 2 S, AES/EBU a nd ADAT. The
p r o j e c t wi l l p r o v i d e t he d e s i g n a nd i mp l e me nt a t i o n a s p e c t o f e a c h i n p ut d i g i t a l i n t e r fa c e a nd ho w
d i g i t a l a ud i o d a t a i s fo r ma t t e d t o f i t t o d e s i r e d o u
t p ut i n t e r fa c e i n a F P GA e n v i r o n me n t us i n g
ve r i l o g. A c o mp a r i s o n o f t he s e 3 a ud i o fo r ma t s i n c l ud i n g p r o s a nd c o ns wi l l b e i n ve s t i g a t e d. The
d e s i gn wi l l b e i mp l e me nt e d o n F P GA b o a r d fo r ve r i f y i n g i t s r e a l t i me p e r fo r ma nc e.





















EE Graduate
Seminar
, Track 1

Friday, December 03
, 2010

Room E345

11:00 to 16
:20


MSEE Project Presentation




Title
:
“Digital PLL based Frequency Synthesizer”


Presenter:

Deep Singh

Time:

11
:
00
-
11
:25

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Li l i He


Abs t ra c t:
Th i s p r o j e c t d e a l s wi t h t he d e s i g n o f d i g i t a l P LL b a s e d f r e q ue nc y s y nt he s i z e r. The
d e s i g n i nc l ud e s c u r r e nt s t a r ve d Vo l t a ge Co nt r o l Os c i l l a t o r, P ha s e fr e q ue nc y d e t e c t o r, Bi a s i n g
c i r c u i t, c ha r ge p u mp c i r c u i t, l o o p f i l t e r a nd p r o g r a mma b l e Di v i d e r c i
r c u i t. Th e r e f e r e nc e
f r e q ue nc y us e d fo r t he d e s i g n i s 5 0 MHz a nd t he VCO c e n t e r f r e q ue nc y i s 4 GHz. Th i s
F r e q ue n c y s y n t he s i z e r ge ne r a t e s mu l t i p l e f r e q ue nc i e s d e p e nd i n g o n t he d i v i d e r r a t i o. A
f r e q ue nc y c o nt r o l c i r c u i t i s us e d wi t h t he d i v i d e r c i r c u i t t o s e
l e c t t he p r o p e r d i v i s i o n r a t i o a nd
l o c k fr e q ue nc y. The d e s i g n a nd s i mu l a t i o n wi l l b e i mp l e me nt e d i n Ca d e nc e I C d e s i g n
e n v i r o n me n t t o o l. The s up p l y vo l t a ge us e d i s 1 vo l t a nd t he t e c h no l o g y us e d i n t he d e s i g n i s
gp d k 4 5 nm CMOS p r o c e s s t e c hno l o g y.



Ti t l e
:
“Wide frequency range Multiloop PLL”


Presenter:

Jignesh Patel

Time:

11
:
25
-
11
:50

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Li l i He



Abs t ra c t:
A r e g u l a r P ha s e l o c k e d l o o p ( P LL) c o ns i s t s o f a o ne a na l o g l o w p a s s f i l t e r ( LP F ),
p ha s e d e t e c t o r,
d i v i d e r a nd vo l t a ge c o nt r o l l e d o s c i l l a t o r ( VCO). A s i n g l e l o o p f i l t e r i n P LL
p r o v i d e s l i mi t e d b a nd wi d t h s o P LL t a k e s mo r e t i me t o l o c k a nd ge ne r a t e p h a s e e r r o r. Be c a us e
l o o p f i l t e r b a nd wi d t h i s d i r e c t l y r e l a t e d t o p ha s e no i s e a nd l o c k t i me. As a s o l u t i o n,
t h i s p r o j e c t
c o ns i s t s o f o ne mo r e l o o p f i l t e r. Bo t h t he l o o p f i l t e r s ha s d i f f e r e n t b a nd wi d t h. One f i l t e r ha s wi d e
b a nd wi d t h s o i t c a n e a s i l y l o c k t h e P LL. S e c o nd l o o p f i l t e r ha s na r r o w b a nd wi d t h s o i t wi l l
c o r r e c t t he p ha s e. Lo c k d e t e c t o r c i r c u i t i s us e t
o c he c k t he l o c k s t a t u s a nd c o nt r o l t he f i l t e r
s wi t c h i n g. By i nc r e a s i n g t he fr e q ue nc y r a n ge, p r o p o s e d VCO i s d i f f e r e n t t ha n t he c o n ve nt i o na l.
Th i s p r o j e c t c o ns i s t s o f s wi t c h i n g c i r c u i t, wh i c h s e l e c t s t h e b a nd o f t he fr e q u e nc y b y a d d i n g
c ur r e nt, s o i t p r o vi
d e s wi d e fr e q ue nc y r a nge.




Title
:
“PHASE LOCKED LOOP (PLL) CIRCUIT FOR GSM APPLICATIONS”


Presenter:

Biren Salunke

Time:

11
:
50
-
12
:15

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Li l i He



Abs t ra c t:
P h a s e l o c k l o o p s ( P LLs ) a r e o ne o f t he k e y
e l e me nt s i n t o d a y's b l o o mi n g RF i nd u s t r y.
Al o n g wi t h c o mmo n l y e mp l o y e d t o a d d r e s s v a r i o u s t i mi n g r e q u i r e me nt s i n AS I C d e s i g n s, P LL
i s mo s t c o mmo n l y us e d a s F r e q ue nc y s y nt h e s i ze r. F r e q ue nc y s y n t he s i z e r i s t he mo s t c r i t i c a l
c o mp o ne nt i n wi r e l e s s t r a n s c e i ve r s

fo r f r e q ue nc y t r a ns l a t i o n a nd c ha n n e l s e l e c t i o n. Th i s p a p e r
p r e s e nt s a n i n t e ge r
-

N fr e q ue nc y s y n t he s i z e r, P LL c i r c u i t fo r GS M
-
9 0 0, wh i c h ge ne r a t e s
f r e q ue nc y r a n g e fr o m 8 9 0
-
9 1 5 MHz a t t r a ns mi t t e r s i d e, c o nt a i ns 1 2 4 RF, wh i c h 2 0 0 KHz a p a r t
fr o m e a c h o t he r.


Wh i l e s p e c i f i c a t i o ns s e e m s i mp l e e no u g h i n s t r uc t u r e a nd f u n c t i o n, P LL p r e s e n t he r e ha s s o me
u n i q u e d e s i g n c h a l l e n ge s. Wi t h 4 5 na no me t e r
-
s c a l e CMOS p r o c e s s t e c h no l o g i e s, P LL
p e r fo r ma nc e fa c e s mo r e a nd mo r e s e v e r e no i s e l i mi t a t i o ns. I n a d d i t i o n, o t he r i s s u
e s i nc l u d i n g
i n s t a b i l i t y, i n a d e q ua t e f r e q ue nc y r a n ge, l o c k i n g p r o b l e ms a nd s t a t i c
-
p ha s e o f fs e t i s a l s o
d i s c us s e d a s p a r t o f P LL d e s i gn.



Ti t l e
:
“A 2.4GHZ RF RECEIVER FROND END”


Presenter:

Ramkumar Venkataramanujam

Time:

12:15
-
12
:40

P
M

Advisor:

P r o f. Mo r r i s J o ne s

Co
-
Advisor:

P r o f. Li l i He



Abs t ra c t:
A 2.4 GHz Ra d i o fr e q ue n c y r e c e i v e r f r o nt e nd i s d e s i g ne d a nd s i mu l a t e d i n gp d k
9 0 n m t e c h no l o g y. S up e r he t e r o d y ne a r c h i t e c t ur e i s us e d i n t he d e s i g n wh i c h i nc l u d e s a s i n g l e
e nd e d l o w no i s e a mp l i f i
e r, a Lo c a l Os c i l l a t o r a nd a mi x e r t ha t c o mb i n e s b o t h t h e fr e q ue nc i e s t o
ge t I F o ut p u t i n 1 0 0 MHz. The Lo c a l Os c i l l a t o r us e s a r e f e r e nc e f r e q ue nc y f r o m a c r ys t a l
o s c i l l a t o r wi t h na t ur a l fr e q ue nc y o f 2 3 MHz i mp l e me n t e d o f f c h i p. A P LL us e s c r ys t a l o s c i l l a t o r
a s r e fe r e nc e f r e q ue nc y a nd ge ne r a t e s a s i g na l a t a f r e q ue nc y o f 2.3 GHz. The s e t wo fr e q ue n c i e s
a r e c o mb i n e d us i n g a d ua l ga t e mi x e r t o ge ne r a t e I F s i g na l a t 1 0 0 MHz. Th i s r e c e i ve r s ys t e m
c o u l d f i nd a p p l i c a t i o n i n wi r e l e s s LAN a nd Bl ue t o o t h a p p l i c a t i o ns t ha t
us e t he f r e q ue nc y o f
2.4 GHz.



Ti t l e
:
“10 bit Sigma Delta Modulator”


Presenter:

Vinod Reddy Mekala, Raja
Podapati

Time:

12:50
-
01
:15

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abstract:
This paper proposes low power 10 bit Switched capacitor Sigma Delta Modulator for
design of ADC using 45nm technology. The circuit is targeted to applications such as Noise
cancellation earphones. 2nd order Sigma Delta Modulator Architecture is used for de
sign. Clock
frequency of circuit is 4MHz. Fully differential operational amplifier with gain of 40dB and
bandwidth of 12MHz is used for design.



Title
:
“High resolution digital pulse width modulation technique using sigma delta

modulation”


Presenter:

Namita Gokhale

Time:

01:15
-
01
:40

P
M

Advisor:

P r o f.
Da vi d P a r e nt

Co
-
Advisor:

P r o f. Mo r r i s J o ne s


Abs t ra c t:
Mo s t e l e c t r o n i c e mb e d d e d mi c r o c o n t r o l l e r s ys t e ms ha ve p u l s e wi d t h mo d u l a t o r
mo d ul e fo r va r i o us a p p l i c a t i o ns l i k e D t o A c o nve r t e r s, mo t o r
c o nt r o l, s wi t c h

mo d e p o we r s up p l i e s e t c.


The go a l o f t h i s p r o j e c t wa s t o d e s i g n h i g h r e s o l u t i o n p u l s e wi d t h mo d u l a t o r s y s t e m us i n g s i g ma
d e l t a mo d u l a t i o n t e c h n i q ue. The p r o p o s e d d e s i g n us e s a s c he me t h a t i s b a s e d o n t he c o nc e p t o f
o ve r s a mp l i n g a nd no i s e s
h a p i n g. No i s e s ha p i n g i s d o ne wi t h t he l o o p f i l t e r t ha t i s d e s i g ne d i n
s uc h a wa y t ha t i t ha s h i g h ga i n i n t he s i g n a l b a nd a nd t h e i n
-
b a nd q ua nt i z a t i o n no i s e i s s t r o n g l y
a t t e n ua t e d. [ 1 ] The d e s i g n e d p u l s e wi d t h mo d u l a t o r c a n b e u s e d t o d r i v e a b r u s he d d c m
o t o r t ha t
r u n s o n a l o w f r e q ue nc y [ i n t h e r a n ge o f 1 0 K h z


2 0 KHz] [ 2 ]. Th u s, t he mo t o r i t s e l f a c t s a s a
l o w p a s s f i l t e r fo r t he mo d u l a t e d s i g na l. The s e c o nd o r d e r s i g ma d e l t a mo d u l a t o r i s d e s i g n e d a nd
i mp l e me nt e d u s i n g d i g i t a l CMOS t e c h no l o g y. The d e s i g n

c a n a l s o b e s c a l e d t o h i g he r o r d e r
mo d u l a t o r t o a c h i e ve b e t t e r p e r fo r ma nc e. Th e p e r f o r ma nc e o f t he d e s i g n e d mo d u l a t o r i s
me a s ur e d i n t e r ms o f s i gna l t o no i s e r a t i o.


Re fe r e nc e s:

1 )

S c hr e i e r Ri c ha r d, Te me s

Ga b o r “ Und e r s t a nd i n g De l t a
-
S i g ma Da t a Co n ve r t e r s ” J o h n
Wi l e y & S o ns, Ne w Yo r k, 2 0 0 4.

2 )

Te xa s I ns t r ume n t s “Br us he d DC mo t o r c o nt r o l mo d ul e ” Bo a r d d a t a s he e t , F e b 9, 2 0 1 0.



Ti t l e
:
“FABRICATION AND CHARACTERIZATION OF HAFNIUM OXIDE FILMS
FOR
INTERFACING TO A

NEURON



Presenter:

Janet Thao Davis

Time:

01:40
-
02
:05

P
M

Advisor:

Dr.
Da vi d P a r e nt

Co
-
Advisor:

?






Abstract:
In order to use a transistor as a neural interface, the transistor must be protected from
the sodium and potassium
present in the culture media. Fluctuations or shifts in the capacitance
will affect the electrical characteristics of the transistor causing changes to the threshold voltage,
thus making the transistor an unstable amplifier or sensor. In this study, hafniu
m oxide (HfO
2
)
metal oxide semiconductor (MOS) capacitors were fabricated and their ability to maintain a
stable capacitance over time was evaluated in the presence of sodium. HfO
2

is a high
-
κ material
which has the added advantage of increasing the gain o
f the transistor.

The capacitance
-
voltage (C
-
V) method was used to evaluate fixed oxide charge, dielectric
constant, and threshold voltage of the experimental samples. The capacitance
-
time (C
-
t) method
was used to measure capacitance shifts over time due t
o ionic contamination, and the triangular
voltage sweep (TVS) test was used to measure the baseline sodium contamination present in the
grown oxides. Reflectometry methods were used to measure the index of refraction and oxide
thicknesses. HfO
2

was shown t
o be highly resistant to corrosion. The permittivity of the stacked
dielectric including HfO
2

measured was 10.5 and the index of refraction was 2.1 for a 333 Å
film. The capacitance from the C
-
t test was found to be stable when using the 0.1M NaCl
physiolo
gical saline solution on a 197 Å film.



Title
:

Phase locked loop based frequency synthesizer



Presenter:

Chirag Agrawal

Time:

02:05
-
02
:30

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
A f r e q ue nc y s y nt h e s i ze r i s a n e l e c t r o n i c s ys t e m, wh i c h ge ne r a t e s mu l t i p l e fr e q ue n c i e s
f r o m a s i n g l e f i x e d o s c i l l a t o r. To d a y P LL f r e q ue nc y s y nt he s i ze r s a r e wi d e l y us e d i n a l l fo r ms o f
r a d i o c o mmu n i c a t i o n e q u i p me nt s s uc h a s c e l l u l a r p ho n e s, wi r e l e s s p r o d uc t s
, t e l e v i s i o ns, r a d i o s,
l o c a l o s c i l l a t o r s e t c. Ri n g o s c i l l a t o r s a r e u s e d t o r e d uc e t h e d i e a r e a o f f r e q ue nc y s y nt he s i z e r.
The go a l o f t h i s p r o j e c t i s t o g e ne r a t e mu l t i p l e f r e q ue nc i e s a t t he o ut p u t o f VCO.P LL b a s e d
f r e q ue nc y s y nt h e s i ze r c o ns i s t s o f P ha s e
-
fr e
q u e nc y d e t e c t o r ( P F D), c ha r ge p u mp, l o w p a s s f i l t e r,
VCO a nd a d i v i d e r. The f u nc t i o n o f P F D i s t o c o mp a r e t he p ha s e o f r e fe r e nc e s i g na l a nd
fe e d b a c k s i g n a l a nd t h i s d i f f e r e nc e i n p ha s e i s c o n ve r t e d b y c ha r ge p u mp a nd l o w p a s s f i l t e r i n t o
a c o nt r o l vo l t a ge.

Th i s vo l t a ge c o nt r o l s t he VCO a nd a s i g n a l wi t h d e s i r e d f r e q ue nc y i s
ge ne r a t e d. The us e o f p r e s c a l e r o r mu l t i p l e d i vd e r s i n t he fe e d b a c k p a t h c a n b e u s e d i n o r d e r t o
ge ne r a t e mu l t i p l e f r e q ue nc i e s a t t he o ut p u t o f VCO. I n l o c k e d c o nd i t i o n, s i n c e r e fe r e nc e
a nd
fe e d b a c k fr e q ue nc i e s mus t b e e q ua l, t he o u t p ut f r e q ue nc y i s e q ua l t o t he p r o d uc t o f r e f e r e nc e
f r e q ue nc y t i me s t he d i v i s i o n r a t i o. By c ha n g i n g t he d i v i s i o n r a t i o, s i g n a l s wi t h d e s i r e d f r e q ue nc y
c a n b e ge ne r a t e d. The r e f e r e nc e f r e q ue nc y us e d i n t h i s p r o j
e c t i s 1 0 0 MHz a nd t he t e c h no l o g y
us e d i s TS MC 0.1 8 um.



Ti t l e
: “De s i g n o f Di r e c t l y Di gi t i ze d S ynt he s i z e ”


Pre s e nt e r:

Ja yk uma r Da l wa d i

Ti me:

0 2:4 0
-
0 3
:0 5

P
M

Adv i s o r:

Pr o f. Li l i He

Co
-
Advisor:

Pr o f. Mo r r i s J o ne s



Abs t ra c t:
No w
-
a
-
d a ys c o s t
-
c o mp e t i t i ve, h i g h p e r f o r ma n c e, f u l l y i n t e gr a t e d a nd c o mp l e x
p a c k a ge d
-
s i z e d DDS ( Di r e c t l y Di g i t i z e d S y nt he s i ze r ) p r o d uc t s a r e ga i n i n g a c c e p t a nc e a s a n
alternative to a traditional frequency
-
agile analog synthesizer (PLL). The Directly Digiti
zed
synthesizer produces sine wave by generating time varying signal in the digital form and then
converting that digital form in analog waveform using Digital to Analog converter. The desired
frequency of the output sine wave can be specified by 16 bit Ph
ase Accumulator. The DDS
(Directly Digitized Synthesizer) consist of three main blocks, i.e. 16 bit Phase Accumulator, 256
Byte ROM & 7 Bit Digital to Analog converter running at 1GHz clock frequency. DDS has
benefits over PLL like sub
-
hertz frequency reso
lution, fast settling time, low phase noise, less
area & cost.



Title
:
“Hybrid adder with combination of CLA, CSA and RCA”


Presenter:

Ankit Garg

Time:

03:05
-
03
:30

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Ad d e r i s a f u nd a me n t a l o p e r a t i o n i n d i g i t a l c i r c u i t s o f a d d i n g b i t s. The r e i s a gr o wi n g
d e ma nd fo r h i g h s p e e d a nd l o w p o we r c o ns u mp t i o n i n mo d e r n c o mp u t e r s fo r b e t t e r p e r fo r ma nc e
o f ALU, wh i c h c o nt a i n mo s t b a s i c p a r t a d d e r. Al s o i t s us e d fo r fa s t mu l t i p l i c
a t i o n a nd o t he r
i mp o r t a nt c i r c ui t func t i o n s a nd he nc e a d e d i c a t e d ha r d wa r e b e c o me s ne c e s s a r y.

The go a l o f t h i s p r o j e c t wa s t o d e s i g n a h yb r i d a d d e r wi t h c o mb i na t i o n o f d i f f e r e n t a d d e r b a s e d
o n t he i r c ha r a c t e r i s t i c s. RCA( Ri p p l e c a r r y a d d e r ) go o d f o r l o we r
b i t s, l e s s d e s i g n c o mp l e x i t y a nd
e a s y t o i mp l e me nt. C LA( c a r r y l o o k a he a d a d d e r ) i s t h e fa s t e s t c a r r y ge ne r a t i o n a d d e r.
CI A( Ca r r y I nc r e me n t Ad d e r ) c a l c u l a t e s c a r r y f i r s t b y a s s u mi n g c a r r y i n e q u a l t o ze r o a nd t he n
i n c r e me nt t he s u m i f i t s o n e. CS A( Ca r r y s
e l e c t a d d e r ) c a l c u l a t e s s u m fo r b o t h c a r r y i n p ut e q ua l
t o ze r o a nd o ne i n a d va nc e a nd t a k e c a r e o f o ve r f l o w b i t s i f a n y. Af t e r a na l y z i n g d i f f e r e nt a d d e r
c ha r a c t e r s t i c s, d e s i g ne d a h yb r i d a d d e r wi t h RCL fo r LS B( Le a s t s i g n i f i c a n t b i t s ), c o mb i n a t i o n o f
CLA a n
d CI A fo r mi d d l e b i t s a a nd CS A f o r MS B b i t s t o t a k e o f o v e r f l o w i n a d va nc e. De s i g ne d
a r c h i t e c t ur e s up p o r t s t he r e u s e o f d i f fe r e nt b l o c k s. Tr a d e o f f wa s s e e n i n t e r ms o f ha r d wa r e us e d,
c o mp l e x i t y a nd r e us e o f c i r c ui t i n fut ur e.



Ti t l e
:

DDR2
-
SDRAM Memory
Controller



Presenter:

Mahesh A. Mylarapu

Time:

03:30
-
03
:55

P
M

Advisor:

P r o f.
Thuy L
e

Co
-
Advisor:

P r o f. Mo r r i s J o ne s



Abs t ra c t:
Th i s p r o j e c t i s t o d e s i g n a nd ve r i f y a DDR2
-
S DRAM c o nt r o l l e r. The c o n t r o l l e r c o r e
s up p o r t s mo s t o f t he fe a t u r e s o f J EDEC
s p e c i f i c a t i o ns o n DDR2
-
S DRAM. S o me o f t he ma j o r
fe a t ur e s i n c l ud e us e r c o nt r o l l e d i n i t i a l i z a t i o n, Mo d e Re g i s t e r S e t t i n g ( MRS ) a nd Ext e nd e d Mo d e
Re g i s t e r S e t t i n g ( EMRS ), va r i a b l e b ur s t l e n gt hs, c o n f i g u r a b l e C AS l a t e nc i e s, a ut o
-
r e f r e s h a nd
s e l f
-
r e fr e s h mo d e s,

e t c …


The c o r e ha s b e e n ve r i f i e d wi t h h e l p o f DDR2
-
4 0 0 mo d e l f r o m Mi c r o n. The t e s t e n v i r o n me nt
ha s r a nd o m a nd s e q ue nt i a l d a t a ge ne r a t i o n b l o c k s t ha t a r e us e d i n ge ne r a t i n g d a t a fo r DDR
controller. The data is written to the model through the DDR controlle
r and read back. Checking
is done by reading/writing the model data through a back door method and comparing it with
data from data generation tasks. Testcases that were carried out include (using both burst length
settings) random writes and reads, sequen
tial writes and reads, read followed by write and vice
versa, burst writes and reads, writes with data masks, and read terminated using overriding reads.


The design has been targeted for Xilinx virtex
-
5 family of FPGA’s and can be used in any SOC
based
applications that has a single master
.



Title
:
“An All
-
Digital Phase
-
Locked Loop with Input Fault Detection”


Presenter:

Tin
-
Yam Yau

Time:

03:55
-
04
:20

P
M

Advisor:

P r o f. Tr i Ca o huu

Co
-
Advisor:

P r o f.
Thuy L
e



Abs t ra c t:
An a l l
-
d i g i t a l p ha s e
-
l o c k e d l o o p ( ADP LL) ha v i n g a fa u l t d e t e c t i o n o f t he i n p ut
r e fe r e nc e s i g na l wa s mo d e l e d i n Ve r i l o g ha r d wa r e d e s c r i p t i ve l a n g ua ge ( HDL) a nd i s p r e s e nt e d
i n t h i s p a p e r. The d e s i g n c a n t r a c k a n i n p ut s i g na l wi t h fr e q ue n c y r a n g i n g fr o m 6 1 k
Hz t o
4 3 MHz i n a ma x i mu m l o c k e d
-
i n t i me o f f i v e r e f e r e nc e c yc l e s. I n t he c a s e o f l o s s o f i n p ut
r e fe r e nc e, i t c a n c o nt i n u e t o ge ne r a t e a n o u t p ut s i g n a l wi t h t h e p r e v i o us l y s t o r e d p a r a me t e r s a nd
r e p o r t t he a no ma l y a s s t a t u s. The f u n c t i o na l a nd t i mi n g r e q u i
r e me nt s o f t he d e s i g n we r e ve r i f i e d
us i n g S y no p s ys e l e c t r o n i c d e s i g n a ut o ma t i o n ( EDA) t o o l s. The ADP LL c a n b e u t i l i z e d a s a n
i n t e l l e c t ua l p r o p e r t y ( I P ) c o r e t o r e d uc e t he d e ve l o p me n t t i me o f a n a p p l i c a t i o n
-
s p e c i f i e d
i n t e gr a t e d c i r c u i t ( AS I C) p r o d uc t. The

i np ut fa u l t mo n i t o r i n g c a p a b i l i t y c a n p r o v i d e o p e r a t i o na l
fe e d b a c k t ha t i mp r o ve s t he o ve r a l l s ys t e m r e l i a b i l i t y.




















MSEE Thesis Defense

16:30 to 18:1
5




Thesis Title
:
“Study of the Switching Mechanisms of Resistance Change Memories”


Presenter:

Da Xia

Time:

04:30
-
05
:05

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Da vi d P a r e nt & P r o f.
S o t o ud e h Ha me d i
-
Ha g h



Abs t ra c t:
Re s i s t a n c e c ha n ge me mo r i e s ( RRAMs ) a r e a t t r a c t i n g l o t s o f a t t e n t i o n r e c e nt l y. The
s wi t c h i n g b e h a v i o r s a nd me c h a n i s ms o f RRAMs a r e s t i l l u nd e r i n ve s t i g a t i o n, ma n y q ue s t i o n s a r e
s t i l l o p e n. Th i s t he s i s p r e s e nt s a c o mp r e he ns i v e s t ud y o f t h e s wi t c h i n g b e ha v i o r
s a nd
me c ha n i s ms o f RRAMs. Va r i o us RRAM mo d e l s a r e s t ud i e d a nd a na l y z e d. A Ve r i l o gA mo d e l o f
RRAMs i s i n t r o d uc e d. Th i s mo d e l g i v e s a d e t a i l e d t e c h n i c a l e xp l a na t i o n o f RRAMs wh i c h
c o mp l i me nt s e x i s t i n g mo d e l s. Va r i o us p o t e n t i a l a p p l i c a t i o ns o f RRAMs a r e i n t r
o d uc e d. F i na l l y,
t h e s i mu l a t i o n r e s u l t s o f t he Ve r i l o g A mo d e l a r e p r e s e nt e d a nd d i s c us s e d. The s i mu l a t i o n r e s u l t s
i nd i c a t e b a s i c I
-
V c ha r a c t e r i s t i c s a nd p r o p e r t i e s o f RRAMs d e c e nt l y. As a s u mma r y, t he f u t ur e
o f RRAMs i s p r o mi s i n g.



The s i s Ti t l e
:
“Modeling

of the Impact of Electrical Stressors on the Degradation Process of
Power MOSFETs”


Presenter:

Shompa Shohiny Mahiuddin

Time:

05:05
-
05
:40

P
M

Advisor:

P r o f. Li l i He

Co
-
Advisor:

P r o f. Mo r r i s J o ne s & P r o f.
Da vi d P a r e nt



Abs t ra c t:
The r e s e a r c h f o c us e s
o n b u i l d i n g a mo d e l b a s e d o n c o l l e c t i o n o f e xp e r i me nt a l d a t a
a c q u i r e d wi t h h i g h e l e c t r i c a l s t r e s s o r s a t t he ga t e o f t he p o we r MOS F ET u nd e r i s o t he r ma l
c o nd i t i o n t o a na l y ze c e r t a i n d e gr a d i n g i n t r i n s i c p r o p e r t i e s l e a d i n g t o d e g r a d a t i o n. The p r i ma r y
i nd i c a t o r
s a r e t hr e s ho l d s h i f t, d e v i a t i o n i n s wi t c h i n g c ha r a c t e r i s t i c s a nd s i g n i f i c a nt e xp a n s i o n o f
Mi l l e r P l a t e a u d ue t o a c c e l e r a t e d s t r e s s i n g o f t he d e v i c e fr o m t he p r i s t i ne c o nd i t i o n. The
i n t r i n s i c me c ha n i s m a s s o c i a t e d wi t h t he t hr e s ho l d s h i f t a nd c ha n g e s i n t h
e p a r a s i t i c c a p a c i t a nc e s
a r e o b s e r ve d a nd a na l y z e d wi t h ma t he ma t i c a l p r e c i s i o n a nd d e v i c e p a r a me t e r s i mu l a t i o n. I t i s
s e e n t ha t t he t hr e s ho l d vo l t a ge s h i f t s b y 1 7 2 %, t h e wi d t h o f Mi l l e r P l a t e a u i n c r e a s e s b y 5 2 5 %,
c a p a c i t a n c e s a r e r e d uc e d b y 2 4 ~ 4 3 % a t a p p l
i e d s t r e s s i n a d d i t i o n t o a l t e r e d s wi t c h i n g b e h a v i o r
a nd o t he r c ha n ge s. Th i s b e ha v i o r s a t i s f i e s o ne p a r t o f t h e h yp o t he s i s b y e x h i b i t i n g d e v i a t i o n
f r o m p r i s t i ne c o nd i t i o n; ho we ve r, d e gr a d a t i o n d o e s no t o c c u r. The r o o t c a us e o f t he mo d i f i e d
b e ha v i o r o f s t r
e s s e d d e v i c e i s a l s o a na l y z e d. Two
-
d i me ns i o na l d e v i c e p r o c e s s i n g s o f t wa r e
“S e nt a ur us ” c o r r e l a t e s t he hyp o t he s i s b a s e d o n t he e xp e r i me n t a l o b s e r va t i o n.


Thesis Title
:

Principles of X
-
ray crystallography



Presenter:

Luke Snow

Time:

05:40
-
06
:
1
5

P
M

Advisor:

Ra y Kwo k

Co
-
Advisor:

P r o f.
S o t o ud e h Ha me d i
-
Ha gh

&

Ma s o ud Mo s t a fa vi



Abs t ra c t:
P r i nc i p l e s o f X
-
r a y c r ys t a l l o g r a p h y a r e ve r i f i e d a t r a d i o
-
fr e q ue nc y us i n g t h e c o mp u t e r
p r o g r a m HF S S, a nd u s e d t o d e s i g n a n a n t e n na. The a n t e n na i s c o n s t r u c t e d u s i n g a 2
-
d i me ns i o na l
ma c r o s c o p i c c r ys t a l r e a l i z e d b y a n a r r a y o f ve r t i c a l p o s t s, mo u nt e d i ns i d e
a ho r n
-
l i k e s t r uc t ur e
c o n ne c t e d t o a s t a nd a r d wa v e g u i d e. The d i r e c t i o n o f t he ma i n l o b e o f t h e a nt e n na r a d i a t i o n
p a t t e r n i s d e s i g ne d v i a Br a g g’ s l a w, a nd t he p e a k wi d t h i s c o mp a r e d t o t he r e s u l t s g i v e n b y t he
S c he r r e r La w. The d e s i g n wi l l b e v e r i f i e d b y e x
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