C 16 Draft rev 2

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16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999




Microprocessor based relays are replacing the old electromechanical relays for several reasons. This
includes the added features and capabilities that are offered with the newer technology that an
Intelligent Electronic Device (IED) offers

Retrievable files include things such as settings, event records, disturbance or oscillographic
records, fault location, along with time stamping of the record.

Input/output logic can take advantage of these new functions and offer reliability enha
ncements to
remove failure prone auxiliary relays that were previously used for the logic necessary for various
functions. In addition, this logic can perform what could be construed as adaptive functions to some

Adaptive settings can react to l
oad level changes and adjust settings accordingly. This would be
advantageous for winter peak temporary settings.

Communications allow for the remote access to the relay for various retrievable files tasks, as well
as control functions. Initially, these

communications may have taken place over modem based
TELCO circuits. However, due to NERC and other security concerns relay communications are
generally performed over fiber optics cables or Local Area Networks. The security question, or
Cyber Security

as it now has it’s own subject area, is addressed mostly through the use of strong
passwords, or special permissive hardware schemes that grant access to the devices to authorized

Time synchronizing of the relays to GPS time allows comparison of a
ll fault records and sequence
of events files to analyze events that take place. This further allows time stamping of the events
within the Sequence of Events (SOE) function of the IED. This provides a detailed event log that is
especially helpful in tro
ubleshooting misoperation events.

Protection relays are no longer simply a single function device that only mimics the

electromechanical relay function that it replaced, h
nce the name multifunction relay has emerged.
In addition to the operate function
and output contacts, there are other various features built into
multifunction relays that enhance the protection.

Forms of programmable logic control have
manifested themselves with names such as input/output logic, ladder logic, and similar terms.

tiple settings, setting groups, and even adaptive settings may be offered [1], [2]. As an example
for distribution applications, Winter/summer settings, load related, or storm related temporary
reclosing sequence settings are just a couple of examples cur
rently in use for distribution functions.
Breaker failure and breaker restrike detection are just a couple of transmission examples [3], [4].

Platforms for the Multifunction IED have been offered where the basic building block of the relay
defines the ge
neral construction, and then additional I/O boards and options with various firmware
further defines specific functionality of the relay for a given application.

Wiring from one relay to another has always presented various restrictions or concerns, not
mention the added costs and complexity of wiring. Multiple relays or contacts might be required to
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


be wired between relays and panels, which might be located in close or not
close proximity to
each other. By taking consolidating various functions w
ithin the IED itself, wiring on the relay
panels can be reduced, sometimes reducing a panel of relays down to a very low count of
components, sometimes to a single primary relay and a single backup relay.

The I/O functionality also has the advantage of re
placing the use of auxiliary relays, which
historically have contributed to some misoperations due to open coils or contacts or wiring. Making
use of a single input might be mapped to several outputs, which in turn could be wired or
communicated to adjace
nt or peer IEDs.

All modern microprocessor relays have built in self diagnostic logic for self monitoring the health
of the relay. Self
checking diagnostics of I/O hardware may be available which in turn may provide
for almost complete monitoring of the

IED health, with the exception of the output contact itself [1],
[2]. By combining this self monitoring with other internal logic, such as loss of potential and/or
loss of current detection, the user can have a very good indicator of the health of the re
lay. A
combination of relay alarm and output contacts can be wired into local annunciator points and
passed to remote supervisory control and data acquisition (SCADA) monitoring for early indication
of a relay problem. This early warning can help reduce th
e possibility of a relay misoperation or
failure to operate. Complete monitoring of a given IED and the relay scheme can help reduce
maintenance costs as the health of the IED is always known.


Common issues

While much has changed, microprocessor relays h
ave not changed everything about circuit design


DC circuit separation, redundancy

Applying these IEDs causes the engineer to look at several factors:

A. How many functions do I need?

B. How many functions fit in one box?

C. How many boxes do I need?

D. If one box fails,
is there


that provides backup or redundant
protection functions?

there is

a DC system malfunction, how

does it affect the

Conversely, if there is
a protective relay malfunction, short circuit, etc.
, how does

affect the DC system

G. D
oes either (E) or (F) cause a failure that prevents the protective device from
operating the designated breaker, lockout relay, etc?

Where one relay or IED could possibly cover the requirements of both A&B, and it
provide redundant functions within the box, it may most likely fall short of providing the
required redundancy should the power supply fail in the box taking the box down.
Therefore, two boxes, with a splitting up of the protection functions would be
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


where primary functions may be in one box, and the secondary or backup or redundant
functions are in the second box.

By the same token, “isolation” in the DC systems may be realized by separate fusing
circuits, or where more than one battery ban
k is available, separating the functions out so
that primary functions are on one bank and the secondary functions are on the other bank, or
possibly separated by trip coil usage depending upon the utility practice.


Relay contact ratings

In a perfect worl
d, the output or tripping contacts would always be rated to fully close, open,
and carry all currents and applied voltages ever applied to the device circuit. However, big
and clunky do not translate to fast and small. Contact closing and contact carryin
g is
generally not an issue as long as the relay specification is reviewed with the device being
operated. Contact opening on the other hand can be a disaster in the world of DC voltage
and inductive trip and close operate coils.

The issue here is that f
or AC voltage, the arc that takes place when the contacts open is self
extinguishing. Not the case for DC. As the DC voltage level of the DC Battery System
increases, and as the inductance of the coil increases, this results in quite an arc between the
ontacts, causing bumps and holes to form on the contacts until they are unusable.
Sometimes the contact simply vaporizes or welds shut. Various surface materials are
available for special applications, however, the culprit here is the voltage across the
when it opens and the failure to extinguish the arc. Another method adopted by some of the
auxiliary relays provides is a magnetic blowout aided rated contact to help blowout the arc.
Depending upon the T=L/R ratio, the effect is greater as L inc
reases relative to the
small R
value. A break rating of 4
50% of the carry rating may be typical depending upon the
special ratings.

Most circuit breaker or lockout relay circuit schemes typically use a closed contact in series
the coil being

operated. T
hat way, the heavy duty auxiliary contact actually opens up and
breaks the DC current. This would be true whether in the close or trip circuit.

In the case of protective relays, one needs to step back and compare the older
electromechanical relay (ELM) tri
p contacts with the new microprocessor IED contacts.

In the ELM relay, depending upon the construction and the manufacturer of the protective
relay, there typically was a protection relay contact, which typically operated with a seal
and target coil a
ssembly to provide both the functionality of a target and the heavy duty
rating to trip the circuit breaker or end device. In many cases, this target coil scheme even
had two available current selection taps, such as 0.2 and 2.0 amperes. Selection of the

ampere tap would have the least affect on tripping current to the end device, but may not
always drop a target if the device had a higher resistance trip coil and drew less than 2
amperes. If the 0.2A tap was chosen in order to drop a target, then th
e target resistance
increased substantially, and could possibly reduce the voltage available to the end device(s)
being tripped and the end device(s) may fail to operate. (i.e., DC resistance of the 2.0A tap is
0.24 ohms and of the 0.2A tap is 8.3 ohms.)

So, in this arrangement, the seal
in contact picked up around the protective relay contact and
the small relay contact was not subjected to the arcing when it opened and the large contacts
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


took the brunt of the operation. Again, they usually relied upon t
he device being tripped
having the ability to open up the trip or close circuit and chose not to provide any break

Typical Example 0.2 / 2.0 target and seal
in ratings

in Coil tap



Carry 30A for




Carry 10A for








Min operating




DC Resistance




In the microprocessor IED, a more typical arrangement is a “target” that is independent of
the trip or close coil current, but simply an indica
tion that the output contact was called upon
to operate. The contact itself may be a single “a” contact, or multiple contacts in series,
sometimes referred to as an “x” contact. The use by the manufacturer of using more than
one contact in series provide
s for the voltage and arc to be broken across the number of
contacts. So, in a 125vDC system, instead of one contact attempting to break the current
with 125v across it, if there are two internal contacts in series, the contact only sees half
voltage acro
ss it and has a slightly better chance of survival. Keep in mind that the relay is
expecting for the end device to provide a series auxiliary contact capable of breaking the DC
current such that when the relay contact opens, the current has already been b
roken. An
example of the ratings of the
trip contacts in one microprocessor IED:

Make and Carry for 1.0 sec:

30 A @ 300 VDC (ANSI)

Carry Continuous:

6 A @ 300 VDC.

Break @ L/R of 40 ms:

0.25 ADC Max

So, for a stuck circuit breaker

the contacts need to be checked for damage. The
same holds true for the reclosing circuit where the reclosing funct
ion of the relay attempted
to close a breaker with a DC close circuit and the breaker did not close. In both cases, the
protection relay co
ntact may be wielded shut, heavily damaged, or burned open.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Bibliography & references

IEEE/PSRC Website: http://www.pes


Refer to the IEEE/PSRC website, “Understanding Microprocessor Based
Technology Applied To Relaying, WG
I16 Report, 2004


EEE Tutorial Course, Microprocessor Relays and Protection Systems, 88EH0269


Bruce Pickett, Mirta Signo
Diaz, Alan Baker, Joe Schaefer, John Meinardi

(Florida Power & Light Co), Bogdan Kasztenny, Ilia Voloh

General Electric

vin Depew, Joseph Wolete

Potomac Electric Power Co; “Restrike and Breaker Failure
Conditions for Circuit Breakers Connection Capacitor Banks” TAMU 2008 Protective Relay
Conference and GaTech Protective Relay Conference.


K3 Paper

Reducing outa
ge durations through improved protection and
autorestoration in distribution substations. (12


Separate CT & PT circuits

Typically, separate CT circuits are utilized for a power element’s redundant relay protection
packages. If one of the relays i
s connected to one CT set and is taken out of service for
maintenance and testing, the second, redundant, relay, which is connected to the other CT
set, will provide protection for the power element. Therefore, it is advantageous to have
separate CT circui
Fault in the control cable?

However, a failure of a CT will result in an outage for all the power elements if the failed
CT is located in their protection zones. From this perspective, separating the CT circuits will
not help to avoid the outage shoul
d a CT failure occur.

Separating PT circuits, when one of the relays is connected to the PT secondary and the

to the PT tertiary windings is helpful to keep at least one of the relays in service
when a secondary PT fuse is blown on the other relay
’s input. This advantage is in addition
to a situation when one relay is taken out of service for maintenance and testing.

The principle of separating the CT and PT circuits remains valid when the microprocessor
relays are utilized, even more so since, ty
pically, the identical protective functions are
programmed in both redundant protective relaying packages. Separate CT and VT control
circuits and a complete duplicate of the protective functions in the second relay will insure
the adequate protection of t
he power system element when one of the control circuit paths or
relaying packages becomes temporary unavailable.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999



Changes to relay trip circuit design due to microprocessor relays

Although the capabilities of programmable logic and multiple inputs and ou
tputs has
enabled microprocessor relays to be used to modernize and simplify a variety of classical
protection and control schemes, many of the relay trip circuit design practices that engineers
and designers followed in the component relay days are still
valid today. For example, it is
important to ensure that the type and current rating of any relay output is appropriate for the
application. It is still good practice to route and size DC control cables to limit the voltage
drop to an acceptable value wh
en the breaker is tripped. For high voltage protection
schemes, the primary relays are often connected to operate trip coil one of the breaker, and
the secondary relays may be connected to operate trip coil two. In some protection and
control schemes, th
e relays are supplied from a different DC source than the breaker(s).


Trip Circuit Design

M. Best/K. Behrendt

Circuit breaker control circuits perform the vital tasks of electrically tripping and closing the
circuit breaker. As such, these control circu
its should be simple and very reliable. The trip
circuit is a very critical link in the overall process of detecting and interrupting fault current
to safely isolate a faulted power system circuit. Utmost attention must be paid to making this
circuit as si
mple and reliable as possible.

Microprocessor based relays offer built
in functions that can simplify trip circuit design and
improve reliability when compared to traditional schemes using component style relays.
The control voltage level for substation
DC systems may be selected for 24, 48, 125, or 250
V DC, with 125 V DC being typical. Voltage levels of 125 V and above were often used in
the past to ensure that any contaminants from the surrounding environment that accrued on
the contacts of some auxil
iary relays would not prevent full voltage to be delivered to the
operating coils of other relays in the control scheme. The designer has greater flexibility in
selecting the DC control system voltage for microprocessor relay designs because the output
ntacts of microprocessor relays are encapsulated so that contaminants from the
surrounding environment are not an issue.

Some examples of built
in functions include:

Logic driven targets

Breaker failure initiate logic and timers

Autoreclose initiate lo
gic and timers

Microprocessor based relays generally have multiple “trip
rated” contacts that can energize
and operate breaker trip coils directly without the need for auxiliary contacts or seal
devices. The presence of multiple isolated contacts makes

it relatively simple to provide
redundant trip circuits to individual trip coils on breakers with dual trip coils. Multiple trip
contacts also allows for tripping multiple breakers without the need for contact multiplying
auxiliary relays.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


, protection and control schemes used c

style electromechanical
(EM) and solid
state (SS) relays.
relays historically used to implement protection and control

These relays generally require internal auxiliary devices in the circuit bre
aker trip
circuit to provide targeting and to seal in around delicate, non
rated relay contacts. They
also require external auxiliary relays to initiate breaker failure timers and automatic
reclosing for protective relay trips. Steering diodes are al
so required in the trip circuit to
segregate manual and SCADA initiated tripping from the protective relay trips when it is
desirable to prevent breaker failure initiation and automatic reclosing for manual and
SCADA trips.

The EM and SS relays


normally equipped with target indicators

trip seal
units that



the current drawn by the breaker trip coil. If multiple relays
, their individual target indicators
sometimes did

not always operate because of
le trip current paths. Therefore, the DC current setting (usually 0.2 or 2.0 Amps) for
each target indicator


to be selected to ensure that each individual device

” enough
of the total coil
trip current to operate the target whenever mul
tiple relays

Each additional element in the trip circuit complicates the wiring, decreases the overall
reliability of the scheme, and introduces the possibility of “sneak circuits” that may cause
inadvertent and undesirable operation, not to men
tion adding cost and requiring

Microprocessor relays essentially eliminate the problem of

ensuring correct

by providing a single
for multiple

trip current path

and using
microprocessor relays use
/logic driven


indicating means

, thereby
simplifying the circuit breaker trip circuit.

Moreover, a single contact operated by all
protective functions in the relay is typically used to trip the breaker.

The multiple
output conta
cts available in microprocessor relays can be used to trip
multiple breakers directly without introducing an additional trip time delay from dc auxiliary
tripping relays. Direct tripping of the breakers ensures that the individual breaker trip
circuits ar
e isolated from one
and limits the total trip current drawn through any
single contact to the individual breaker trip coil current.

in breaker failure and autoreclose initiates, plus isolated inputs for external initiates
available in mic
roprocessor based relays, eliminates the need for separate auxiliary relays in
the trip circuit that are needed with EM and SS relays for these functions. These functions
also need to be selective, such that breaker failure and autoreclosing is only initia
ted for
protective relay trips and not for manual and remote SCADA initiated trips. Programmable
logic within microprocessor based relays makes this selectivity relatively easy to accomplish
without additional external wiring.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Another consideration is th
e selection of the battery system voltage used to supply the
circuit breaker trip and close control circuits. Voltage levels of 125 V and above were often
used with EM and SS relay control circuits to ensure that any contaminants from the
surrounding envir
onment that accumulated on auxiliary relay contacts would not prevent
sufficient voltage from being delivered to the breaker trip or close coils, or other relays in
the control scheme. The designer has greater flexibility in selecting the DC control syste
voltage for microprocessor relay designs because the output contacts of microprocessor
relays are encapsulated so that contaminants from the surrounding environment are not an


Protection and Control Scheme Design

Protection and control scheme
designs using microprocessor relays involve elements of
digital logic design and coding as well as physical layout, interconnection, and wire routing.
The extensive protection and logic capabilities of microprocessor relays make it possible to
implement m
uch if not all of the desired protection and control scheme logic inside the
relay, thus eliminating a great number of physical wiring connections and auxiliary scheme
components such as contact multiplying relays, timers, communications interface relays,
target indicating relays, tripping rectifiers, blocking diodes, and control switches. However,
in replacing the physical complexity of old scheme components and wiring with protection
functions and digital logic inside the microprocessor relay, it is impo
rtant to keep the
internal logic and coding as simple as possible to avoid “sneak logic” (the digital equivalent
of a “sneak circuit”) and unwanted system responses. With the majority of the protection
and control scheme logic inside the microprocessor re
lay, external connections to and from
the relay such as voltage and current inputs, status inputs, and trip outputs can be designed
to provide direct paths and isolation between circuits.

When a pilot protection scheme application requires a microproces
sor relay to be interfaced
with external communications equipment, the pilot scheme logic can be implemented in the
microprocessor relay and functions such as transmitter keying and received signal status can
be implemented by interconnecting signaling con
tacts and digital inputs between the
microprocessor relay and the communications equipment. Many microprocessor relays are
equipped with direct digital or fiber optic communications channels which enable them to
communicate directly with each other. In t
his case, the only external communications
equipment between the relays may be a multiplexer, and all of the pilot scheme logic
including transmitter keying and received signal status may reside in the microprocessor

There is essentially no limit

to the number and variety of protection and control schemes that
can be designed using microprocessor relays. Specific designs can be and often are tailored
to meet the specific technical requirements or operating practices of the user. A major
ge for the engineer is to decide how many functions to design into the system and
how much functional redundancy is necessary and yet keep the design as simple as possible.
Additional design considerations and examples for relay scheme design using
rocessor relays can be found in
a report titled "Ancillary Protective and Control
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Functions Common to Multiple Protective Relays", by
roup K5

Substation Protection Subcommittee.


General Scheme Design


functional relays

essor technology has lead to the development of digital relays, which have
essentially replaced electromechanical and solid
state devices in power system protection.
Among their many advantages such as high accuracy, low maintenance, event recording
lity, and self
diagnostics, their ability to perform several protective functions in one
physical unit is particularly valuable. A single relaying unit, with all the protective logic
programmed inside it, has replaced several electromechanical and/or solid
state relays on a
typical protection panel, which used to perform various protective functions to protect a
power system element.

Installing a single multi
functional relaying unit instead of several discrete function relays
has significantly reduced pa
nel space and wiring and the associated cost. At the same time,
the relay scheme design has become both simpler for a purpose of creating relaying
drawings and more complex because of several protective functions, now being “hidden”
inside a box and, there
fore, necessitating continuous expertise development by engineers to
correctly design and apply these relays.

Practically, each element of the electric power system such as a bus, transformer, generator,
or power line may be protected utilizing a single m
icroprocessor multi
functional relay. The
programmable logic of the digital relay allows its customization for unique and special

Since all the protection logic is now internal to the relay, the unit is connected in the control
circuit via i
ts binary inputs for status of other elements of the power system such as a circuit
breaker or components of the control circuit and output contacts, which trip or block from
operating other power system elements or control circuit components. The unit is
connected to a power supply source and its analog inputs are connected to the protected
element’s voltages and currents.

Schematically, this relay, in general, is represented as a box, with connections to power
supply and other devices. The relay’s
logic, internal to the unit, is not shown, but typically
appears in the separate relay setting documentation. Because of that and the digital relay
being multi
functional, the schematic drawings are greatly simplified, in contrast with
electromechanical an
d solid
state relays.


Applying multiple output contacts

Electromechanical (EM) and solid state (SS) relays typically have a limited number of
output contacts, so for applications, such as breaker failure trips or bus protection trips,
contact multiplying

auxiliary (device 94) or lockout relays (device 86) are required to
facilitate multi
breaker tripping (and lockout if required).

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Microprocessor based relays generally have more output contacts than are required for basic
single breaker trip and close fun
ctions. Most microprocessor based relays can also be
equipped with additional output contacts by adding optional input/output boards. The
additional contacts can be used to provide direct tripping to multiple breakers to effect a bus
trip or ancillary func
tions. Multiple

output contact outputs also eliminates the
concern about tripping separate breaker trip coils or separate breakers that are supplied from
different battery systems. This often required the use of diodes to maintain isolation
en dc battery systems and separately fused dc circuits when EM or SS relays were

Direct breaker tripping also eliminates the delay incurred by an intermediate contact
multiplying or lockout relay, thereby reducing the time to interrupt a fault. This

may be
advantageous where total fault interrupting time must be reduced to preserve power system
stability or near critical customer loads that are sensitive to momentary voltage disturbances.

A lockout relay may also be used to provide redundant trippin
g, and to effect breaker
lockout where desired. Or additional microprocessor based relay output contacts can be used
to effect the lockout function (blocking breaker close) as well as tripping the breakers. This
can be accomplished by using inverted trip l
ogic (e.g., NOT TRIP) to hold a contact closed
in the breaker close circuit until the relay trip logic asserts, at which time the contact(s)
connected in the breaker close circuit(s) will open, preventing automatic or manual closing
until the relay contac
t is again closed. Latching or seal
in logic in the microprocessor based
relay can be used to maintain the open contact until some control action is used to reset the
latch in a manner similar to resetting a lockout relay. Alternatively, normally closed re
contacts can be connected in the breaker close circuit to
ffect the lockout function simply
by applying the trip logic with a latching or seal
in function.

Further tripping speed improvement can be accomplished by using high
speed solid state
relay c
ontacts that are available either standard, or as an option, on some microprocessor
based relays in place of, or in addition to, standard electromechanical contact outputs.

Multifunction microprocessor based relays generally have one or two output contact
programmed with the OR combination of multiple protective relay elements to effect
tripping one or two breakers or breaker trip coils. Testing the individual protective relay
elements can create a challenge, as described later in
section ???

of this docu
ment. When
available, spare output contacts can be programmed with individual protective relay
elements to isolate the individual functions for testing, eliminating the undesirable practice
of changing relay settings to test the relay. Taking this one ste
p further, these output
contacts could be individually wired to the breaker trip circuit to provide individual
protective element trip functions, providing both improved trip circuit dependability as well
as improved ease of testing.


Integration vs. sep

Almost all of the digital relays perform several, often all, protective functions for each of
power system elements. For example, a single relay can perform differential, impedance,
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


and overcurrent protective functions for a transmission line or d
ifferential, overcurrent, and
excitation protective functions for a transformer while utilizing older relaying
technologies would require about a dozen of relays for the line and half a dozen for the

Integrating protective functions into

a single digital relaying unit has significant advantages.
It frees up a lot of space on a relaying panel and reduces the amount of wiring and its
associated cost.

The single multi
functional relay offers a bigger package of functions as compared to the

only basic functions available in the discrete relays and allows choosing the ones most
suitable for a specific application.

The single unit’s common relaying logic supports all the protective functions available in the
relay, and the robust relaying pr
ogramming capabilities allow creating a new customized
logic for a unique application.

Since all the protective functions for a power system element are located in the same unit, it
simplifies setting the relay since it is just one and speeds up testing a
nd maintenance.

However, there are disadvantages associated with the integration. Should the single relaying
unit fail or be out of service for testing, no protective function is available. A common
algorithm or a setting mistake may affect all functio
ns, which are inter
dependent on each
other through the relaying logic.

Location of traditional backup protective and control functions such as breaker failure and
auto reclose in the same relaying unit as the main protective function also presents a
llenge should the single relaying unit fail or be out of service for testing.

At the same time, because of the variety of the protective functions in the same relaying
device, many of which are not used, both the protection engineer and field technician h
to be especially careful in setting the multi
functional relay and entering the settings into the
device to avoid undesired operations or relay non
response when it is called for action.

Without basic digital relaying logic standardization, there may
be a tendency by protection
engineers to utilize many or all of the relays’ capabilities to create unique and sneaky logics
in the digital relays, which could complicate the maintenance and testing work of field
personnel whereas no such a problem exists w
ith electromechanical relays.

disadvantages do not affect the discrete relays. If one of them fails or is out of service for
testing, there are others working in parallel or as a backup that are available to keep
protecting the power system element.



16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


As it is stated above, the main drawback of protecting equipment with a single multi
functional relay is that, should the relay fail, the affected equipment will be unprotected.
Another potential problem is associated with the relay’s inter
nal design and logic algorithm
when either of them may fail to correctly respond to an abnormal system condition or fault.

The most obvious solution is to employ another relay, which operates in parallel with the
main multi
functional relay or serves as
a backup and operates when the main relay fails or
does not respond to the system’s fault.

The issue associated with the multi
functional relay redundancy involves the degree of
separation of the two relays based on utilizing:


Same or different manufact


Same or different protective devices of the same manufacturer.


Same or different protection principle.

The simplest option is to apply two identical multi
functional relays, of the same
manufacturer. The benefits are increased dependability and c
saving design, setting the
relays, commissioning, and maintenance. However, the risks associated with utilizing the
same relays include sharing a potential hardware or software problem and an incorrect
setting in both relays, all of which may decrease
the reliability of the protection package.

Obviously, utilizing the relays of the two different manufacturers may greatly increase
dependability and overall reliability of the scheme. At the same time, this comes at the cost
of more complex design and mo
re expensive engineering and maintenance and additional

A good alternative is to utilize two relays of the same manufacturer, which are, nevertheless,
the products of different design and production lines and have a different hardware or
re or both. While this approach may somewhat complicate the design and setting the
relays, the familiarity with the relays of the same manufacturer will positively affect setting
the relays, their commissioning and maintenance, and, at the same time, will
avoid problems
associated with the identical relays’ hardware or software and duplicating incorrect settings.

Applying different protection principles greatly contributes to the dependability of
protection. For transmission line protection, for example,

impedance protection can be
employed in one relay unit and current differential function

in the other.

The impedance protection requires voltage potential. It may be affected by line loading and
power swings in the system. It can be utilized without a

communication channel in a step
distance scheme, but can be set to protect 80
90% of the line instantaneously and requires
coordination with the adjacent impedance protective zones.

The current differential protection, on the other hand, is voltage
pendent and does not
need voltage potential for operation. It is not affected by line loading and power swings in
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


the system. It protects 100% of the line and does not require coordination with other
protection zones; however, it requires a communication c
hannel to operate. Also, the
differential protection pickup needs to be set sufficiently high as to not operate for a line
charging current so that sensitivity of the differential protection may be lower that the
sensitivity of the impedance protection.

his comparison demonstrates that two different protective principles effectively
complement each other and should be considered for redundancy purposes.

Similarly, ground overcurrent protection can be utilized alongside the impedance protection
for transm
ission lines as it is more sensitive for high
resistance ground faults than a ground
impedance function.


Power supply considerations

M. Stojak/
Robert Frye

All microprocessor relays have power supplies to transform the station battery voltage or
other voltage such as an AC voltage into suitable processor and control voltages for
the electronics and microprocessors or the relay. The power supplies generally draw only a
few voltamps of load from the supply, and they are available in a variety of vo
ltages such as:
48, 125, & 250VDC as well as 120VAC.

Thoughtful consideration should be given to the source from which the power supply
voltage is to be obtained. Most utilities use the station or plant battery. The station battery
is usually the first
choice for supplying relay power supplies. It is generally designed to
supply a reliable source of 48, 125 or 250 volts that is resistant to transients and is at a
relatively immune to system disturbances. Some companies connect their station batteries
to inverters and thereby create a 120 VAC source that is used for relay and instrument power
supplies. These systems can be as reliable as the DC systems. The final choice for power
supply voltage is to use the station service supply or to use a voltage
transformer secondary.
Due to the fact that these voltages can reflect the system voltages during fault conditions i.e
drop to zero or drop to some value below the power supply threshold, these sources should
not be considered for relays performing protec
tive functions. However, relays that perform
strictly control functions have been successfully applied using the station service or voltage
transformers as a source i.e capacitor bank control relays.


Circuit overcurrent design

M. Stojak/
Robert Frye

en designing the power supply connections from the DC system to a microprocessor
relay, attention should be given not so much to protecting the relay but to protecting the DC
system from short circuits in the conductors to the relay or in the relay itself.

Many utilities
install a pair of fuses at the beginning of the power supply circuit where it leaves the DC
bus. The purpose of these fuses is to isolate any faults in the power supply branch circuit,
and to keep any problems from migrating up into other

critical circuits or even drain the
battery. The selection of the fuse’s current rating depends on utility practice, continuous
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


current capacity of the conductors, or the desire to coordinate with other fuses during short
circuits. In general, the size
is usually found to be between 3

30A. It must be remembered
that the current consumption of the power supply is usually in the milliamp range, and to
size fuses for overload protection of the power supply is not reasonable.

An alternate design that mus
t be considered is to provide no overcurrent protection to the
power supply. In this design, the power supply is connected directly to the tripping DC of a
circuit breaker. This design is occasionally used in applications where a single breaker and
r are protected by a single relay such as in a distribution or switchgear arrangement.
The thought is that if the power supply fails, the breaker will not trip anyway. The fault will
then be cleared by the fuses supplying the breaker’s tripping DC supply
. This design is only
to be used for the simplest of applications and should not be used on breakers that are being
tripped by multiple relays because a single fault in a relay power supply or conductors
should not disable a breaker.


Battery load creep

M. Stojak/
Robert Frye

Microprocessor relays add load to the station battery and they affect the battery design load
curve. In substations or power plants where microprocessor relays are replacing
electromechanical relays, the designer should consider t
hat as more new relays are added,
the continuous load on the battery and charger will gradually increase or “creep”. The net
result is that the once adequate station battery and/or battery charger may now not meet the
original design criteria. This is fu
rther complicated by the co requisite addition of other
electronics such as digital meters and digital communication equipment connected to the
protection battery.


Particular changes in circuit functionality

Rich Hunt


ux relays, diodes, timers


In conventional protection scheme especially when electro mechanical type protection is
used auxiliary relays, timer, diode are frequently used in the wide range of applications.

These elements are used to interface the output and input commands f
orm, and to the relays,
to build the logic for trip or interlock purposes, for selective trip matrix, for the trip (94) and
lockout (86) units, to monitor and signaling the status and operation of the protection relays.

The conventional scheme which build
s in this way often requires fare amount of internal
panel or rack wiring to connect various elements of the scheme together. While protection
system designed with Microprocessor based protection relays potentially could be build
without any timer, auxilia
ry relay or diodes. Microprocessor relay depend of the type and
make very often has scalable type hardware, quantity, voltage, type and duty of input and
output cards could be specified by application engineer prior to ordering and purchasing the
relay. In

addition most if is not all the microprocessor relays are well capable to be used to
develop the logic for wide range of application without use of any auxiliary relays. The
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


amount of internal wiring is significantly reduced which also reduces the hardwar
e checkout
of the protection scheme in comparison to the conventional scheme.

The suitability duty of the relay output contacts rating (make and break) has to be checked
when the relay contacts are used to trip the circuit breaker trip coil directly.
Heavy duty and
fast type of output contacts should be used for such a circuit, alternatively conventional trip
and lockout unit may still be used (94+86).

It is important to note that in the microprocessor relay the current drawn by relay input
ated input) when is energized is` very low, therefore binary input wetting voltage
threshold or when possible setting has to be verified by design application engineer to make
sure DC ground fault in protection scheme could not trigger the binary inputs.


trip coil monitors

For successful operation of a protection system, healthiness of the trip circuit is extremely
critical. If there is an undetected discontinuity in the trip circuit, a fault in the system will not
be able to be cleared in spite of b
eing correctly detected by a protection scheme. The fault
will have to be cleared by another protection upstream in the power system or a backup
breaker failure protection scheme, which could instigate unnecessary disturbances in the
system. The breaker fa
ilure protection activated as a result of such an “un
cleared” fault
condition could result in a loss of an entire bus section in a station and including possible
remote tripping.

Trip coil monitoring schemes are utilized for continuous supervision of bre
aker trip circuits
to detect possible wiring damage, loose terminal screws, poorly crimped terminal wiring,
circuit breaker coil open circuit conditions and loss of supply to the trip circuit. The
intention is to detect possible breaker trip circuit failur
es as early as possible and provide an
alarm to the system operators.

Trip circuit monitoring can be performed either using a standalone trip circuit supervision
relay or through the microprocessor based protection relay itself. Both schemes have their
vantages and disadvantages. The standalone trip circuit supervision relays provide reliable
supervision of the complete trip circuit and are capable of supervising the circuit breaker in
both open and closed states. However, such a scheme could mean additi
onal cost and
additional wiring. Some microprocessor based relays have a trip circuit supervision function
integrated into the protection relay. Such a scheme can usually monitor the circuit breaker in
closed state and requires a correctly sized external r
esistor to be included in the trip circuit in
order to monitor the circuit breaker in both open and closed states.

A trip coil monitoring scheme can be implemented in a microprocessor based relay using
two digital inputs and internal relay logic. An exam
ple scheme is shown in
Figure 2.6.1

below. A time delay will have to be introduced to the relay logic in such a scheme to prevent
erroneous pickup of the logic during the transition of circuit breaker states.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Alternatively, another trip coil monitoring s
cheme can be implemented in a
microprocessor relay using one digital input of the relay as shown in Figure 2.6.2. If an
advanced RTU system is utilized, the input can be wirelessly connected (softwired) to
SCADA or a relay output can be assigned to be wire
d to RTU for breaker trip coil
status indication to SCADA.

Figure 2.6.1 Trip coil monitoring scheme using two digital inputs of microprocessor relay

Figure 2.6.2 Trip coil monitoring scheme using one digital input of micro
processor relay


Breaker Failure Initiate

Regardless of the concept used in Breaker Failure (BF) scheme such as Breaker current,
Breaker image or combinations; in the conventional type scheme generally at least one stand
alone relay per circuit breaker
is used to perform the breaker fail function. The relay
supervising the correct performance of the trip circuit and circuit breaker in response to any
trip issued by protection elements during normal system operation. The supervision of
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


breaker fail elemen
ts or relay starts when protection relay trips the breaker which in the
same time should also send the Breaker failure Starts or Initiate command to BF relay.

From design point of view in the conventional scheme since breaker failure relay is stand
e relay and protection relay are mostly not multi functions for each relays, breaker
initiate has to be wired to BF relay. In addition some utility and designer do prefer to not use
the latched type trip command for BF initiate signals, for reduction of th
e risk of BF mal

operation in testing and maintenance or when BF operation is not required. In such cases an
additional circuit should be designed to convert latch type signal to temporary type.
Transformer mechanical protections are example of these kind

of trip commands.

In microprocessor based relay the design of BF initiate signal potentially could be simplified
to the great extend. Microprocessor relay are multifunction relay so BF Initiate signal for all
protection elements activated in the main rel
ay could be summarized (logical or gate) and
send to BF relay as one signal or if BF relay also is located inside the micro process relay
this signal could be an internal signal only, in either cases the circuitry get simplified by
reduction of number of
hardware elements used in the circuit.

Regarding the latched type command for BF initiate signal, if is preferred by utility the
signal could be converted to temporary signal without use of any additional component.


Sneak Circuit Elimination

Robert Frye

Sneak circuits are the unexpected paths along which current, energy, or logical sequence
flows in an unintended direction [1]. Sneak circuits are always “designed
in” by the
designer, and can have consequences ranging from a simple nuisance,
to a failure of a
critical system, or to loss of life. The sneak circuit may manifest itself immediately or it
may remain hidden for years until the correct set of circumstances occurs for it to appear.
The circuit based electrical world is not the sole
domain of sneak circuits. They can also be
found in mechanical, pneumatic, software, and digital “circuits.” The four types of sneak
circuits or sneak conditions as they are referred to are described below:


Sneak Path (also called a Sneak Circuit)

an u
nexplained path along which current,
thergy, or logical sequence flows in an unintended direction [1].


Sneak Timing

events occurring in an unexpected or conflicting sequence [1].


Sneak Label

incorrect or imprecise labeling of system functions (e.g., sy
stem inputs,
controls, displays, and buses) that may cause an operator to apply an incorrect stimulus
to the system[1].


Sneak Indication

Ambiguous or false displays of system operating conditions that may
cause the operator to take an undesired action[1]

To begin to eliminate digital sneaks in microprocessor relays, the designer must first
understand how, and in what order, the relay processes the programmable logic. Since every
element and word bit in the relay cannot be scanned and processed simultane
ously, the relay
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Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


will have some type of specific scanning order. This information is usually found in the
relay instruction manual, but the designer may have to refer to the factory for this
information. As an example, one manufacturer’s programmable log
ic controller processes
its logic top
bottom and left
right one rung at a time based on the logic ladder diagram.
Knowing and understanding the processing order is particularly important in designing
trouble free high speed or race control circuits
such as reclosing.

The preferred method of eliminating sneaks in the utility industry is to perform a systematic
inspection of the digital logic and the connected relay logic. This consists of performing a
systematic challenge of the system to perform it
s intended function under all circumstances
and a systematic challenge of the system to not perform any unintended actions. In the
checking for sneaks in this type of evaluation, it is customary for fuses, molded case circuit
breakers, and circuit

nect points to act as switches. Circuit disconnect points would
be test switches (such as PK type blocks, FT switches, and the like), wire disconnect points
on the back of relays or in wiring harnesses, sliding link terminal blocks, or other disconnect
ints that may tend to change the flow of current.

The systematic inspection method is a most basic method and has the tendency to overlook
potential sneaks. As electric utility microprocessor relay schemes become more complex, a
Topographic Approach to s
neak circuit analysis should be considered. This is the method
used by NASA, DOD, aircraft manufacturers, and others to evaluate complex digital,
software, and circuit systems. For further information concerning Topographic Sneak
Circuit Analysis, the re
ader should refer to reference [1].

Microprocessor relays when interfaced with the electrical control circuit world can create or
become part of external sneak circuits. Digital inputs on typical microprocessor relays draw
only 3
5mA of current. A circ
uit containing a relay coil or a switchboard indicating light
can be configured to assert relay’s digital input due to a blown fuse or misaligned switch.
Likewise, the paralleling of two digital inputs on a relay could easily unintentionally seal
the c
oil of an external control relay.

Some microprocessor control devices use thyristor based output “contacts.” These outputs
are not “air” contacts in the usual sense. Rather, they are a gated silicon controlled rectifier
or other electronic device that

is used to perform the function of an output contact. They are
usually employed by the manufacturer to obtain the desired 125 or 250VDC rating, or to
satisfy a space need within the microprocessor relay. These outputs can act as a switch in
one directio
n of current flow and a diode in the other direction. The designer should
carefully study the external circuit and microprocessor relay interface to ensure that a
current reversal due to a blown fuse or other event will not cause undesired results as a re
of current flowing backwards through and “open” output contact.


[1] American Institute of Aeronautics & Astronautics (AIAA) S
based Sneak Circuit Analysis (sca) Requirements.


Logic order in

Robert Frye

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


o design high speed controls such as reclosing or other complex logic schemes using
microprocessor relays, the designer may first need to understand how, and in what order, the
relay processes the programmable logic. Since every element and word bit in th
e relay
cannot be scanned and processed simultaneously, the relay will have some type of specific
scanning and processing order. This information is usually found in the relay instruction
manual, but the designer may have to refer to the factory for this i
nformation. As an
example, one manufacturer’s programmable logic controller processes its logic top
bottom and left
right one rung at a time based on the logic ladder diagram. Other
manufacturer’s relays process all logic within a specific time inte
rval, usually several times
in a power system cycle. During this interval, all inputs are scanned, internal and
intermediate logic is processed, and the resulting logic is applied to virtual or hardware
outputs, providing a deterministic operating time. Kn
owing and understanding the
processing order of microprocessor relays is particularly important in designing trouble free,
high speed, or race control logic.


Accelerated tripping


Choice of contacts



Don Sevcik

Target i
s still used the same way when the design is done using electromechanical relays
although it is a lot simpler to use. Targeting is used to indicate that a protection
element/function has operated after an event. In microprocessor relays there are
tection targets available from different functions in the device. This information is
tagged which becomes very useful when testing a protection scheme timing and
investigating an event. In the electromechanical relays the time
tag information is lack
The accuracy of the time tag depend on the clock/IRIG source how well the time source is
synchronized to a good reference.

The explanations of Shunt and Series Targets from the 1999 report are still valid in the
microprocessor design although these
terms usually are not used in microprocessor design.
Here is an example on how the explanations from 1999 report relate to microprocessor relay
scheme design:


A microprocessor relay use Out101 to trip a line breaker. The logic for the Trip equation
is set
as :


TRIP = 50P AND (21P1 OR (21P2 AND 2P)) OR 67GPI OR 67GPT.




According to 1999 report, the shunt targets are any of the relay elements such as the 50P,
21P1, 21P2, 2P.


According to 1999 report, the series target is OUT101 or TRIP.

Seal in
is no longer an issue in most modern microprocessor relay because their contact
outputs are typically rated for current drawn by tripping coil of a breaker for some period of

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999



Target Dropping

In the
microprocessor relay the target usually is indicate
d via an LED or

HMI interface in
the front of the relay. Nowadays most of the relay’s LED and HMI are user programmable
to fit criticality and information that need to be conveyed to technicians and engineers. Here
are a few examples of what modern micropr
ocessor can do:


LED color or blink rate can be used to indicate different level of targets based on
their usage.


HMI provides more descriptive information using text as oppose to on/off indication.

This information is viewable just by looking at the front

of the relay or utilizing a couple
navigation buttons on the relay. There is no longer mechanical/magnetic target dropping in
microprocessor relay scheme design.

The addition of microprocessor relay into an existing electromechanical tripping scheme can
e used for adding time reference for targets that comes from electromechanical relay by
wiring auxiliary contacts from the electromechanical relay outputs into the microprocessor
relay inputs.

Resetting of the target can be done via a button in the front
of the relay or via remote

or Local HMI


if necessary

There will be typically two kinds of resets.


reset usually is used for non
lockout type event/operation. The target clear
without requiring another signal as soon as the initiating c
ondition that causes the
operation goes away.


Latching usually is used for lockout type event/operation. The target is hold in place
even after the initiating condition that cause the operation goes away. It requires
another signal to be sent to clear/rese
t the target.


al target


Sequence of Events Records

A. Higdon

Microprocessor relays have the benefit of containing additional functions such as Sequence
of Events Records with very little additional cost. An events report can contain status of
y items along with a time stamp to the nearest millisecond for when each changed state.
Data such as relay power
up, protective relay element pickup and dropout, settings group
changes, input and output changes of state, and alarm changes of state can be
recorded in
these reports.

When electromechanical relays were the norm a target from the relay would drop indicating
which relay operated during a fault. This worked well for the first relay coil that operated,
but if the fault evolved from a phase to gro
und fault to a phase to phase fault triggering
additional relay coils to operate one seldom knew it. The second and third relay coil’s
targets would not drop since the fault current would get interrupted by the breaker opening.
Sequence of event records
give much better target info and show the full evolvement of the

The elements that trigger the events recorder in a microprocessor relay are programmed by
the user. For example, protective elements, inputs, and relay logic bits can be used to trigg
the event recorder upon their transition from a zero to a one. A trip output from the relay
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


also usually triggers the event recorder. The length of the recording can be also be
programmed into the relay but will be limited by the amount of memory in t
he relay. Once
the memory is full the oldest events will get erased as new events are recorded. Events
reports are accessible from the front panel, or for download over the LAN or WAN.

Sequence o
f events records are useful in the
testing phase as well as after the relay has been
placed in service. The report contains the exact sequence and timing of each event recorded
by the relay making it possible to verify correct tripping times occurred, the proper
protective elements operate
d, the pilot scheme functioned correctly with proper timing, and
the reclosing functioned correctly. This information can reveal trouble spots in a design
scheme or relay settings, and it can reveal why a relay misoperated. The oscillography
recorded dur
ing an actual fault can be saved and uploaded into a power system simulator for
future end to end relay testing. It can also be used in power system modeling software to
run simulations and verify relay settings.

With event recording available in micropro
cessor relays there is a wealth of information
available to the engineer with very little added cost and effort above installing the relay to
perform its protective duties and programming the record triggers. A lot of information can
be obtained with no a
dditional wiring having been completed.



Just like sequence of event recorder, targeting can also be used for oscillography or fault
records. This can be short term duration (in cycles) or long term duration (in minutes,
hours). This is

one of the feature modern microprocessor has advantage of
electromechanical relay. The oscillography can be part of the same device as the protection
relay unlike its electromechanical counter part where the recording device usually is another

Typically you want to trigger recording only for the element/targets that initiate tripping of a


SCADA functions

Bruce Mackie

SCADA (Supervisory Control and Data Acquisition) provides the means for utilities to control and

many substations from one or more control centers. SCADA has been an integral part of
the electric industry for many years. The advancement of microprocessor relays has drastically
changed the design of SCADA functions in terms of both control and monit



SCADA has been used to provide many control functions for electric utilities for many
years. Some of the more common control functions include opening and closing circuit
breakers, enabling and disabling reclosing functions for circu
it breakers, opening and
closing switches, changing voltage taps on regulators and tap changers. In the past, controls
were accomplished by the master SCADA unit at the control center sending a control
command to the RTU (remote terminal unit) at the subs
tation. Various communication
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Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


systems and protocols are used to accomplish this. The RTU is similar to a computer in
that it would usually have a CPU (central processing unit) and output board with contacts
used to open and close to perform the control

function. These contacts on the output board
were not robust enough to be used to open and close breakers so these contacts were used to
control interposing relays which had contacts that could be used in the device control circuit
possibly with the assi
stance of other auxiliary or lock
out relays.

The development of microprocessor relays has made significant changes to the design of
SCADA control circuits. In modern designs, the SCADA control signal can communicate
from the SCADA master unit to an ind
ividual microprocessor relay through the utility’s
chosen communication system and protocols. There are several methods the utility uses to
communicate the control signal to the relay. One of these methods includes using a
traditional RTU that uses a com
munication port that is connected to the relay to send the
signal rather than using an auxiliary relay. Another method is to use a TCPIP/Ethernet
switch to communicate to the relay. There are other methods that can also be chosen.
However once the micro
processor relay receives the control signal, then the relay can use
one or more of its output contacts to execute the control. The control of circuit breakers will
be examined in more detail in the next section.

The discussion of SCADA control must addr
ess the utility’s philosophy regarding
local/remote control switches. The local/remote control switch, if in the substation, needs to
be monitored by the microprocessor relay so it can block remote signals if needed.

One control feature that has not bee
n used before the advancement of microprocessor relays
is the ability to change relay setting groups. Since the SCADA master can communicate
directly to the microprocessor relay, the SCADA master can send a command to change the
relay setting group. This

provides the utility with far more flexibility to run their system
than ever before. The setting group can be changed for changing environments such as
configuration, weather, and the like.


Breaker control

Breaker control in its simplest form is the ab
ility to open and close the breaker. SCADA has
performed this control feature for many years in the method described earlier using the RTU
and interposing relays. Another aspect of breaker control is the enabling and disabling of
the reclosing function f
or the circuit breaker. It is often important to consider the reclosing
function of a circuit breaker when designing the SCADA trip circuit for a circuit breaker.

One traditional design for a SCADA trip circuit before microprocessor relays was to not

trip the circuit breaker but also to ensure the reclosing function of the circuit breaker
was disabled. The need for this type of feature was needed when the breaker status provided
the means to initiate the reclosing feature. In this type of design the

reclosing relay would
not be able to distinguish between a circuit breaker trip from protective relays where
reclosing is desired verses a SCADA trip where reclosing is not desired. In this case, the
design of the SCADA trip would include an additional c
ontact by means of the interposing
relays that would disable the reclosing feature by opening the reclosing path or disabling the
reclosing relay.

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Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


The use of microprocessor relays has simplified the design of the SCADA trip circuit mostly
by changing the

design from a hardware design to a software design. For instance the actual
contact from the microprocessor relay that is used to SCADA trip the circuit breaker could
also be used as the protective trip contact. In this method, no additional hardware de
sign is
needed to add the SCADA trip, since the protective trip will often be needed. The only
change is a change in the control equation of the output contact to ensure the SCADA
command is included. Some utilities may however desire an additional separ
ate output
contact to be used for the SCADA trip. As with traditional designs, it is important to ensure
the reclosing function of the circuit breaker is disabled when the SCADA trip is activated.
There are several methods to handle this in microprocesso
r relays. One method is to change
the reclose initiate signal from the breaker status to a protective trip only feature. In this
method only protective trips would initiate the reclosing feature and therefore the SCADA
trip would not activate the reclosi
ng feature. Another method is to include the SCADA trip
protocol point as an input in the reclosing lock
out equation. If the SCADA trip and the
reclose function reside in the same relay, then this application is very simple. If they are in
separate rel
ays, then the design will need to ensure these signals are handled properly
whether they are hard
wired or communicated via relay to relay protocols such as
IEC61850. Since these schemes are software based, extensive testing of the schemes is a
to ensure proper operation.

The SCADA close feature has similar considerations when moving from traditional designs
to a microprocessor based design. In traditional designs, the SCADA close contact from the
interposing relays had to be placed in the prop
er location in the close circuit to ensure the
breaker was not closed improperly. Some of these situations that had to be considered in
locating the closing contact in the closing circuit were the lock
out relay contacts , the use of
synch checking relays
, as well as the control handle contacts. Depending upon the design of
the microprocessor circuit most of these variables can be handled via software. One
decision that needs to be made is whether the same contact will be used for the reclose
circuit and

the SCADA close contact. If the same contact is used, then the software will
have to be programmed to ensure proper operation of the reclose and SCADA close

Another control issue regarding circuit breaker control via SCADA is the enabling and
sabling of the reclose feature. Before microprocessor relays, this feature was often
controlled similar to other controls with the SCADA master sending a signal to the RTU
which used interposing relays to block the path of the reclose circuit. If there i
connection to the microprocessor that handles the reclosing function, then a simple SCADA
command to the relay can disable or enable the reclosing feature of the relay.

The change of designs when installing microprocessor relays can lead to un
foreseen issues.
Great care should be taken when designing the revised scheme to ensure the actual operation
of the sceme matches the desired operation. In addition to great care during the design, it is
important to communicate with all parties affecte
d to ensure they are satisfied with the
scheme. The parties also need to know who to contact if they see issues with the design.
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Once again, it should be pointed out that such For example, one utility in their design of
disabling the reclosing feature of

the circuit breaker used the actual status of the reclose
out state as the indication for the control point of the reclose enable and disable point.
Since the microprocessor relay would lock
out the reclose if it went through its entire trip

cycle for a permanent fault, the reclose feature would show it disabled. However

when the line was tested via SCADA close command, the reclose feature would be ready to
activate and go through its cycle again which is not the desire of the SCADA operato
They would have wanted to disabled the reclose feature but could not since it already
appeared to be disabled.



SCADA metering is another task that has been made far easier with the arrival of
microprocessor relays. Before microprocessor rel
ays or meters, the ability to meter at the
control center required additional transducers which would convert the typical relay current
or voltage signals of 5 amps or 120volts to 1mA signals that could be handled by the RTU.
The RTU would use its analog
to digital cards to convert these 1mA signals to a digital
count that would be sent to the control center. In addition to the additional equipment that
was required to meter current, volts, and power there was also the issue of calibration. The
RTU analo
g cards or the transducers would drift and become inaccurate so calibration had to
be performed on a regular basis.

The microprocessor relay makes metering very easy. The currents and voltages that are
used for the protection features can be monitored
and sent to the control center via any
number of SCADA protocols such as the popular protocol, DNP. This removes the need for
additional equipment such as transducers. Since the microprocessor does not require
calibration and the signals are digital beyo
nd the relay, there is no need to calibrate.

In addition to the common metering quantities such as current and voltage, the
microprocessor relay also allows one to meter other quantities that required additional
equipment to measure in the past. Some of t
hese special quantities include frequency and
battery voltage.



Similar to metering, the monitoring of various points at the substation has also been made
more convenient with microprocessor relays. In traditional designs, points that needed t
o be
monitored such as breaker status had to be wired into the digital input board of the RTU. In
designs with microprocessor relays, the points that are needed to be monitored can be wired
into the input contacts of the relay. These points are often wir
ed into the relay for protective
relays so additional wiring is not needed in these cases. Once the point is wired into the
relay, then the input contact needs to have its protocol location mapped to
SCADA so it can
be monitored.

One of t
he most common


used in the industry is RS

(also known as

This interface
is employed to connect RTU with various IEDs in an electrical
sbstation. It
has important advantages
compared to

the popular serial RS
232 interface.
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


n media of the RS



pair cable

and is based
differential principle (measures the voltage difference between the wires rather than
the voltages of the send and receive wires
to a reference point) thus

immune to noise and

ted u
p to 3000 ft and with speeds higher
than 100 kb/s.

This is especially useful when relays are located
ple control houses in


he interface
allows multiple

sor based relays for
example) to be daisy chained

fewer ports on the RTU
will be

needed to
monitor all the
digital relays in a substation. Various protocols are supported by this interface such as
, MirrorBits,

, etc.

Apart from the analog

data which can

transmitted to the Control Center

the following are some example

of critical binary
information which can dispatched to the
Control Center
, thus limiting the
amount of wiring
from panel to panel and to the RTU: breaker status,
trip coil fail alarm,

enable/disable/reset/lockout, breaker low pressure/low energy, breaker pole disagreement,
breaker failure, loss of potential, etc.

any relay word bit can be mapped to the
protocol used and send
remotely to the Contro
l Center c
omputer via RTU using a
or a TCPIP/Ethernet


Additional monitoring

Adi Mulawarman

This section suggests monitoring on each circuit level as oppose to overall substation battery
monitoring system. Monitoring
or targeting loss of DC source to a specific tripping circuit is
important because without it, the intended tripping action from that circuit will not happen.
Whether monitoring should be done on each circuits or not depends on the design of the
tripping s
cheme. Having primary and secondary tripping circuits may justify not having to
monitor each own DC source. The example below show an example where monitoring Loss
of DC source is an important part of the tripping scheme.

Due to possibility of
s in understanding of the definition


DC Trip Bus
”, the
following definition will apply:

DC Trip Bus

: The use of a common wire to send tripping through several aux tripping
relays from several protection functions that has the same zone of protection
(trip the same
set of breakers plus more).


A substation with breaker and a half scheme is used for this example (figure 1). One side of
the bus (#2) is protected by 3 breakers. For any bus differential fault on that bus, breaker
failure on an
y of those 3 breakers, the same 3 breakers will be tripped. By using a common
tripping wire to collect the trip outputs from one bus differential relays and 3 breaker
failures we save some wiring costs. This common tripping wire is commonly called trip bus
The trip bus will then be wired to 3 auxiliary relays for each breaker for tripping into the trip
coil and breaker failure initiate signal.

The above design can be duplicated for redundancy purposes calling it primary and
secondary trip buses. If each t
rip busses are fed from separate DC fuses that will be better.
Additional local/remote monitoring/targeting should be recommended because the loss of
DC source on both trip busses will result in no tripping for multiple functions. Although this
effect is m
ore significant in the trip bus design, in general monitoring DC source to any
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


tripping circuit can easily be by microprocessor relay logic with minimum amount of wiring
and should be considered.

See figure … for example.

Attach is an example how Loss of

DC Source (or my company call it Loss of DC Trip Bus
Voltage) can easily be implemented in microprocessor relay.


Figure 2 shows how the DC positive and negative is wired into the digital input for
microprocessor relay.


Figure 3 shows how the Boolean i
nput is simply passed to the output. If the output is high
than the DC trip Bus voltage is healthy otherwise it is dead. Remote EMS or local LED
targeting in microprocessor can be done easily by using the same Boolean variable.
Substation operator can then

take appropriate action to remedy the situation.


attery voltage

(see section 4.2)


reaker monitoring

In traditional designs, monitoring of the breaker status was carried out using the station RTU
with the breaker status signals wired to the digital i
nput board of the RTU. In present
designs using microprocessor relays, the breaker signals that are required to be monitored
can be directly wired to the digital inputs of the microprocessor based relays. Once these
signals are connected to the digita
l inputs of the relays, the status of the input signals can be
provided to the SCADA system through the communication mechanism between the
protection relays and the SCADA system. Some of these signals, for example the breaker
auxiliary contacts, are often

used in protective relay applications and therefore additional
wiring will not be required to monitor such signals using a separate device such as an RTU.

The modern IEDs are not only used for protection applications, but also for providing
control, mon
itoring and metering for equipment as required. Most importantly, the
monitoring and metering data can be easily made available to the station SCADA system. In
protection and control scheme designs using microprocessor based relays, breaker open and

status and breaker alarms such as breaker gas pressure low, breaker spring
mechanism failure, breaker dc supply failure, and breaker ac supply failure can be connected
to the digital inputs of the relay. This information can be made available to the SCADA

also be used for making intelligent decisions such as blocking protection trips when gas
pressure in the breaker is extremely low or opening the breaker when the gas pressure goes
below a certain level.


Transducer replacement

(see section 4.2)




function integration considerations

Jay Sp

function relays were straightforward to test; multi
function relays are more challenging. The
additional functionality can distort the results and confuse the test technicia
n, especially if testability
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Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


is not considered up front in the scheme design. Further, the ease of testing with modern test sets can
actually create unwarranted confidence in the results

Before any testing begins, the type of testing should be considere
d. Acceptance, commission, and
scheduled testing are all different, have different requirements and are performed for different
reasons. Acceptance testing is typically focused on a single relay and completed when the relay is
received from the manufactu
rer. Commission testing is the most common type of testing performed
by utilities and is often done just prior to the relay going into service. This type of testing may also
involve functional testing. Scheduled testing is a debated topic with modern re
lays, but typically
happens in the course of time and depends on the philosophy of each utility. That said, the following
are general considerations for testing multi
function relays. In testing a multi
function relay, it is
advantageous to first test the

metering functions. This action ensures the inputs are properly wired
and the relay is properly configured for the correct potential and current ratios.

Once the metering is checked, testing of the protective elements can be performed, usually one at a
ime. Methods vary on how to configure a relay to allow testing without disturbing protection
settings. One method is to program an independent output to each element, such as Output 7 to a
time overcurrent element and Output 8 to a Zone 2 ground element.

If the application is simple, the
relay may contain enough spare contacts. The disadvantage with this method is that most of the time
suitable spare contacts are not available and the relay settings likely have to be modified during the
testing process.

Also, the actual outputs that perform the trip function, and the elements that input
into the trip equation need to be tested to confirm functionality.

Another method is to use, if available, the multi
function relay’s built
in event recording and
event capability. These features of the relay, along with pre
defined tests can be used to
target certain trip elements. The advantage of this method is the protection settings need not be
changed. The disadvantage is being sure the trip elemen
t of interest’s response is not disturbed by
other elements that might respond to the same test input.

Regardless of which method is used, it is critical that the “As
left settings” match the “As
settings.” The testing procedures need to include st
eps and text to remind the test technician of this
critical need.

Functional testing verifies the trip path from external inputs, through the relay, and to outputs, such
as the circuit breaker. Many a relay has passed element testing and been put into
service, only to
discover later that the trip circuit itself was not configured properly, or the scheme design was just
wrong. For pilot schemes, satellite end
end functional testing provides the opportunity to not only
test the local trip path, but to

confirm pilot equipment operability, such as carrier time delays, signal
levels, ancillary equipment operation, etc. Functional testing is further described in section 5.5.


Test switches

Don Lukach

mechanical (EM) relays were usually singl
e function devices with fixed trip output
terminals. For example terminals 1 and 10 would be the trip function. Most contained built
in test switches or paddles that could be removed for isolation. The EM relays that did not
have these features were eit
her hard wired directly to other devices or wired to a separate
test device. Styles of test devices varied among manufactures, but were all installed to allow
adequate and safe testing.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Microprocessor (uP) relays are typically not simple, one
function de
vices with built
in test
switches. Many relays are utilized in cross
functional groups like line protection, breaker
failure, and reclosing in the same relay. Outputs are now programmable. Functions that use
to be built in discrete relay logic are now c
ontained within the single device or devices with
established communication paths. However, test switches as applied to a uP relay are
fundamentally no different than their predecessors.

Test switches can be though of as a functional device that interr
upts a signal to or from the
tested device, that may allow the input of voltage or current, and that may be used for
sensing of relay outputs. With this concept, the function can be a traditional physical switch
on the panel, a slide
link terminal block,
or possibly a software enabled block within the
logic (although no usage reports have yet surfaced of this concept). All the different
methods have advantages and disadvantages and depend on several factors, such as panel
space, utility practice, technici
an safety, etc. The use of external devices is not new.
However, how test switches are configured with the usage of uP relays is new and can cause
problems for the trip circuit designer.

Panel density has increased many
fold with the advent of uP relays
. What use to take
several panels will now fit into a single panel. The EM relays generally contained large
studs where the uP relays have smaller terminals or even plug
type connectors. What use to
be easy to “clip
on” test leads to a relay’s terminals

is now more difficult and possibly less
safe. Another issue is that with the unlimited ability to configure the uP relays, the manner
that the test switches are connected may impact functional groups. For example, a typical
EM relay would have a single
switch, probably in the case. This switch was “assigned” to a
single function. The uP relay may be configured for Trip 1 as a line function and Trip 2 as a
breaker failure function as an example. If a shared test switch is used for both trips, then
tended system impacts could occur during testing.

Overall, what worked for an EM scheme may not work for a uP scheme. The design
engineers must be cognizant of and maintain the testing function, ability of the craft to
adequately test, and to assure te
sting can be performed in a safe manner when changing to a
uP scheme.

NOTE: additional material submitted from another contributor

Adi Mulawarman

In a fully automated design, microprocessor relay logic will use very little or no test
switches. However ma
intainability and testing need to be part of the early design. It is useful
to still maintain the idea of test switches but not in a physical sense but virtually. A virtual
test switch can be part of the logic of each trip/close Boolean equation allowing t
to test the function without taking the relay out of service. A consistent practice will be
needed as to decide whether the sending or receiving only or may be both devices will have
this virtual test switch logic. Another factor that needs to be

considered is the amount of
logic that the microprocessor can handle. There is a limit of Boolean variable, control bit
that are available in the relay (after other usage such as auto
manual, trip/close, on
off, etc.)
These all have to be taken into accou
nt during the early engineering design. A good design
feature is to display the bit status that will be on the incoming and outgoing sides of the
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


virtual switch in addition to the switch status itself. Proper documentation of logic diagram
is very importa
nt for maintenance and testing.

Procedures or labels are needed to clarify operator that a single microprocessor relay are
now doing multifunction targeting thus turning off a malfunctioned relay may in fact turn
off not just 1 protection function but 2 o
r more. The same principle applied with testing.
Injecting test current/voltage in microprocessor relay is going to affect all the
function/element in that relay. It is recommended to take the relay off line from the system
before testing it.



Don Lukach

mechanical (EM) relays were usually installed in a punched
out designed panel.
Changes were difficult and usually required cutting new holes for the additional relays.
Recent relay design provides for such things as a 19” rack
design. Physical additions are
easier as spare plates, affixed with screws, are replaced with additional relays.

The Microprocessor (uP) relays are complex and usually have many more functions that are
ever enabled. They are inherently expandable. For
example, take an existing EM step
distance two
zone scheme that needed to be upgraded to a carrier based four
zone scheme.
With an EM scheme, additional relays and possibly a new panel would be needed. With an
existing uP scheme, most of the changes are
software settings within existing relays and the
additional carrier equipment would probably fit into the rack
type panel with little


Power up / power down considerations

Adi Mulawarman


ogic states, output states

It is important to kn
ow the status of the Boolean bit during power loss. There 2 types of
memory that are used to store this type of information in general. A volatile type reset to a
preset value thus not maintaining the last state received by the device. A non
volatile type
will remember the last state received by the device. Depending on the security vs.
dependability of your trip/close or block trip/close requirement you may use one but not the


Network Consideration

The power up/down of the relay device is not the
only one affecting your Boolean bits. In
some design where the relays are communicating to each other through an Ethernet
switch/router the network equipment status and high traffic condition causing lock up/ port
down condition should be taken into consid
eration. Temporary loss of network equipment
due to loss of power or port down condition will prevent data being passed to each other or
additional delay. Most of communication protocol used on this physical layer network has a
detection method that can be

used to indicate that network/message quality has been lost.
The same consideration for power up/down can be applied here.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999



Functional testing

Don Lukach

Functional testing is a broad subject and is applied differently by different utilities. For th
purposes of this report, functional testing is defined as the testing required to

verify the
entire trip path, including the trip logic.

The EM relays were usually single function devices that were combined with other relays to
form logical tripping sch
emes. Relay logic was discrete and depicted as such on schematics.
The level of understanding by engineers and field personnel developed over decades of
usage. The uP relays changed all that when the discrete logic was replaced in a single relay.
was easy to follow changed to a “black box”.

The requirement for functional testing remains the same. The change is that the engineer
needs to be able to convey the logic design to anybody that needs to know it and also needs
to design testability withi
n the design. This requires knowledge of how
a technician

performs functional testing and for the craft in how to interpret the logic. For example, if

blocks the directional unit contacts of an EM overcurrent relay with a wood

stick, the

same directional blocking function would need to be considered in the uP scheme,
especially if the logic is contained in software. Likewise, if the engineer issues Boolean
expressions or a logic diagram, the technician needs to have the knowledge to read


Drawings, settings, and testing philosophies vary widely. The point is that everybody within
a company needs to use a system where the logic is conveyed from the engineers to the field
and the design is such that functional testing as defined by t
he company can be adequately
and safely performed.


Frequency of testing vs. self
check alarming

Jay Sp

Electrical mechanical relays tend to drift out of calibration, microprocessor relays seldom
do. Instead their failures tend to be
, th
at is, some function within them just
quits working. The good news is they typically have self
diagnostics built in and will alarm
on such failures.

However, it is good to remember self
diagnostics cannot check everything.
diagnostics are limited to

the digital realm. They cannot check the analog input
circuitry, that is, the CT and PT inputs. They also cannot check the health of the output
contacts. The analog inputs can be checked by comparing the meter output to another
source. And the output
contacts can, somewhat, be checked by reviewing event reports
(somewhat because the event report will not help if the physical contacts are burned out).
That said, is regular maintenance still required or should users only respond to self
alarms? M
ore and more utilities

after a relay is configured, tested, and put in service

choosing to only test relays if the relay configuration changes or the relay’s self
check alarm

They have determined more frequent testing has few benefits and man
y negatives:
Testing requires time and effort, and there is always a risk a technician will accidently
introduce changes to the relay that result in later problems.

16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


Firmware control is an important consideration relative to testing frequency since firmwa
updates are often at the mercy of this testing interval. Manufacturers update firmware to
resolve bugs in the previous version and to add additional functionality and features. But
manufacturers need to understand a utility may not be able to or choos
e to keep relays
updated with the latest firmware and may not even track what version of firmware is on a
relay. Critical updates need to be communicated differently than evolutionary updates,
perhaps via a PAL (Product Advisory Letter), to trigger a spec
ial maintenance check.

Finally, with this extended testing interval good records and reference material have become
even more critical. Manufacturer’s reference material needs to be updated as functionality
and features are added to relays via firmware c
hanges (new manuals or addendums). This
would include updating the recommended testing procedures and examples.





Mike Stojak

& Robert Frye

Aside from protective settings, microprocessor relays use programmable logic to complete
arious functions and operations. Some of the logic is user programmable while other parts
are static. With the use of a combination of relay inputs and outputs, the logic can be
programmed to mimic legacy hard wired schemes; in effect, duplicating the op
eration of
such schemes within the relay itself. Aside from the obvious advantages in reducing wiring
and panel space, it becomes more efficient to design and implement new schemes which
increase security and functionality in protective applications

e also allowing for various
controls and supervision. In addition, the overall speed for detection and scheme operation
is increased due to the fact that decisions are being made at microprocessor time intervals as
opposed to combinations of coil pickups
and contact operations. Logic within the relay
consists of variables, timers and latches from which functionality is programmed via
combinations of these elements using conventional logic gates: AND, OR, NOT etc…
Internal “hardwired” logic exists to crea
te certain protective element functions which are
usually designed to provide


primary function for which the relay was created. Since
variables can have many combinations of elements defining their state, there is a need to
document the logic scheme in

a manner which allows for ease of use and understanding. In
some microprocessor relays, variables are grouped and stored by function type, such as:
Timer1, Timer2, Timer3 or Latch1, Latch2, Latch3. In other relays, specific timers may be
assigned to fun
ction with certain other elements, and are grouped and stored together with
those elements, such as: Phase OC 1, Phase Timer1 or Latch1, Latch1 Timer. Due to this
fact, it could be difficult to see the overall function that is being constructed logically
the relay by just viewing the settings report. Documenting this data in the form of logic
diagrams provides a clear method of representing the operation of the various schemes
logically constructed within the relay. In essence, what was once repre
sented by series and
parallel combinations of open and closed contacts, coils, resistors, lights and diodes on an
elementary diagram is now represented as a combination of elements on a logic diagram.
Although elementary diagrams are still needed to diagr
am the wired schematics connecting
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


microprocessor relay inputs and outputs, the logic diagram is a necessary to completely
describe the functions of the microprocessor relay in the scheme.


sub and inter
sub communications

Jim O’Brien

Scheme design

utilizing microprocessor relays frequently includes relay to relay
communication such as an IEC61850 substation scheme or a transmission line pilot
protection scheme. Having a full understanding of the scheme would include an
understanding of that relay t
o relay communication.

Drawing details must show how the communications are accomplished and to what other
devices the communications are being made. For intra
sub communications this can be a
part of the referencing of circuits from one drawing to anothe
r within the substation. Inter
sub communications can be more difficult to reference since the remote substation might be
owned by another entity. In this case, as much detail specifying the remote substation relay
should be included in the drawings.

A de
scription of the scheme can be included in station operating instructions to further
document how the scheme functions. This can be helpful in the case where communication
engineering and substation engineering are separate entities and their design drawin
gs aren’t
fully integrated.


Operating instructions

Mike Stojak

Operating instructions are usually provided to those who will be operating specific
equipment and its associated protection and control schemes. With the advent of the use of
or based relaying, many control functions have been incorporated in the
devices. Since the device is monitoring system analog data such as voltages and currents,
local users may need instructions on how to access the data via the front panel of the device
in order to verify switching. Often, pushbuttons available on the relays will be programmed
to take the place of functional switches eliminating the available “visible operation” that a
device such as a cutout once provided. Users will have to rely on
cutout status indication
from lights or front panel display messages to determine that a certain operation was
performed properly. Those operating from remote locations with access to a SCADA data
view may not see much difference in their displays or how
they operate for control, but they
may see new alarms associated with the devices and possibly more data since there is often
more calculated data available from these devices. One significant change in remote
operations occurs in how operators will need
to respond to issues involving microprocessor
devices such as the Relay Fail alarm. Since many functions may be programmed in the
single device, instructions need to describe what protections and controls have been affected
and what actions to take to min
imize the risk of undesirable events. Since microprocessor
relays perform multiple protective functions, targeting for the different types of operations
will need to be addressed. Most microprocessor relays come with target indicating lights;
some have f
ixed labeling and programming while others have user defined labeling and
programming, or a combination of both. An advantage to digital targeting is that targets can
be brought back through SCADA which may give the remote operator enough information
16 Working Group Draft 2.6

Relay Scheme Design Using Microprocessor Relays

A Supplement to Relay

Trip Circuit Design by IEEE PSRC 1999


to a
llow him to choose between different courses of action. An example would be a fault
locating indication which would allow the operator to sectionalize smaller parts of the


Operator alarms

Jim O’Brien

The microprocessor relays have the capa
bility to provide operator information such as
breaker status, breaker alarms, communications alarms, etc. The relay settings contain the
alarm information: however, the settings probably aren’t available to the operator or if they
are there might not be s
ufficient comments for the operator to know. A complete listing of
the alarms available within each relay is required in the documentation for station operation
so the operator can know what to expect from each relay. This information should be one of

items included in the station operating instructions.



Raluca Lascu


Lessons learned